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| To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com Renesas Technology Corp. Customer Support Dept. April 1, 2003 Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. Hitachi Single-Chip Microcomputer H8S/2276 Series H8S/2277F-ZTATTM HD64F2277 Hardware Manual ADE-602-224 Rev. 1.0 12/26/01 Hitachi Ltd. Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products. Preface This LSI is a single-chip microcomputer made up of the H8S/2000 CPU with an internal 32-bit architecture as its core, and the peripheral functions required to configure a system. This LSI is equipped with ROM, RAM, a bus controller, data transfer controller (DTC), three types of timers, a serial communication interface (SCI), an A/D converter, FLEXTM*1 decoder II, and I/O ports as on-chip supporting modules. This LSI is suitable for use as an embedded processor for high-level control systems. Its on-chip ROM is flash memory (F-ZTATTM*2) that provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. This is particularly applicable to application devices with specifications that will most probably change. Note: *1 FLEXTM is a trademark of Motorola. *2 F-ZTATTM is a trademark of Hitachi, Ltd. Target Users: This manual was written for users who will be using the H8S/2276 Series in the design of application systems. Members of this audience are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8S/2276 Series to the above audience. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of the instruction set. Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual. * In order to understand the details of a register when its name is known The addresses, bits, and initial values of the registers are summarized in Appendix B, Internal I/O Registers. Example: Bit order: The MSB is on the left and the LSB is on the right. Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.hitachisemiconductor.com/ H8S/2276 Series manuals: Manual Title H8S/2276 Series Hardware Manual H8S/2600 Series, H8S/2000 Series Programming Manual ADE No. This manual ADE-602-083 Users manuals for development tools: Manual Title C/C++ Complier, Assembler, Optimized Linkage Editor User's Manual Simulator Debugger Users Manual Hitachi Embedded Workshop Users Manual ADE No. ADE-702-247 ADE-702-037 ADE-702-231 Application Notes: Manual Title H8S Series Technical Q & A ADE No. ADE-502-059 Contents Section 1 1.1 1.2 1.3 Overview ........................................................................................................... Overview............................................................................................................................ Internal Block Diagrams.................................................................................................... Pin Description .................................................................................................................. 1.3.1 Pin Arrangements ................................................................................................. 1.3.2 Pin Functions in Each Operating Mode................................................................ 1.3.3 Pin Functions........................................................................................................ 1 1 6 7 7 8 12 Section 2 2.1 CPU..................................................................................................................... 17 17 17 18 19 19 20 25 26 26 27 28 30 31 31 33 34 34 35 37 44 45 45 45 48 52 52 53 54 57 57 i 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Overview............................................................................................................................ 2.1.1 Features ................................................................................................................ 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 2.1.3 Differences from H8/300 CPU............................................................................. 2.1.4 Differences from H8/300H CPU.......................................................................... CPU Operating Modes ...................................................................................................... Address Space.................................................................................................................... Register Configuration ...................................................................................................... 2.4.1 Overview .............................................................................................................. 2.4.2 General Registers.................................................................................................. 2.4.3 Control Registers.................................................................................................. 2.4.4 Initial Register Values .......................................................................................... Data Formats...................................................................................................................... 2.5.1 General Register Data Formats ............................................................................ 2.5.2 Memory Data Formats.......................................................................................... Instruction Set.................................................................................................................... 2.6.1 Overview .............................................................................................................. 2.6.2 Instructions and Addressing Modes ..................................................................... 2.6.3 Table of Instructions Classified by Function........................................................ 2.6.4 Basic Instruction Formats..................................................................................... 2.6.5 Notes on Use of Bit-Manipulation Instructions.................................................... Addressing Modes and Effective Address Calculation ..................................................... 2.7.1 Addressing Mode.................................................................................................. 2.7.2 Effective Address Calculation.............................................................................. Processing States ............................................................................................................... 2.8.1 Overview .............................................................................................................. 2.8.2 Reset State ............................................................................................................ 2.8.3 Exception-Handling State .................................................................................... 2.8.4 Program Execution State ...................................................................................... 2.8.5 Bus-Released State ............................................................................................... 2.8.6 Power-Down State................................................................................................ 57 Basic Timing...................................................................................................................... 58 2.9.1 Overview .............................................................................................................. 58 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 58 2.9.3 On-Chip Supporting Module Access Timing....................................................... 60 2.9.4 External Address Space Access Timing............................................................... 61 2.10 Usage Note ........................................................................................................................ 62 2.10.1 STM/LDM Instruction.......................................................................................... 62 2.9 Section 3 3.1 3.2 3.3 3.4 3.5 MCU Operating Modes ................................................................................ 63 Overview............................................................................................................................ 63 3.1.1 Operating Mode Selection.................................................................................... 63 3.1.2 Register Configuration ......................................................................................... 64 Register Descriptions......................................................................................................... 64 3.2.1 Mode Control Register (MDCR).......................................................................... 64 3.2.2 System Control Register (SYSCR) ...................................................................... 65 Operating Mode Descriptions............................................................................................ 66 3.3.1 Mode 4.................................................................................................................. 66 3.3.2 Mode 5.................................................................................................................. 66 3.3.3 Mode 6.................................................................................................................. 67 3.3.4 Mode 7.................................................................................................................. 67 Pin Functions in Each Operating Mode ............................................................................ 68 Memory Map in Each Operating Mode............................................................................. 68 Exception Handling........................................................................................ 71 71 71 72 72 74 74 74 76 76 77 78 79 80 81 Overview............................................................................................................................ 4.1.1 Exception Handling Types and Priority ............................................................... 4.1.2 Exception Handling Operation ............................................................................. 4.1.3 Exception Sources and Vector Table ................................................................... Reset .................................................................................................................................. 4.2.1 Overview .............................................................................................................. 4.2.2 Reset Sequence..................................................................................................... 4.2.3 Interrupts after Reset ............................................................................................ 4.2.4 State of On-Chip Supporting Modules after Reset Release ................................. Traces ................................................................................................................................ Interrupts............................................................................................................................ Trap Instruction ................................................................................................................. Stack Status after Exception Handling.............................................................................. Notes on Use of the Stack.................................................................................................. Section 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Section 5 5.1 ii Interrupt Controller ........................................................................................ 83 Overview............................................................................................................................ 83 5.1.1 Features ................................................................................................................ 83 5.2 5.3 5.4 5.5 5.6 5.1.2 Block Diagram...................................................................................................... 5.1.3 Pin Configuration ................................................................................................. 5.1.4 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 5.2.1 System Control Register (SYSCR) ...................................................................... 5.2.2 Interrupt Priority Registers A to G, I to K, O (IPRA to IPRG, IPRI to IPRK, IPRO) ................................................................. 5.2.3 IRQ Enable Register (IER) .................................................................................. 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 5.2.5 IRQ Status Register (ISR) .................................................................................... Interrupt Sources................................................................................................................ 5.3.1 External Interrupts................................................................................................ 5.3.2 Internal Interrupts ................................................................................................. 5.3.3 Interrupt Exception Handling Vector Table ......................................................... Interrupt Operation ............................................................................................................ 5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 5.4.2 Interrupt Control Mode 0...................................................................................... 5.4.3 Interrupt Control Mode 2...................................................................................... 5.4.4 Interrupt Exception Handling Sequence .............................................................. 5.4.5 Interrupt Response Times..................................................................................... Usage Notes ....................................................................................................................... 5.5.1 Contention between Interrupt Generation and Disabling..................................... 5.5.2 Instructions that Disable Interrupts ...................................................................... 5.5.3 Times when Interrupts are Disabled..................................................................... 5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... DTC Activation by Interrupt ............................................................................................. 5.6.1 Overview .............................................................................................................. 5.6.2 Block Diagram...................................................................................................... 5.6.3 Operation .............................................................................................................. 84 84 85 85 85 86 88 88 89 90 90 92 92 95 95 98 100 102 103 104 104 105 105 105 106 106 106 107 Section 6 6.1 PC Break Controller (PBC) ......................................................................... 109 109 109 110 111 111 111 112 112 114 114 115 115 iii 6.2 6.3 Overview............................................................................................................................ 6.1.1 Features ................................................................................................................ 6.1.2 Block Diagram...................................................................................................... 6.1.3 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 6.2.1 Break Address Register A (BARA) ..................................................................... 6.2.2 Break Address Register B (BARB)...................................................................... 6.2.3 Break Control Register A (BCRA) ...................................................................... 6.2.4 Break Control Register B (BCRB) ....................................................................... 6.2.5 Module Stop Control Register C (MSTPCRC).................................................... Operation ........................................................................................................................... 6.3.1 PC Break Interrupt Due to Instruction Fetch........................................................ 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 PC Break Interrupt Due to Data Access ............................................................... Notes on PC Break Interrupt Handling ................................................................ Operation in Transitions to Power-Down Modes ................................................ PC Break Operation in Continuous Data Transfer ............................................... When Instruction Execution is Delayed by One State ......................................... Additional Notes .................................................................................................. 115 116 116 117 118 119 Section 7 7.1 Bus Controller.................................................................................................. 121 121 121 122 123 124 124 124 125 126 129 131 132 134 134 135 136 136 137 139 139 139 140 141 149 151 151 151 153 154 154 156 157 157 157 158 7.2 7.3 7.4 7.5 7.6 7.7 Overview............................................................................................................................ 7.1.1 Features ................................................................................................................ 7.1.2 Block Diagram...................................................................................................... 7.1.3 Pin Configuration ................................................................................................. 7.1.4 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 7.2.1 Bus Width Control Register (ABWCR) ............................................................... 7.2.2 Access State Control Register (ASTCR).............................................................. 7.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 7.2.4 Bus Control Register H (BCRH).......................................................................... 7.2.5 Bus Control Register L (BCRL)........................................................................... 7.2.6 Pin Function Control Register (PFCR) ................................................................ Overview of Bus Control................................................................................................... 7.3.1 Area Partitioning .................................................................................................. 7.3.2 Bus Specifications ................................................................................................ 7.3.3 Memory Interfaces................................................................................................ 7.3.4 Interface Specifications for Each Area................................................................. 7.3.5 Chip Select Signals............................................................................................... Basic Bus Interface............................................................................................................ 7.4.1 Overview .............................................................................................................. 7.4.2 Data Size and Data Alignment ............................................................................. 7.4.3 Valid Strobes ........................................................................................................ 7.4.4 Basic Timing ........................................................................................................ 7.4.5 Wait Control ......................................................................................................... Burst ROM Interface ......................................................................................................... 7.5.1 Overview .............................................................................................................. 7.5.2 Basic Timing ........................................................................................................ 7.5.3 Wait Control ......................................................................................................... Idle Cycle........................................................................................................................... 7.6.1 Operation .............................................................................................................. 7.6.2 Pin States in Idle Cycle......................................................................................... Bus Release........................................................................................................................ 7.7.1 Overview .............................................................................................................. 7.7.2 Operation .............................................................................................................. 7.7.3 Pin States in External Bus Released State............................................................ iv 7.8 7.9 7.7.4 Transition Timing................................................................................................. 7.7.5 Usage Note ........................................................................................................... Bus Arbitration .................................................................................................................. 7.8.1 Overview .............................................................................................................. 7.8.2 Operation .............................................................................................................. 7.8.3 Bus Transfer Timing ............................................................................................ 7.8.4 External Bus Release Usage Note ........................................................................ Resets and the Bus Controller............................................................................................ 159 160 160 160 160 161 161 161 163 163 163 164 165 166 166 167 168 169 169 169 170 171 172 173 173 175 176 179 180 181 182 184 185 186 187 188 190 190 Section 8 8.1 8.2 8.3 8.4 8.5 Data Transfer Controller (DTC) ................................................................ Overview............................................................................................................................ 8.1.1 Features ................................................................................................................ 8.1.2 Block Diagram...................................................................................................... 8.1.3 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 8.2.1 DTC Mode Register A (MRA)............................................................................. 8.2.2 DTC Mode Register B (MRB) ............................................................................. 8.2.3 DTC Source Address Register (SAR) .................................................................. 8.2.4 DTC Destination Address Register (DAR) .......................................................... 8.2.5 DTC Transfer Count Register A (CRA) .............................................................. 8.2.6 DTC Transfer Count Register B (CRB) ............................................................... 8.2.7 DTC Enable Registers (DTCER) ......................................................................... 8.2.8 DTC Vector Register (DTVECR) ........................................................................ 8.2.9 Module Stop Control Register A (MSTPCRA).................................................... Operation ........................................................................................................................... 8.3.1 Overview .............................................................................................................. 8.3.2 Activation Sources................................................................................................ 8.3.3 DTC Vector Table ................................................................................................ 8.3.4 Location of Register Information in Address Space ............................................ 8.3.5 Normal Mode........................................................................................................ 8.3.6 Repeat Mode ........................................................................................................ 8.3.7 Block Transfer Mode............................................................................................ 8.3.8 Chain Transfer...................................................................................................... 8.3.9 Operation Timing ................................................................................................. 8.3.10 Number of DTC Execution States........................................................................ 8.3.11 Procedures for Using DTC ................................................................................... 8.3.12 Examples of Use of the DTC................................................................................ Interrupts............................................................................................................................ Usage Notes ....................................................................................................................... Section 9 9.1 9.2 I/O Ports ............................................................................................................ 191 Overview............................................................................................................................ 191 Port 1.................................................................................................................................. 194 v 9.2.1 Overview .............................................................................................................. 9.2.2 Register Configuration ......................................................................................... 9.2.3 Pin Functions........................................................................................................ 9.3 Port 3.................................................................................................................................. 9.3.1 Overview .............................................................................................................. 9.3.2 Register Configuration ......................................................................................... 9.3.3 Pin Functions........................................................................................................ 9.4 Port 4.................................................................................................................................. 9.4.1 Overview .............................................................................................................. 9.4.2 Register Configuration ......................................................................................... 9.4.3 Pin Functions........................................................................................................ 9.5 Port 7 [Internal I/O Port].................................................................................................... 9.5.1 Overview .............................................................................................................. 9.5.2 Register Configuration ......................................................................................... 9.5.3 Pin Functions........................................................................................................ 9.6 Port A................................................................................................................................. 9.6.1 Overview .............................................................................................................. 9.6.2 Register Configuration ......................................................................................... 9.6.3 Pin Functions........................................................................................................ 9.6.4 MOS Input Pull-Up Function ............................................................................... 9.7 Port B ................................................................................................................................. 9.7.1 Overview .............................................................................................................. 9.7.2 Register Configuration ......................................................................................... 9.7.3 Pin Functions........................................................................................................ 9.7.4 MOS Input Pull-Up Function ............................................................................... 9.8 Port C ................................................................................................................................. 9.8.1 Overview .............................................................................................................. 9.8.2 Register Configuration ......................................................................................... 9.8.3 Pin Functions in Each Mode ................................................................................ 9.8.4 MOS Input Pull-Up Function ............................................................................... 9.9 Port D................................................................................................................................. 9.9.1 Overview .............................................................................................................. 9.9.2 Register Configuration ......................................................................................... 9.9.3 Pin Functions in Each Mode ................................................................................ 9.9.4 MOS Input Pull-Up Function ............................................................................... 9.10 Port E ................................................................................................................................. 9.10.1 Overview .............................................................................................................. 9.10.2 Register Configuration ......................................................................................... 9.10.3 Pin Functions in Each Mode ................................................................................ 9.10.4 MOS Input Pull-Up Function ............................................................................... 9.11 Port F ................................................................................................................................. 9.11.1 Overview .............................................................................................................. 9.11.2 Register Configuration ......................................................................................... vi 194 195 197 203 203 204 206 208 208 209 209 210 210 211 213 214 214 214 218 219 220 220 221 223 226 227 227 228 230 232 233 233 234 236 237 238 238 239 241 242 243 243 244 9.11.3 Pin Functions........................................................................................................ 9.12 Port G................................................................................................................................. 9.12.1 Overview .............................................................................................................. 9.12.2 Register Configuration ......................................................................................... 9.12.3 Pin Functions........................................................................................................ 246 248 248 249 251 Section 10 16-Bit Timer Pulse Unit (TPU).................................................................. 253 10.1 Overview............................................................................................................................ 10.1.1 Features ................................................................................................................ 10.1.2 Block Diagram...................................................................................................... 10.1.3 Pin Configuration ................................................................................................. 10.1.4 Register Configuration ......................................................................................... 10.2 Register Descriptions......................................................................................................... 10.2.1 Timer Control Register (TCR) ............................................................................. 10.2.2 Timer Mode Register (TMDR) ............................................................................ 10.2.3 Timer I/O Control Register (TIOR) ..................................................................... 10.2.4 Timer Interrupt Enable Register (TIER) .............................................................. 10.2.5 Timer Status Register (TSR) ................................................................................ 10.2.6 Timer Counter (TCNT) ........................................................................................ 10.2.7 Timer General Register (TGR) ............................................................................ 10.2.8 Timer Start Register (TSTR)................................................................................ 10.2.9 Timer Synchro Register (TSYR).......................................................................... 10.2.10 Module Stop Control Register A (MSTPCRA).................................................... 10.3 Interface to Bus Master...................................................................................................... 10.3.1 16-Bit Registers.................................................................................................... 10.3.2 8-Bit Registers...................................................................................................... 10.4 Operation ........................................................................................................................... 10.4.1 Overview .............................................................................................................. 10.4.2 Basic Functions .................................................................................................... 10.4.3 Synchronous Operation ........................................................................................ 10.4.4 Buffer Operation .................................................................................................. 10.4.5 PWM Modes ........................................................................................................ 10.4.6 Phase Counting Mode .......................................................................................... 10.5 Interrupts............................................................................................................................ 10.5.1 Interrupt Sources and Priorities............................................................................ 10.5.2 DTC Activation .................................................................................................... 10.5.3 A/D Converter Activation .................................................................................... 10.6 Operation Timing .............................................................................................................. 10.6.1 Input/Output Timing ............................................................................................ 10.6.2 Interrupt Signal Timing ........................................................................................ 10.7 Usage Notes ....................................................................................................................... 253 253 257 258 259 260 260 264 266 273 275 278 278 279 280 281 282 282 282 284 284 285 291 293 296 301 307 307 308 308 309 309 313 317 vii Section 11 8-Bit Timers (TMR) ...................................................................................... 327 11.1 Overview............................................................................................................................ 11.1.1 Features ................................................................................................................ 11.1.2 Block Diagram...................................................................................................... 11.1.3 Register Configuration ......................................................................................... 11.2 Register Descriptions......................................................................................................... 11.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1).......................................................... 11.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1) ............................... 11.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1)................................ 11.2.4 Timer Control Registers 0 and 1 (TCR0, TCR1) ................................................. 11.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1).................................. 11.2.6 Module Stop Control Register A (MSTPCRA).................................................... 11.3 Operation ........................................................................................................................... 11.3.1 TCNT Increment Timing...................................................................................... 11.3.2 Compare Match Timing ....................................................................................... 11.3.3 Timing of Overflow Flag (OVF) Setting.............................................................. 11.3.4 Operation with Cascaded Connection .................................................................. 11.4 Interrupts............................................................................................................................ 11.4.1 Interrupt Sources and DTC Activation................................................................. 11.4.2 A/D Converter Activation .................................................................................... 11.5 Sample Application ........................................................................................................... 11.6 Usage Notes ....................................................................................................................... 11.6.1 Contention between TCNT Write and Clear........................................................ 11.6.2 Contention between TCNT Write and Increment ................................................ 11.6.3 Contention between TCOR Write and Compare Match ...................................... 11.6.4 Switching of Internal Clocks and TCNT Operation............................................. 11.6.5 Interrupts and Module Stop Mode........................................................................ 327 327 328 329 330 330 330 331 331 334 336 337 337 337 339 339 340 340 340 341 342 342 343 344 344 346 Section 12 Watchdog Timer (WDT).............................................................................. 347 12.1 Overview............................................................................................................................ 12.1.1 Features ................................................................................................................ 12.1.2 Block Diagram...................................................................................................... 12.1.3 Pin Configuration ................................................................................................. 12.1.4 Register Configuration ......................................................................................... 12.2 Register Descriptions......................................................................................................... 12.2.1 Timer Counter (TCNT) ........................................................................................ 12.2.2 Timer Control/Status Register (TCSR) ................................................................ 12.2.3 Reset Control/Status Register (RSTCSR) (WDT0 Only) .................................... 12.2.4 Pin Function Control Register (PFCR) ................................................................ 12.2.5 Notes on Register Access ..................................................................................... 12.3 Operation ........................................................................................................................... 12.3.1 Watchdog Timer Operation.................................................................................. 12.3.2 Interval Timer Operation...................................................................................... viii 347 347 348 349 350 351 351 351 356 357 358 359 359 360 12.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ......................... 12.4 Interrupts............................................................................................................................ 12.5 Usage Notes ....................................................................................................................... 12.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 12.5.2 Changing Value of PSS and CKS2 to CKS0........................................................ 12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 12.5.4 Internal Reset in Watchdog Timer Mode ............................................................. 361 362 362 363 363 363 363 364 Section 13 Serial Communication Interface (SCI)..................................................... 365 13.1 Overview............................................................................................................................ 13.1.1 Features ................................................................................................................ 13.1.2 Block Diagram...................................................................................................... 13.1.3 Pin Configuration ................................................................................................. 13.1.4 Register Configuration ......................................................................................... 13.2 Register Descriptions......................................................................................................... 13.2.1 Receive Shift Register (RSR)............................................................................... 13.2.2 Receive Data Register (RDR) .............................................................................. 13.2.3 Transmit Shift Register (TSR).............................................................................. 13.2.4 Transmit Data Register (TDR) ............................................................................. 13.2.5 Serial Mode Register (SMR)................................................................................ 13.2.6 Serial Control Register (SCR).............................................................................. 13.2.7 Serial Status Register (SSR)................................................................................. 13.2.8 Bit Rate Register (BRR)....................................................................................... 13.2.9 Smart Card Mode Register (SCMR) .................................................................... 13.2.10 Module Stop Control Registers B and C (MSTPCRB, MSTPCRC).................... 13.3 Operation ........................................................................................................................... 13.3.1 Overview .............................................................................................................. 13.3.2 Operation in Asynchronous Mode........................................................................ 13.3.3 Multiprocessor Communication Function............................................................ 13.3.4 Operation in Clocked Synchronous Mode ........................................................... 13.4 SCI Interrupts .................................................................................................................... 13.5 Usage Notes ....................................................................................................................... 365 365 367 368 369 370 370 370 371 371 372 375 378 382 389 390 392 392 394 405 413 421 423 Section 14 FLEXTM Roaming Decoder II..................................................................... 433 14.1 Overview............................................................................................................................ 14.1.1 Features ................................................................................................................ 14.1.2 System Block Diagram......................................................................................... 14.1.3 Functional Block Diagram.................................................................................... 14.2 SPI Packets ........................................................................................................................ 14.2.1 Packet Communication Initiated by the Host....................................................... 14.2.2 Packet Communication Initiated by the FLEXTM decoder II ............................... 14.2.3 Host-to-Decoder Packet Map ............................................................................... 433 433 434 436 437 437 438 440 ix 14.2.4 Decoder-to-Host Packet Map ............................................................................... 14.3 Host-to-Decoder Packet Descriptions................................................................................ 14.3.1 Checksum Packet.................................................................................................. 14.3.2 Configuration Packet............................................................................................ 14.3.3 Control Packet ...................................................................................................... 14.3.4 All Frame Mode Packet........................................................................................ 14.3.5 Operator Messaging Address Enable Packet........................................................ 14.3.6 Roaming Control Packet ...................................................................................... 14.3.7 Timing Control Packet ......................................................................................... 14.3.8 Receiver Line Control Packet .............................................................................. 14.3.9 Receiver Control Configuration Packets.............................................................. 14.3.10 Frame Assignment Packets .................................................................................. 14.3.11 User Address Enable Packet ................................................................................ 14.3.12 User Address Assignment Packets ....................................................................... 14.4 Decoder-to-Host Packet Descriptions................................................................................ 14.4.1 Block Information Word Packet .......................................................................... 14.4.2 Address Packet ..................................................................................................... 14.4.3 Vector Packet........................................................................................................ 14.4.4 Message Packet .................................................................................................... 14.4.5 Roaming Status Packet ......................................................................................... 14.4.6 Receiver Shutdown Packet ................................................................................... 14.4.7 Status Packet ........................................................................................................ 14.4.8 Part ID Packet....................................................................................................... 14.5 Application Notes.............................................................................................................. 14.5.1 Receiver Control .................................................................................................. 14.5.2 Message Building ................................................................................................. 14.5.3 Building a Fragmented Message .......................................................................... 14.5.4 Operation of a Temporary Address ...................................................................... 14.5.5 Using the Receiver Shutdown Packet .................................................................. 14.6 Timing Diagrams (Reference Data) .................................................................................. 14.6.1 SPI Timing............................................................................................................ 14.6.2 Start-up Timing .................................................................................................... 14.6.3 Reset Timing ........................................................................................................ 442 442 442 445 448 449 451 451 454 455 455 459 460 461 462 463 464 465 470 470 473 474 476 478 478 481 483 486 488 491 491 493 494 Section 15 A/D Converter ................................................................................................. 495 15.1 Overview............................................................................................................................ 15.1.1 Features ................................................................................................................ 15.1.2 Block Diagram...................................................................................................... 15.1.3 Pin Configuration ................................................................................................. 15.1.4 Register Configuration ......................................................................................... 15.2 Register Descriptions......................................................................................................... 15.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 15.2.2 A/D Control/Status Register (ADCSR)................................................................ x 495 495 496 497 498 499 499 500 15.3 15.4 15.5 15.6 15.2.3 A/D Control Register (ADCR)............................................................................. 15.2.4 Module Stop Control Register A (MSTPCRA).................................................... Interface to Bus Master...................................................................................................... Operation ........................................................................................................................... 15.4.1 Single Mode (SCAN = 0) ..................................................................................... 15.4.2 Scan Mode (SCAN = 1) ....................................................................................... 15.4.3 Input Sampling and A/D Conversion Time.......................................................... 15.4.4 External Trigger Input Timing ............................................................................. Interrupts............................................................................................................................ Usage Notes ....................................................................................................................... 502 503 504 505 505 507 509 510 511 511 Section 16 RAM ................................................................................................................... 517 16.1 Overview............................................................................................................................ 16.1.1 Block Diagram...................................................................................................... 16.1.2 Register Configuration ......................................................................................... 16.2 Register Descriptions......................................................................................................... 16.2.1 System Control Register (SYSCR) ...................................................................... 16.3 Operation ........................................................................................................................... 16.4 Usage Note ........................................................................................................................ 517 517 518 518 518 519 519 Section 17 ROM ................................................................................................................... 521 17.1 Overview............................................................................................................................ 17.1.1 Block Diagram...................................................................................................... 17.1.2 Register Configuration ......................................................................................... 17.2 Register Descriptions......................................................................................................... 17.2.1 Mode Control Register (MDCR).......................................................................... 17.3 Operation ........................................................................................................................... 17.4 Overview of Flash Memory............................................................................................... 17.4.1 Features ................................................................................................................ 17.4.2 Block Diagram...................................................................................................... 17.4.3 Mode Transitions.................................................................................................. 17.4.4 On-Board Programming Modes ........................................................................... 17.4.5 Flash Memory Emulation in RAM....................................................................... 17.4.6 Differences between Boot Mode and User Program Mode.................................. 17.4.7 Block Configuration ............................................................................................. 17.5 Pin Configuration .............................................................................................................. 17.6 Register Configuration ...................................................................................................... 17.7 Register Descriptions......................................................................................................... 17.7.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 17.7.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 17.7.3 Erase Block Register 1 (EBR1)............................................................................ 17.7.4 Erase Block Register 2 (EBR2)............................................................................ 17.7.5 RAM Emulation Register (RAMER) ................................................................... 521 521 522 522 522 522 524 524 525 526 527 529 530 531 532 533 534 534 537 538 538 539 xi 17.8 17.9 17.10 17.11 17.12 17.13 17.14 17.15 17.7.6 Flash Memory Power Control Register (FLPWCR) ............................................ 17.7.7 Serial Control Register X (SCRX) ....................................................................... On-Board Programming Modes ........................................................................................ 17.8.1 Boot Mode............................................................................................................ 17.8.2 User Program Mode ............................................................................................. Programming/Erasing Flash Memory................................................................................ 17.9.1 Program Mode...................................................................................................... 17.9.2 Program-Verify Mode .......................................................................................... 17.9.3 Erase Mode........................................................................................................... 17.9.4 Erase-Verify Mode ............................................................................................... Protection........................................................................................................................... 17.10.1 Hardware Protection............................................................................................. 17.10.2 Software Protection .............................................................................................. 17.10.3 Error Protection .................................................................................................... Flash Memory Emulation in RAM.................................................................................... Interrupt Handling when Programming/Erasing Flash Memory ....................................... Flash Memory Programmer Mode .................................................................................... 17.13.1 Socket Adapter Pin Correspondence Diagram ..................................................... 17.13.2 Programmer Mode Operation............................................................................... 17.13.3 Memory Read Mode............................................................................................. 17.13.4 Auto-Program Mode ............................................................................................ 17.13.5 Auto-Erase Mode.................................................................................................. 17.13.6 Status Read Mode................................................................................................. 17.13.7 Status Polling........................................................................................................ 17.13.8 Programmer Mode Transition Time..................................................................... 17.13.9 Notes on Memory Programming.......................................................................... Flash Memory and Power-Down States............................................................................ 17.14.1 Note on Power-Down States ................................................................................ Flash Memory Programming and Erasing Precautions ..................................................... 540 541 542 542 547 549 549 550 552 552 554 554 555 556 558 560 560 561 563 564 567 569 571 572 572 573 574 574 575 Section 18 Clock Pulse Generator .................................................................................. 581 18.1 Overview............................................................................................................................ 18.1.1 Block Diagram...................................................................................................... 18.1.2 Register Configuration ......................................................................................... 18.2 Register Descriptions......................................................................................................... 18.2.1 System Clock Control Register (SCKCR) ........................................................... 18.2.2 Low-Power Control Register (LPWRCR)............................................................ 18.3 System Clock Oscillator .................................................................................................... 18.3.1 Connecting a Crystal Resonator ........................................................................... 18.3.2 External Clock Input ............................................................................................ 18.4 Duty Adjustment Circuit.................................................................................................... 18.5 Medium-Speed Clock Divider........................................................................................... 18.6 Bus Master Clock Selection Circuit .................................................................................. xii 581 581 582 582 582 583 587 587 588 592 592 592 18.7 Subclock Oscillator............................................................................................................ 592 18.8 Subclock Waveform Shaping Circuit................................................................................ 594 18.9 Note on Crystal Resonator................................................................................................. 594 Section 19 Power-Down Modes ...................................................................................... 595 19.1 Overview............................................................................................................................ 19.1.1 Register Configuration ......................................................................................... 19.2 Register Descriptions......................................................................................................... 19.2.1 Standby Control Register (SBYCR) .................................................................... 19.2.2 System Clock Control Register (SCKCR) ........................................................... 19.2.3 Low-Power Control Register (LPWRCR)............................................................ 19.2.4 Timer Control/Status Register (TCSR)................................................................ 19.2.5 Module Stop Control Register (MSTPCR) .......................................................... 19.3 Medium-Speed Mode ........................................................................................................ 19.4 Sleep Mode........................................................................................................................ 19.4.1 Sleep Mode........................................................................................................... 19.4.2 Clearing Sleep Mode ............................................................................................ 19.5 Module Stop Mode ............................................................................................................ 19.5.1 Module Stop Mode ............................................................................................... 19.5.2 Usage Note ........................................................................................................... 19.6 Software Standby Mode .................................................................................................... 19.6.1 Software Standby Mode ....................................................................................... 19.6.2 Clearing Software Standby Mode ........................................................................ 19.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode .. 19.6.4 Software Standby Mode Application Example.................................................... 19.6.5 Usage Notes.......................................................................................................... 19.7 Hardware Standby Mode ................................................................................................... 19.7.1 Hardware Standby Mode...................................................................................... 19.7.2 Hardware Standby Mode Timing ......................................................................... 19.8 Watch Mode ...................................................................................................................... 19.8.1 Watch Mode ......................................................................................................... 19.8.2 Clearing Watch Mode .......................................................................................... 19.8.3 Usage Notes.......................................................................................................... 19.9 Subsleep Mode .................................................................................................................. 19.9.1 Subsleep Mode ..................................................................................................... 19.9.2 Clearing Subsleep Mode ...................................................................................... 19.10 Subactive Mode ................................................................................................................. 19.10.1 Subactive Mode.................................................................................................... 19.10.2 Clearing Subactive Mode ..................................................................................... 19.11 Direct Transition................................................................................................................ 19.11.1 Overview of Direct Transition.............................................................................. 19.12 o Clock Output Disabling Function................................................................................... 19.13 Usage Notes ....................................................................................................................... 595 599 599 599 601 602 604 605 606 607 607 607 608 608 609 610 610 610 611 611 612 612 612 613 614 614 614 615 615 615 615 616 616 616 617 617 617 618 xiii 19.13.1 19.13.2 19.13.3 19.13.4 19.13.5 19.13.6 I/O Port Status ...................................................................................................... Current Dissipation during Oscillation Stabilization Wait Period ....................... DTC Module Stop ................................................................................................ On-Chip Supporting Module Interrupt................................................................. Writing to MSTPCR............................................................................................. Entering Subactive/Watch Mode and DTC Module Stop .................................... 618 618 618 618 618 619 Section 20 Electrical Characteristics.............................................................................. 621 20.1 Power Supply Voltage and Operating Frequency Range .................................................. 20.2 Electrical Characteristics ................................................................................................... 20.2.1 Absolute Maximum Ratings................................................................................. 20.2.2 DC Characteristics................................................................................................ 20.2.3 AC Characteristics................................................................................................ 20.2.4 A/D Conversion Characteristics ........................................................................... 20.2.5 Flash Memory Characteristics.............................................................................. 20.3 Operational Timing............................................................................................................ 20.3.1 Clock Timing........................................................................................................ 20.3.2 Control Signal Timing.......................................................................................... 20.3.3 Bus Timing ........................................................................................................... 20.3.4 Timing of On-Chip Supporting Modules ............................................................. 621 622 622 623 627 632 633 635 635 636 637 642 Appendix A Instruction Set.............................................................................................. 645 A.1 A.2 A.3 A.4 A.5 A.6 Instruction List................................................................................................................... Instruction Codes ............................................................................................................... Operation Code Map.......................................................................................................... Number of States Required for Instruction Execution ...................................................... Bus States During Instruction Execution .......................................................................... Condition Code Modification............................................................................................ 645 669 683 687 701 715 Appendix B Internal I/O Register .................................................................................. 721 B.1 B.2 Addresses........................................................................................................................... 721 Functions............................................................................................................................ 727 Appendix C I/O Port Block Diagrams.......................................................................... 813 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 xiv Port 1 Block Diagrams ...................................................................................................... Port 3 Block Diagrams ...................................................................................................... Port 4 Block Diagram........................................................................................................ Port 7 Block Diagrams ...................................................................................................... Port A Block Diagrams...................................................................................................... Port B Block Diagram ....................................................................................................... Port C Block Diagram ....................................................................................................... Port D Block Diagram ....................................................................................................... Port E Block Diagram........................................................................................................ 813 816 820 821 825 826 827 828 829 C.10 Port F Block Diagrams ...................................................................................................... 830 C.11 Port G Block Diagrams...................................................................................................... 836 Appendix D Pin States ....................................................................................................... 840 D.1 Port States in Each Processing State.................................................................................. 840 Appendix E Appendix F Timing of Transition to and Recovery from Hardware Standby Mode ............................................................... 843 Product Code Lineup ................................................................................. 844 Appendix G Package Dimensions.................................................................................. 845 xv xvi Section 1 Overview 1.1 Overview The LSI is a microcomputer (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Hitachi's proprietary architecture, and equipped with the on-chip peripheral functions necessary for system configuration. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. On-chip peripheral functions required for system configuration include data transfer controller (DTC) bus masters, ROM and RAM memory, 16-bit timer-pulse unit (TPU), 8-bit timer (TMR), watchdog timer (WDT), serial communication interface (SCI), A/D converter, FLEXTM*1 decoder II, and I/O ports. The on-chip ROM is single-power-supply flash memory (F-ZTATTM* 2) with a capacity of 128 kbytes. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching has been speeded up, and processing speed increased. Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or external expansion mode. The features of the LSI are shown in table 1.1. Notes: *1 FLEXTM is a trademark of Motorola. *2 F-ZTATTM is a trademark of Hitachi, Ltd. 1 Table 1.1 Item CPU Overview Specification * General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * High-speed operation suitable for realtime control Maximum clock rate: 13.5 MHz High-speed arithmetic operations (at 13.5 MHz operation) 8/16/32-bit register-register add/subtract: 74 ns 16 x 16-bit register-register multiply: 1480 ns 32 / 16-bit register-register divide: 1480 ns * Instruction set suitable for high-speed operation Sixty-five basic instructions 8/16/32-bit move/arithmetic and logic instructions Unsigned/signed multiply and divide instructions Powerful bit-manipulation instructions * Two CPU operating modes Normal mode: 64-kbyte address space (not available in the LSI) Advanced mode: 16-Mbyte address space Bus controller * * * * * * * Address space divided into 8 areas, with bus specifications settable independently for each area Chip select output possible for areas 0 to 3 Choice of 8-bit or 16-bit access space for each area 2-state or 3-state access space can be designated for each area Number of program wait states can be set for each area Burst ROM directly connectable External bus release function Can be activated by internal interrupt or software Multiple transfers or multiple types of transfer possible for one activation source Transfer possible in repeat mode, block transfer mode, etc. Request can be sent to CPU for interrupt that activated DTC Data transfer controller (DTC) * * * * 2 Item 16-bit timer-pulse unit (TPU) Specification * * * * * * 3-channel 16-bit timer on-chip Pulse I/O processing capability for up to 6 pins' Automatic 2-phase encoder count capability 8-bit up-counter Two time constant registers Two-channel connection possible Watchdog timer or interval timer selectable Can operate on subclock (1 channel only) Asynchronous mode or synchronous mode selectable Multiprocessor communication function LSB first/MSB first selectable SCI3 is dedicated to the FLEXTM decoder II interface Resolution: 10 bits Input: 8 channels 9.9 s minimum conversion time (at 13.5 MHz operation) Single or scan mode selectable Sample and hold circuit A/D conversion can be activated by external trigger or timer trigger 8-bit timer (TMR) 2 channels Watchdog timer * (WDT) x 2 channels * Serial communication interface (SCI) x 3 channels A/D converter * * * * * * * * * * FLEXTM decoder II * * * I/O ports Memory * * * On-chip FLEXTM decoder II Conforms to FLEXTM protocol revision 1.9 Decoding capability: 1600, 3200, 6400 bits/second Decoding phase: Any-phase, single-phase 60 I/O pins, 8 input-only pins Flash memory High-speed static RAM ROM 128 kbytes RAM 16 kbytes Product Name H8S/2277, H8S/2277R 3 Item Interrupt controller Specification * * * * Nine external interrupt pins (NMI, IRQ0 to IRQ7) IRQ6 is a dedicated interrupt for the FLEXTM decoder II 36 internal interrupt sources Eight priority levels settable Supports debugging functions by means of PC break interrupts Two break channels Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Subclock operation (subactive mode, subsleep mode, watch mode) External Data Bus On-Chip Initial ROM Value Maximum Value 16 bits 16 bits 16 bits PC break controller * * Power-down state * * * * * * Operating modes Four MCU operating modes CPU Operating Mode Mode Description 4 5 6 7 * Advanced On-chip ROM disabled Disabled 16 bits expansion mode On-chip ROM disabled Disabled 8 bits expansion mode On-chip ROM enabled expansion mode Single-chip mode Enabled Enabled 8 bits -- Clock pulse generator Two on chip clock pulse generators System clock pulse generator: 2 to 13.5 MHz Built-in duty correction circuit Subclock pulse generator: 76.8 kHz, 160 kHz Packages 100-pin plastic TQFP (TFP-100B, TFP-100G) 4 Item Product lineup Specification Model Name Specification Non-roaming Roaming F-ZTAT Version HD64F2277 HD64F2277R ROM/RAM (Bytes) 128 k/16 k 128 k/16 k Packages TFP-100B TFP-100G 5 1.2 Internal Block Diagrams Figure 1.1 shows internal block diagrams. PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/ D9 PD0/ D8 PE7/ D7 PE6/ D6 PE5/ D5 PE4/ D4 PE3/ D3 PE2/ D2 PE1/ D1 PE0/ D0 VCC VCC VSS VSS Port D Port E Bus controller Interrupt controller DTC PC break controller (2 channels) WDT0 PF7/o PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT PF1/BACK/BUZZ PF0 /BREQ/IRQ2 PG4/CS0 PG3/CS1 PG2/CS2 PG1/CS3/IRQ7 Peripheral data bus MD2 MD1 MD0 EXTAL XTAL OSC1 OSC2 STBY RES NMI FWE System Subclock clock pulse clock pulse generator generator PA3 / A19 PA2 / A18 PA1 / A17 PA0 / A16 PB7 / A15 PB6 / A14 PB5 / A13 PB4 / A12 PB3 / A11 PB2 / A10 PB1 / A9 PB0 / A8 PC7 / A7 PC6 / A6 PC5 / A5 PC4 / A4 PC3 / A3 PC2 / A2 PC1 / A1 PC0 / A0 Internal data bus Peripheral address bus WDT1 (subclock operation) ROM Port F 8-bit timer (2 channels) SCI (3 channels) Port C Port B H8S/2000 CPU Internal address bus Port A RAM P35 / SCK1/IRQ5 P34 / RxD1 P33 / TxD1 P32 / SCK0/IRQ4 P31 / RxD0 P30 / TxD0 P47 / AN7 P46 / AN6 P45 / AN5 P44 / AN4 P43 / AN3 P42 / AN2 P41 / AN1 P40 / AN0 Vref AVCC AVSS Port G TPU (3 channels) A/D converter (8 channels) Port 4 Port 7 PG0 / IRQ6 P74 P75 / SCK3 P76 / RxD3 P77 / TxD3 Figure 1.1 H8S/2276 Series Internal Block Diagram 6 CLKOUT SYMCLK S7 S6 S5 S4 S3 S2 S1 S0/IFIN LOBAT TESTD EXTS1 EXTS0 READY SS RESET SCK MISO MOSI FLEXTM decoder II P36 P10 /TIOCA0 /A20 P11 /TIOCB0 /A21 P12 /TIOCC0 /TCLKA/A22 P13 /TIOCD0 /TCLKB/A23 P14 /TIOCA1/IRQ0 P16 /TIOCA2/IRQ1 Port 1 Port 3 1.3 1.3.1 Pin Description Pin Arrangements Figure 1.2 shows the pin arrangement of the H8S/2276 Series. PF0/BREQ/IRQ2 PF1/BACK/BUZZ PF2/WAIT PF3/LWR/ADTRG/IRQ3 PF4/HWR PF5/RD PF6/AS PF7/o MD2 FWE EXTAL VSS XTAL VCC STBY NMI RES OSC1 OSC2 MD1 MD0 AVCC Vref P40/AN0 P41/AN1 P30/TxD0 P31/RxD0 P32/SCK0/IRQ4 P33/TxD1 P34/RxD1 P35/SCK1/IRQ5 CLKOUT S7 S6 S5 S4 S3 S2 S1 S0/IFIN SYMCLK PG1/CS3/IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 TFP-100B TFP-100G (top view) Figure 1.2 H8S/2276 Series Pin Arrangement (TFP-100B, TFP-100G: Top View) PE5/D5 PE6/D6 PE7/D7 PD0/D8 PD1/D9 PD2/D10 PD3/D11 PD4/D12 PD5/D13 PD6/D14 PD7/D15 VCC PC0/A0 VSS PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 LOBAT TESTD AVSS EXTS1 P16/TIOCA2/IRQ1 EXTS0 P14/TIOCA1/IRQ0 P13/TIOCD0/TCLKB/A23 P12/TIOCC0/TCLKA/A22 P11/TIOCB0/A21 P10/TIOCA0/A20 PA3/A19 PA2/A18 PA1/A17 PA0/A16 PB7/A15 PB6/A14 PB5/A13 PB4/A12 7 1.3.2 Pin Functions in Each Operating Mode Table 1.2 shows the pin functions in each of the operating modes. Table 1.2 Pin No. TFP-100B TFP-100G 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Mode 4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 D13 D14 D15 VCC A0 VSS A1 A2 A3 A4 A5 A6 A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 Mode 5 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 D13 D14 D15 VCC A0 VSS A1 A2 A3 A4 A5 A6 A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 Pin Functions in Each Operating Mode Pin Name Mode 6 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 D13 D14 D15 VCC PC0/A0 VSS PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 Mode 7 PE5 PE6 PE7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 VCC PC0 VSS PC1 PC2 PC3 PC4 PC5 PC6 PC7 PB0 PB1 PB2 PB3 PB4 PB5 Flash Memory Programmer Mode OE WE CE D0 D1 D2 D3 D4 D5 D6 D7 VCC A0 VSS A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 8 Pin No. TFP-100B TFP-100G 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Mode 4 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 PA3/A19 Mode 5 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 PA3/A19 Pin Name Mode 6 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 PA3/A19 Mode 7 PB6 PB7 PA0 PA1 PA2 PA3 Flash Memory Programmer Mode A14 A15 A16 A17 A18 NC P10/TIOCA0/ P10/TIOCA0/ P10/TIOCA0/ P10/TIOCA0 NC A20 A20 A20 P11/TIOCB0/ P11/TIOCB0/ P11/TIOCB0/ P11/TIOCB0 NC A21 A21 A21 P12/TIOCC0/ P12/TIOCC0/ P12/TIOCC0/ P12/TIOCC0/ NC TCLKA/A22 TCLKA/A22 TCLKA/A22 TCLKA P13/TIOCD0/ P13/TIOCD0/ P13/TIOCD0/ P13/TIOCD0/ NC TCLKB/A23 TCLKB/A23 TCLKB/A23 TCLKB P14/TIOCA1/ P14/TIOCA1/ P14/TIOCA1/ P14/TIOCA1/ VSS IRQ0 IRQ0 IRQ0 IRQ0 EXTS0 EXTS0 EXTS0 EXTS0 NC P16/TIOCA2/ P16/TIOCA2/ P16/TIOCA2/ P16/TIOCA2/ VSS IRQ1 IRQ1 IRQ1 IRQ1 EXTS1 AVSS TESTD LOBAT P47/AN7 P46/AN6 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 Vref AVCC EXTS1 AVSS TESTD LOBAT P47/AN7 P46/AN6 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 Vref AVCC EXTS1 AVSS TESTD LOBAT P47/AN7 P46/AN6 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 Vref AVCC EXTS1 AVSS TESTD LOBAT P47/AN7 P46/AN6 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 Vref AVCC NC VSS NC NC NC NC NC NC NC NC NC NC VCC VCC 9 Pin No. TFP-100B TFP-100G 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Mode 4 MD0 MD1 OSC2 OSC1 RES NMI STBY VCC XTAL VSS EXTAL FWE MD2 PF7/o AS RD HWR Mode 5 MD0 MD1 OSC2 OSC1 RES NMI STBY VCC XTAL VSS EXTAL FWE MD2 PF7/o AS RD HWR Pin Name Mode 6 MD0 MD1 OSC2 OSC1 RES NMI STBY VCC XTAL VSS EXTAL FWE MD2 PF7/o AS RD HWR Mode 7 MD0 MD1 OSC2 OSC1 RES NMI STBY VCC XTAL VSS EXTAL FWE MD2 PF7/o PF6 PF5 PF4 Flash Memory Programmer Mode VSS VSS NC VCC RES VCC VCC VCC XTAL VSS EXTAL FWE VSS NC NC NC NC PF3/LWR/ PF3/LWR/ PF3/LWR/ PF3/ VCC ADTRG/IRQ3 ADTRG/IRQ3 ADTRG/IRQ3 ADTRG/IRQ3 PF2/WAIT PF1/BACK/ BUZZ PF0/BREQ/ IRQ2 P30/TxD0 P31/RxD1 P32/SCK0/ IRQ4 P33/TxD1 P34/RxD1 PF2/WAIT PF1/BACK/ BUZZ PF0/BREQ/ IRQ2 P30/TxD0 P31/RxD1 P32/SCK0/ RQ4 P33/TxD1 P34/RxD1 PF2/WAIT PF1/BACK/ BUZZ PF0/BREQ/ IRQ2 P30/TxD0 P31/RxD1 P32/SCK0/ IRQ4 P33/TxD1 P34/RxD1 PF2 PF1/BUZZ PF0/IRQ2 P30/TxD0 P31/RxD1 P32/SCK0/ IRQ4 P33/TxD1 P34/RxD1 NC NC VCC NC NC NC NC NC 10 Pin No. TFP-100B TFP-100G 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Mode 4 P35/SCK1/ IRQ5 CLKOUT S7 S6 S5 S4 S3 S2 S1 S0/IFIN SYMCLK PG1/CS3/ IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 Mode 5 P35/SCK1/ IRQ5 CLKOUT S7 S6 S5 S4 S3 S2 S1 S0/IFIN SYMCLK PG1/CS3/ IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 Pin Name Mode 6 P35/SCK1/ IRQ5 CLKOUT S7 S6 S5 S4 S3 S2 S1 S0/IFIN SYMCLK PG1/CS3/ IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 Mode 7 P35/SCK1/ IRQ5 CLKOUT S7 S6 S5 S4 S3 S2 S1 S0/IFIN SYMCLK PG1/IRQ7 PG2 PG3 PG4 PE0 PE1 PE2 PE3 PE4 Flash Memory Programmer Mode NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCC VSS 11 1.3.3 Pin Functions Table 1.3 outlines the pin functions. Table 1.3 Type Power Pin Functions Symbol VCC VSS I/O Input Input Input Name and Function Power supply: For connection to the power supply. All VCC pins should be connected to the system power supply. Ground: For connection to ground (0 V). All V SS pins should be connected to the system power supply (0 V). Crystal: Connects to a crystal oscillator. See section 18, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. External clock: Connects to a crystal oscillator. The EXTAL pin can also input an external clock. See section 18, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. Subclock: Connects to a 76.8 kHz or 160 kHz crystal oscillator. See section 18, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator. Subclock: Connects to a 76.8 kHz or 160 kHz crystal oscillator. See section 18, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator. Clock XTAL EXTAL Input OSC1 Input OSC2 Input o Operating mode control MD2 to MD0 Output System clock: Supplies the system clock to an external device. Input Mode pins: These pins set the operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the LSI is operating. Except when changing the mode, the levels of mode pins MD2 to MD0 must be fixed by pulling the pins up or down. MD2 0 MD1 0 1 1 0 1 MD0 0 1 0 1 0 1 0 1 Operating Mode -- -- -- -- Mode 4 Mode 5 Mode 6 Mode 7 12 Type System control Symbol RES STBY BREQ BACK FWE I/O Input Input Input Name and Function Reset input: When this pin is driven low, the chip enters the power-on reset state. Standby: When this pin is driven low, a transition is made to hardware standby mode. Bus request: Used by an external bus master to issue a bus request to the LSI. Output Bus request acknowledge: Indicates that the bus has been released to an external bus master. Input Input Input Flash write enable: Enables or disables flash memory programming. Nonmaskable interrupt: Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high. Interrupt request 7 to 0: These pins request a maskable interrupt. IRQ6 is a dedicated interrupt for the FLEXTM decoder II. Interrupts NMI IRQ7 to IRQ0 Address bus Data bus Bus control A23 to A0 D15 to D0 CS3 to CS0 AS RD HWR Output Address bus: These pins output an address. I/O Data bus: These pins constitute a bidirectional data bus. Output Chip select: Signals for selecting areas 3 to 0. Output Address strobe: When this pin is low, it indicates that address output on the address bus is enabled. Output Read: When this pin is low, it indicates that the external address space can be read. Output High write: A strobe signal that writes to external space and indicates that the upper half (D15 to D8) of the data bus is enabled. Output Low write: A strobe signal that writes to external space and indicates that the lower half (D7 to D0) of the data bus is enabled. Input Wait: Requests insertion of a wait state in the bus cycle when accessing external 3-state address space. LWR WAIT 13 Type Symbol I/O Input I/O Name and Function Clock input B and A: These pins input an external clock. Input capture/output compare match A0 to D0: The TGR0A to TGR0D input capture input or output compare output, or PWM output pins. Input capture/output compare match A1: The TGR1A input capture input or output compare output, or PWM output pin. Input capture/output compare match A2: The TGR2A input capture input or output compare output, or PWM output pin. 16-bit timerTCLKB, pulse unit (TPU) TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1 I/O TIOCA2 I/O Watchdog timer (WDT) Serial communication interface (SCI) BUZZ TxD3, TxD1, TxD0 RxD3, RxD1, RxD0 SCK3 SCK1, SCK0 Output BUZZ output: Outputs pulses scaled by the watchdog timer. Output Transmit data: Data output pins. TxD3 is an internal dedicated pin for the FLEXTM decoder II interface. Input Receive data: Data input pins. RxD3 is an internal dedicated pin for the FLEXTM decoder II interface. Output Serial clock: Clock I/O pins. I/O Input Input Input SCK3 is an internal dedicated pin for the FLEXTM decoder II interface. Analog 7 to 0: Analog input pins. A/D conversion external trigger input: Pin for input of an external trigger to start A/D conversion. This is the power supply pin for the A/D converter. When the A/D converter is not used, this pin should be connected to the system power supply (+3 V). This is the ground pin for the A/D converter. This pin should be connected to the system power supply (0 V). This is the reference voltage input pin for the A/D converter. When the A/D converter is not used, this pin should be connected to the system power supply (+3 V). A/D converter AN7 to AN0 ADTRG AVCC AVSS Vref Input Input 14 Type I/O ports Symbol I/O Name and Function Port 1: A 6-bit I/O port. Input or output can be designated for each bit by means of the port 1 data direction register (P1DDR). Port 3: A 6-bit I/O port. Input or output can be designated for each bit by means of the port 3 data direction register (P3DDR). Port 4: An 8-bit input port. Port A: A 4-bit I/O port. Input or output can be designated for each bit by means of the port A data direction register (PADDR). Port B: An 8-bit I/O port. Input or output can be designated for each bit by means of the port B data direction register (PBDDR). Port C: An 8-bit I/O port. Input or output can be designated for each bit by means of the port C data direction register (PCDDR). Port D: An 8-bit I/O port. Input or output can be designated for each bit by means of the port D data direction register (PDDDR). Port E: An 8-bit I/O port. Input or output can be designated for each bit by means of the port E data direction register (PEDDR). Port F: An 8-bit I/O port. Input or output can be designated for each bit by means of the port F data direction register (PFDDR). Port G: A 4-bit I/O port. Input or output can be designated for each bit by means of the port G data direction register (PGDDR). Port 3: A 1-bit I/O port. Input or output can be designated for each bit by means of the port 3 data direction register (P3DDR). Port 7: A 4-bit I/O port. Input or output can be designated for each bit by means of the port 7 data direction register (P7DDR). Port G: A 1-bit input port. P16, I/O P14 to P10 P35 to P30 P47 to P40 PA3 to PA0 PB7 to PB0 PC7 to PC0 PD7 to PD0 PE7 to PE0 PF7 to PF0 PG4 to PG1 I/O Input I/O I/O I/O I/O I/O I/O I/O Internal I/O P36 I/O ports (dedicated ports for the FLEXTM decoder P77 to P74 I/O II interface) PG0 Input 15 Type FLEXTM decoder II Symbol RESET EXTS1 EXTS0 LOBAT SS SCK MOSI MISO READY CLKOUT SYMCLK S0 S1 to S7 IFIN I/O Input Input Input Input Input Input Input Name and Function Decoder reset: A reset is executed when this pin goes low. Decode symbol input: MSb of the symbol currently being decoded. Decode symbol input: LSb of the symbol currently being decoded. Voltage drop detection input: Input pin for the voltage drop detection signal. SPI mode select: Slave mode is selected when this pin goes low. SPI clock input: SPI clock input. SPI receive data input: SPI data input. Output SPI transmit data output: SPI data output. Output Ready pin: Goes low when the SPI is ready to transmit/receive. Output Clock output: 38.4 kHz or 40 kHz clock output (derived from on-chip crystal oscillator). Output Symbol clock output: Recovered symbol clock pin. Output Receiver control output: Receiver control signal output pin (when using external demodulator). Output Receiver control output: Three-state receiver control signal output. Input IF signal input: Limited IF signal input pin (when using internal demodulator). 16 Section 2 CPU 2.1 Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2000 CPU has the following features. * Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H object programs * General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * Sixty-five basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes (4 Gbytes architecturally) 17 * High-speed operation All frequently-used instructions execute in one or two states Maximum clock rate: 13.5 MHz 8/16/32-bit register-register add/subtract: 74 ns (at 13.5 MHz operation) 8 x 8-bit register-register multiply: 888 ns (at 13.5 MHz operation) 16 / 8-bit register-register divide: 888 ns (at 13.5 MHz operation) 16 x 16-bit register-register multiply: 1480 ns (at 13.5 MHz operation) 32 / 16-bit register-register divide: 1480 ns (at 13.5 MHz operation) * Two CPU operating modes Normal mode* Advanced mode Note: * Not available in the LSI. * Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. * Register configuration The MAC register is supported only by the H8S/2600 CPU. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. * Number of execution states The number of exection states of the MULXU and MULXS instructions. Internal Operation Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21 18 There are also differences in the address space, CCR and EXR register functions, power-down state, etc., depending on the product. 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. * More general registers and control registers Eight 16-bit expanded registers, plus one 8-bit and two 32-bit control registers, have been added. * Expanded address space Normal mode* supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. Note: * Not available in the LSI. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. 2.1.4 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. * Additional control register One 8-bit and two 32-bit control registers have been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. 19 * Higher speed Basic instructions execute twice as fast. 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal* and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data areas combined). The mode is selected by the mode pins of the microcontroller. Note: * Not available in the LSI. Maximum 64 kbytes, program and data areas combined Normal mode* CPU operating modes Advanced mode Maximum 16-Mbytes for program and data areas combined Note: * Not available in the LSI. Figure 2.1 CPU Operating Modes (1) Normal Mode (not available in the LSI) The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. 20 Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The configuration of the exception vector table in normal mode is shown in figure 2.2. For details of the exception vector table, see section 4, Exception Handling. H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Power-on reset exception vector (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.2 Exception Vector Table (Normal Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. 21 Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. SP PC (16 bits) SP *2 (SP ) EXR*1 Reserved*1,*3 CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: *1 When EXR is not used it is not stored on the stack. *2 SP when EXR is not used. *3 Ignored when returning. Figure 2.3 Stack Structure in Normal Mode (2) Advanced Mode Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program and data areas combined). Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. Instruction Set: All instructions and addressing modes can be used. 22 Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Power-on reset exception vector H'00000003 H'00000004 H'00000007 H'00000008 (Reserved for system use) Exception vector table H'0000000B H'0000000C H'00000010 Reserved Exception vector 1 Figure 2.4 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table. 23 Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. SP SP Reserved PC (24 bits) *2 (SP ) EXR*1 Reserved*1,*3 CCR PC (24 bits) (a) Subroutine Branch (b) Exception Handling Notes: *1 When EXR is not used it is not stored on the stack. *2 SP when EXR is not used. *3 Ignored when returning. Figure 2.5 Stack Structure in Advanced Mode 24 2.3 Address Space Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF Data area Cannot be used by LSI H'FFFFFFFF (a) Normal Mode* Note: * Not available in the LSI. (b) Advanced Mode Figure 2.6 Memory Map 25 2.4 2.4.1 Register Configuration Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) Control Registers (CR) 23 PC 76543210 EXR T -- -- -- -- I2 I1 I0 76543210 CCR I UI H U N Z V C Legend SP: PC: EXR: T: I2 to I0: CCR: I: UI: 0 E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit* H: U: N: Z: V: C: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Note: * In the LSI, this bit cannot be used as an interrupt mask. Figure 2.7 CPU Registers 26 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2.8 illustrates the usage of the general registers. The usage of each register can be selected independently. * Address registers * 32-bit registers * 16-bit registers E registers (extended registers) (E0 to E7) * 8-bit registers ER registers (ER0 to ER7) R registers (R0 to R7) RH registers (R0H to R7H) RL registers (R0L to R7L) Figure 2.8 Usage of General Registers 27 General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the stack. Free area SP (ER7) Stack area Figure 2.9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) (2) Extended Control Register (EXR): This 8-bit register contains the trace bit (T) and interrupt mask bit. Bit 7--Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is executed. Bits 6 to 3--Reserved: They are always read as 1. 28 Bits 2 to 0--Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. All interrupts, including NMI, are disabled for three states after one of these instructions is executed, except for STC. (3) Condition-Code Register (CCR): This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7--Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller. Bit 6--User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. With the LSI, this bit cannot be used as an interrupt mask bit. Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4--User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3--Negative Flag (N): Stores the value of the most significant bit (sign bit) of data. Bit 2--Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift and rotate instructions, to indicate a carry. The carry flag is also used as a bit accumulator by bit manipulation instructions. 29 Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to Appendix A.1, List of Instructions. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. 2.4.4 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. 30 2.5 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.10 shows the data formats in general registers. Data Type Register Number Data Format 1-bit data RnH 7 0 76543210 Don't care 1-bit data RnL Don't care 7 0 76543210 4-bit BCD data RnH 7 Upper 43 Lower 0 Don't care 4-bit BCD data RnL Don't care 7 Upper 43 Lower 0 Byte data RnH 7 MSB 0 Don't care LSB 7 Don't care MSB LSB 0 Byte data RnL Figure 2.10 General Register Data Formats 31 Data Type Register Number Data Format Word data Rn 15 MSB 0 LSB Word data 15 MSB Longword data 31 MSB En 0 LSB ERn 16 15 En Rn 0 LSB Legend ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.10 General Register Data Formats (cont) 32 2.5.2 Memory Data Formats Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 0 0 Data Format Byte data Address L MSB LSB Word data Address 2M MSB Address 2M + 1 LSB Longword data Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB Figure 2.11 Memory Data Formats When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size. 33 2.6 2.6.1 Instruction Set Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Function Data transfer Instruction Classification Instructions MOV POP* , PUSH* LDM, STM MOVFPE* , MOVTPE* 3 3 1 1 Size BWL WL L B BWL B BWL L BW WL B BWL Types 5 Arithmetic operations ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS* 4 19 Logic operations Shift Bit manipulation Branch System control Block data transfer AND, OR, XOR, NOT 4 8 14 5 9 1 SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc* 2, JMP, BSR, JSR, RTS B -- TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP -- EEPMOV -- Total: 65 Notes: B-byte size; W-word size; L-longword size. *1 POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. *2 Bcc is the general name for conditional branch instructions. *3 Cannot be used in the LSI. *4 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 34 2.6.2 Table 2.2 Combinations of Instructions and Addressing Modes Addressing Modes Function #xx Instruction Rn @ERn @(d:16,ERn) @(d:32,ERn) @-ERn/@ERn+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,PC) @(d:16,PC) @@aa:8 Data transfer BWL -- -- -- BWL WL B -- -- -- -- -- -- -- -- -- B -- -- -- WL -- -- -- -- -- -- BWL -- -- -- -- -- BW -- -- -- -- -- -- -- -- -- BW -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- BWL -- -- -- -- -- -- -- L -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- BWL -- -- -- -- -- -- -- -- BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BWL BWL BWL BWL BWL B BWL -- BWL -- -- MOV -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- WL L -- -- -- -- -- -- -- -- -- -- -- -- POP, PUSH LDM, STM MOVFPE*1, MOVTPE*1 Arithmetic operations ADD, CMP SUB ADDX, SUBX ADDS, SUBS Instructions and Addressing Modes INC, DEC DAA, DAS MULXU, DIVXU MULXS, DIVXS NEG EXTU, EXTS Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU can use. -- TAS*2 35 #xx Rn @ERn @(d:16,ERn) @(d:32,ERn) @-ERn/@ERn+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,PC) @(d:16,PC) @@aa:8 Logic operations AND, OR, XOR NOT -- -- -- -- -- -- -- -- B -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B W W W W -- -- -- -- B W W W W -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- B B -- -- -- B B -- B BWL -- -- -- -- -- -- -- -- -- BWL -- -- -- -- -- -- -- -- -- -- -- BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Shift Bcc, BSR JMP, JSR RTS TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP Bit manipulation Branch System control -- -- -- Block data transfer BW Legend B: Byte W: Word L: Longword Notes: *1 Cannot be used in the LSI. *2 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. -- 36 Addressing Modes Instruction Function 2.6.3 Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation Rd Rs Rn ERn (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / :8/:16/:24/:32 General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). 37 Table 2.3 Type Data transfer Instructions Classified by Function Instruction MOV Size* 1 B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Cannot be used in the LSI. Cannot be used in the LSI. @SP+ Rn Pops a register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn @-SP Pushes a register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. @SP+ Rn (register list) Pops two or more general registers from the stack. Rn (register list) @-SP Pushes two or more general registers onto the stack. Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. MOVFPE MOVTPE POP B B W/L PUSH W/L LDM STM Arithmetic operations ADD SUB L L B/W/L ADDX SUBX B INC DEC B/W/L ADDS SUBS DAA DAS L B 38 Type Arithmetic operations Instruction MULXU Size* 1 B/W Function Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16bit remainder. Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. @ERd - 0, 1 ( MULXS B/W DIVXU B/W DIVXS B/W CMP B/W/L NEG B/W/L EXTU W/L EXTS W/L TAS B 39 Type Logic operations Instruction AND Size* 1 B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. (Rd) (Rd) Takes the one's complement of general register contents. Rd (shift) Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. Rd (shift) Rd Performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. Rd (rotate) Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. Rd (rotate) Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. 1 ( OR B/W/L XOR B/W/L NOT B/W/L Shift operations SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR B/W/L B/W/L B/W/L B/W/L Bitmanipulation instructions BSET B BCLR B BNOT B 40 Type Bitmanipulation instructions Instruction BTST Size* 1 B Function ( BAND B BIAND B BOR B BIOR B BXOR B BIXOR B BLD B BILD B 41 Type Bitmanipulation instructions Instruction BST Size* 1 B Function C ( BIST B Branch instructions Bcc -- JMP BSR JSR RTS System control TRAPA instructions RTE SLEEP -- -- -- -- -- -- -- Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. 42 Type Instruction Size* 1 B/W Function (EAs) CCR, (EAs) EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 PC Only increments the program counter. if R4L 0 then Repeat @ER5+ @ER6+ R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+ R4-1 R4 Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6. R4L or R4: size of block (bytes) ER5: starting source address ER6: starting destination address Execution of the next instruction begins as soon as the transfer is completed. System control LDC instructions STC B/W ANDC B ORC B XORC B NOP Block data transfer instruction EEPMOV.B -- -- EEPMOV.W -- Notes: *1 Size refers to the operand size. B: Byte W: Word L: Longword *2 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 43 2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc field). Figure 2.12 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc rn rm MOV.B @(d:16, Rn), Rm, etc. Figure 2.12 Instruction Formats (Examples) (1) Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. (2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. (3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. (4) Condition Field: Specifies the branching condition of Bcc instructions. 44 2.6.5 Notes on Use of Bit-Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, carry out bit manipulation, then write back the byte of data. Caution is therefore required when using these instructions on a register containing write-only bits, or a port. The BCLR instruction can be used to clear internal I/O register flags to 0. In this case, the relevant flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt handling routine, etc. 2.7 2.7.1 Addressing Modes and Effective Address Calculation Addressing Mode The H8S/2000 CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.4 No. 1 2 3 4 5 6 7 8 Addressing Modes Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 (1) Register Direct--Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 45 (2) Register Indirect--@ERn: The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). (3) Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn): A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. (4) Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn: * Register indirect with post-increment--@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. * Register indirect with pre-decrement--@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. (5) Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.5 indicates the accessible absolute address ranges. 46 Table 2.5 Absolute Address Access Ranges Normal Mode* 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF Absolute Address Data address Program instruction address 24 bits (@aa:24) Note: * Not available in the LSI. (6) Immediate--#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) Program-Counter Relative--@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. (8) Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF* in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Note: * Not available in the LSI. 47 Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode* Note: * Not available in the LSI. (b) Advanced Mode Figure 2.13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation Table 2.6 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. 48 No. Effective Address Calculation Addressing Mode and Instruction Format Effective Address (EA) 1 rn Operand is general register contents. Table 2.6 Register direct (Rn) op rm 2 31 General register contents Don't care 0 31 24 23 Register indirect (@ERn) 0 op r 3 31 General register contents 31 disp 31 Sign extension disp 0 0 Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) 24 23 Don't care 0 Effective Address Calculation op r 4 31 Register indirect with post-increment or pre-decrement * Register indirect with post-increment @ERn+ 0 General register contents 31 24 23 Don't care 0 op r 1, 2, or 4 31 General register contents 31 24 23 Don't care Operand Size Value added Byte Word Longword 1 2 4 1, 2, or 4 0 0 * Register indirect with pre-decrement @-ERn op r 49 50 Effective Address Calculation Effective Address (EA) 31 24 23 H'FFFF abs Don't care No. Addressing Mode and Instruction Format 5 87 Absolute address 0 @aa:8 op @aa:16 31 24 23 op abs Don't care 16 15 Sign extension 0 @aa:24 abs 31 24 23 Don't care 0 op @aa:32 op abs 31 24 23 Don't care 0 6 op IMM Immediate #xx:8/#xx:16/#xx:32 Operand is immediate data. No. Effective Address Calculation 23 PC contents 0 Addressing Mode and Instruction Format Effective Address (EA) 7 Program-counter relative @(d:8, PC)/@(d:16, PC) op 23 Sign extension disp 31 Don't care disp 0 24 23 0 8 Memory indirect @@aa:8 * Normal mode* abs 31 H'000000 87 abs 0 31 24 23 Don't care op 16 15 H'00 0 15 Memory contents 0 * Advanced mode abs 31 H'000000 31 Memory contents 87 abs 0 31 24 23 Don't care op 0 0 Note: * Not available in the LSI. 51 2.8 2.8.1 Processing States Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, interrupt, or trap instruction. Processing states Program execution state The CPU executes program instructions in sequence. Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU. Sleep mode Power-down state CPU operation is stopped to conserve power.* Software standby mode Hardware standby mode Note: * The power-down state also includes a medium-speed mode, module stop mode, subactive mode, subsleep mode, and watch mode. Figure 2.14 Processing States 52 End of bus request Bus request Program execution state End of bus request Bus request SLEEP instruction with SSBY = 0 Bus-released state End of exception handling Request for exception handling SLEEP instruction with SSBY = 1 Sleep mode Interrupt request Exception-handling state External interrupt RES = high Software standby mode STBY = high, RES = low Power-on reset state*1 Reset state Hardware standby mode*2 Power-down state*3 Notes: *1 From any state except hardware standby mode, a transition to the power-on reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. *2 From any state, a transition to hardware standby mode occurs when STBY goes low. *3 There are also other modes, including watch mode, subactive mode, and subsleep mode. For details, refer to section 21, Power-Down State. Figure 2.15 State Transitions 2.8.2 Reset State When the RES input goes low all current processing stops and the CPU enters the power-on reset state. All interrupts are disabled in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, refer to section 12, Watchdog Timer. 53 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for resets, traces, interrupts, and trap instructions. Table 2.7 indicates the types of exception handling and their priority. Trap instruction exception handling is always accepted, in the program execution state. Exception handling and the stack structure depend on the interrupt control mode set in SYSCR. Table 2.7 Priority High Exception Handling Types and Priority Type of Exception Reset Detection Timing Synchronized with clock Start of Exception Handling Exception handling starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. When the trace (T) bit is set to 1, the trace starts at the end of the current instruction or current exception-handling sequence When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Exception handling starts when a trap (TRAPA) instruction is executed* 3 Trace End of instruction execution or end of exception-handling sequence* 1 End of instruction execution or end of exception-handling sequence* 2 When TRAPA instruction is executed Interrupt Trap instruction Low Notes: *1 Traces are enabled only in interrupt control mode 2. Trace exception-handling is not executed at the end of the RTE instruction. *2 Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. *3 Trap instruction exception handling is always accepted, in the program execution state. 54 (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, reset exception handling starts when RES goes high again. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. (3) Traces Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR is set to 1. When trace mode is established, trace exception handling starts at the end of each instruction. At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode is cleared. Interrupt masks are not affected. The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to return from the trace exception-handling routine, trace mode is entered again. Trace exceptionhandling is not executed at the end of the RTE instruction. Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit. (4) Interrupt Exception Handling and Trap Instruction Exception Handling When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution starts from that start address. Figure 2.16 shows the stack after exception handling ends. 55 Normal mode*2 SP SP CCR CCR*1 PC (16 bits) EXR Reserved*1 CCR CCR*1 PC (16 bits) (a) Interrupt control mode 0 (b) Interrupt control mode 2 Advanced mode SP SP CCR PC (24 bits) EXR Reserved*1 CCR PC (24 bits) (c) Interrupt control mode 0 Notes: *1 Ignored when returning. *2 Not available in the LSI. (d) Interrupt control mode 2 Figure 2.16 Stack Structure after Exception Handling (Examples) 56 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. There is one other bus master in addition to the CPU: the data transfer controller (DTC). For further details, refer to section 7, Bus Controller. 2.8.6 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode, software standby mode, hardware standby mode, subsleep mode, and watch mode. There are also three other power-down modes: medium-speed mode, module stop mode, and subactive mode. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. Subactive mode, subsleep mode, and watch mode are power-down states in which subclock input is used. For details, refer to section 21, Power-Down State. (1) Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the SSBY bit in SBYCR and the LSON bit in LPWRCR are both cleared to 0. In sleep mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU registers are retained. (2) Software Standby Mode: A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, and the LSON bit in LPWRCR and the PSS bit in TCSR (WDT1) are both cleared to 0. In software standby mode, the CPU and clock halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states. (3) Hardware Standby Mode: A transition to hardware standby mode is made when the STBY pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. 57 2.9 2.9.1 Basic Timing Overview The H8S/2000 CPU is driven by a system clock, denoted by the symbol o. The period from one rising edge of o to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 On-Chip Memory (ROM, RAM) On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 2.17 shows the on-chip memory access cycle. Figure 2.18 shows the pin states. Bus cycle T1 o Internal address bus Internal read signal Internal data bus Internal write signal Write access Internal data bus Write data Read data Address Read access Figure 2.17 On-Chip Memory Access Cycle 58 Bus cycle T1 o Address bus AS RD HWR, LWR Data bus Unchanged High High High High-impedance state Figure 2.18 Pin States during On-Chip Memory Access 59 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the access timing for the on-chip supporting modules. Figure 2.20 shows the pin states. Bus cycle T1 T2 o Internal address bus Address Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Write data Read data Figure 2.19 On-Chip Supporting Module Access Cycle 60 Bus cycle T1 T2 o Address bus Unchanged AS RD HWR, LWR High High High Data bus High-impedance state Figure 2.20 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 7, Bus Controller. 61 2.10 Usage Note Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Hitachi H8S and H8/300 series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used. 2.10.1 STM/LDM Instruction With the STM or LDM instruction, the ER7 register is used as the stack pointer, and thus cannot be used as a register that allows save (STM) or restore (LDM) operation. With a single STM or LDM instruction, two to four registers can be can be saved or restored. The available registers are as follows: * For two registers: ER0 and ER1, ER2 and ER3, or ER4 and ER5 * For three registers: ER0 to ER2, or ER4 to ER6 * For four registers: ER0 to ER3 For the Hitachi H8S or H8/300 Series C/C++ compiler, the STM/LDM instruction including ER7 is not created. 62 Section 3 MCU Operating Modes 3.1 3.1.1 Overview Operating Mode Selection The LSI has four operating modes (modes 4 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD2 to MD0). Table 3.1 lists the MCU operating modes. Table 3.1 MCU Operating Mode Selection External Data Bus On-Chip Initial ROM Width -- -- Max. Width MCU CPU Operating Operating Mode MD2 MD1 MD0 Mode Description 0* 1* 2* 3* 4 5 6 7 1 1 0 1 0 0 0 1 0 1 0 1 0 1 -- -- Advanced On-chip ROM disabled, Disabled 16 bits expanded mode 8 bits On-chip ROM enabled, Enabled 8 bits expanded mode Single-chip mode -- 16 bits 16 bits 16 bits Note: * Not available in the LSI. The CPU's architecture allows for 4 Gbytes of address space, but the LSI actually accesses a maximum of 16 Mbytes. Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. Note that the functions of each pin depend on the operating mode. 63 The LSI can be used only in modes 4 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.2 Register Configuration The LSI has a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) that controls the operation of the LSI. Table 3.2 summarizes these registers. Table 3.2 Name Mode control register System control register MCU Registers Abbreviation MDCR SYSCR R/W R R/W Initial Value Undetermined H'01 Address* H'FDE7 H'FDE5 Note: * Lower 16 bits of the address. 3.2 3.2.1 Bit Register Descriptions Mode Control Register (MDCR) : 7 -- 1 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 MDS2 --* R 1 MDS1 --* R 0 MDS0 --* R Initial value: R/W : Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit read-only register that indicates the current operating mode of the LSI. Bit 7--Reserved: This bit cannot be modified and is always read as 1. Bits 6 to 3--Reserved: These bits cannot be modified and are always read as 0. Bits 2 to 0--Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are read-only bits-they cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a power-on reset. 64 3.2.2 Bit System Control Register (SYSCR) : 7 -- 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 -- 0 R/W 1 -- 0 -- 0 RAME 1 R/W Initial value: R/W : SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, the detected edge for NMI, and enables or disables on-chip RAM. SYSCR is initialized to H'01 by a power-on reset and in hardware standby mode. SYSCR is not initialized in software standby mode. Bit 7--Reserved: Only 0 should be written to this bit. Bit 6--Reserved: This bit cannot be modified and is always read as 0. Bits 5 and 4--Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and Interrupt Operation. Bit 5 INTM1 0 Bit 4 INTM0 0 1 1 0 1 Interrupt Control Mode 0 -- 2 -- Description Control of interrupts by I bit Setting prohibited Control of interrupts by I2 to I0 bits and IPR Setting prohibited (Initial value) Bit 3--NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input. Bit 3 NMIEG 0 1 Description An interrupt is requested at the falling edge of NMI input An interrupt is requested at the rising edge of NMI input (Initial value) Bit 2--Reserved: Only 0 should be written to this bit. Bit 1--Reserved: This bit cannot be modified and is always read as 0. 65 Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset status is released. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) Note: When the DTC is used, the RAME bit must be set to 1. 3.3 3.3.1 Operating Mode Descriptions Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Pins P13 to P10, and ports A, B, and C function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. Pins P13 to P11 function as input ports immediately after a reset. Address (A23 to A21) output can be enabled or disabled by bits AE3 to AE0 in the pin function control register (PFCR) regardless of the corresponding data direction register (DDR) values. Pin 10 and ports A and B function as address (A20 to A8) outputs immediately after a reset. Address output can be enabled or disabled by bits AE3 to AE0 in PFCR regardless of the corresponding DDR values. Pins for which address output is disabled among pins P13 to P10 and in ports A and B become port outputs when the corresponding DDR bits are set to 1. Port C always has an address (A7 to A0) output function. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. 3.3.2 Mode 5 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Pins P13 to P10, and ports A, B, and C function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. Pins P13 to P11 function as input ports immediately after a reset. Address (A23 to A21) output can be enabled or disabled by bits AE3 to AE0 in the pin function control register (PFCR) regardless of the corresponding data direction register (DDR) values. Pin 10 and ports A and B function as address (A20 to A8) outputs immediately after a reset. Address output can be enabled 66 or disabled by bits AE3 to AE0 in PFCR regardless of the corresponding DDR values. Pins for which address output is disabled among pins P13 to P10 and in ports A and B become port outputs when the corresponding DDR bits are set to 1. Port C always has an address (A7 to A0) output function. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.3 Mode 6 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Pins P13 to P10, and ports A and B function as input ports immediately after a reset. Address (A23 to A8) output can be enabled or disabled by bits AE3 to AE0 in the pin function control register (PFCR) regardless of the corresponding data direction register (DDR) values. Pins for which address output is disabled among pins P13 to P10 and in ports A and B become port outputs when the corresponding DDR bits are set to 1. Ports D and E function as a data bus, and part of port F carries data bus signals. Port C is an input port immediately after a reset. Addresses A7 to A0 are output by setting the corresponding DDR bits to 1. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.4 Mode 7 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. 67 3.4 Pin Functions in Each Operating Mode The pin functions of ports 1, and A to F vary depending on the operating mode. Table 3.3 shows their functions in each operating mode. Table 3.3 Port Port 1 P13 to P11 P10 Port A Port B Port C Port D Port E Port F PF7 PF6 to PF4 PF3 PF2 to PF0 Legend P: I/O port A: Address bus output D: Data bus I/O C: Control signals, clock I/O *: After reset PA3 to PA0 Pin Functions in Each Operating Mode Mode 4 P*/A P/A* P/A* P/A* A D P/D* P/C* C P/C* P*/C Mode 5 P*/A P/A* P/A* P/A* A D P*/D P/C* C P*/C P*/C Mode 6 P*/A P*/A P*/A P*/A P*/A D P*/D P/C* C P*/C P*/C Mode 7 P P P P P P P P*/C P 3.5 Memory Map in Each Operating Mode Figure 3.1 shows the memory map in each operating mode. The address space is 16 Mbytes in modes 4 to 7 (advanced modes). The address space is divided into eight areas for modes 4 to 7. For details, see section 7, Bus Controller. 68 Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM External address space H'01FFFF H'020000 External address space H'FFB000 On-chip RAM* H'FFEFC0 External address space H'FFB000 On-chip RAM* H'FFB000 On-chip RAM H'FFEFBF H'FFEFC0 H'FFFF40 H'FFFF60 H'FFFFC0 H'FFFFFF External address space External address space H'FFF800 Internal I/O registers H'FFFF40 External address space H'FFF800 Internal I/O registers H'FFF800 Internal I/O registers H'FFFF3F H'FFFF60 H'FFFFC0 H'FFFFFF Internal I/O registers On-chip RAM H'FFFF60 H'FFFFC0 H'FFFFFF Internal I/O registers On-chip RAM* Internal I/O registers On-chip RAM* Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.1 Memory Map in Each Operating Mode in the LSI 69 70 Section 4 Exception Handling 4.1 4.1.1 Overview Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times, in the program execution state. Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR. Table 4.1 Priority High Exception Handling Types and Priority Exception Handling Type Start of Exception Handling Reset Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. The CPU enters the power-on reset state when the RES pin is low. Starts when execution of the current instruction or exception handling ends, if the trace (T) bit is set to 1 Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued* 2 Trace* 1 Interrupt Low Trap instruction (TRAPA)*3 Started by execution of a trap instruction (TRAPA) Notes: *1 Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. *2 Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. *3 Trap instruction exception handling requests are accepted at all times in program execution state. 71 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out. 4.1.3 Exception Sources and Vector Table The exception sources are classified as shown in figure 4.1. Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Reset Trace Exception sources Direct transition External interrupts: NMI, IRQ7 to IRQ0 Interrupts Internal interrupts: 36 interrupt sources in on-chip supporting modules Trap instruction Figure 4.1 Exception Sources 72 Table 4.2 Exception Vector Table Vector Address* 1 Exception Source Power-on reset Reserved for system use Vector Number 0 1 2 3 4 Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063 H'01EC to H'01EF Trace Direct transition* 3 5 6 NMI 7 8 9 10 11 External interrupt Trap instruction (4 sources) Reserved for system use 12 13 14 15 External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 16 17 18 19 20 21 22 23 24 123 Internal interrupt* 2 Notes: *1 Lower 16 bits of the address. *2 For details of internal interrupt vectors, see section 5.3.3, Interrupt Exception Handling Vector Table. *3 For details of direct transition, see section 19.11, Direct Transition. 73 4.2 4.2.1 Reset Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the LSI enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the RES pin changes from low to high. The LSI can also be reset by overflow of the watchdog timer. For details see section 12, Watchdog Timer. 4.2.2 Reset Sequence The LSI enters the reset state when the RES pin goes low. To ensure that the LSI is reset, hold the RES pin low for at least 20 ms at power-up. To reset the LSI during operation, hold the RES pin low for at least 20 states. When the RES pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip supporting modules are initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4.2 and 4.3 show examples of the reset sequence. 74 Vector Internal Prefetch of first program fetch processing instruction o RES Internal address bus Internal read signal Internal write signal Internal data bus (1) (2) (3) (4) (2) (1) (3) High (4) Reset exception handling vector address ((1) = H'0000) Start address (contents of reset exception handling vector address) Start address ((3) = (2)) First program instruction Figure 4.2 Reset Sequence (Modes 2 and 3: Not available in the LSI) 75 Vector fetch Internal Prefetch of first processing program instruction * * * o RES Address bus RD HWR, LWR D15 to D0 (2) (1) (3) (5) High (4) (6) (1) (3) (2) (4) (5) (6) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) Start address (contents of reset exception handling vector address) Start address ((5) = (2) (4)) First program instruction Note: * 3 program wait states are inserted. Figure 4.3 Reset Sequence (Mode 4) 4.2.3 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx:32, SP). 4.2.4 State of On-Chip Supporting Modules after Reset Release After reset release, MSTPCRA is initialized to H'3F, MSTPCRB and MSTPCRC are initialized to H'FF, and all modules except the DTC enter module stop mode. Consequently, on-chip supporting module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited. 76 4.3 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking. Table 4.4 shows the state of CCR and EXR after execution of trace exception handling. Interrupts are accepted even within the trace exception handling routine. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Table 4.3 Status of CCR and EXR after Trace Exception Handling CCR Interrupt Control Mode 0 2 1 I UI I2 to I0 EXR T Trace exception handling cannot be used. -- -- 0 Legend 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution. 77 4.4 Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 36 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), 16-bit timer-pulse unit (TPU), 8-bit timer, serial communication interface (SCI), data transfer controller (DTC), PC break controller (PBC) and A/D converter. Each interrupt source has a separate vector address. NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. For details of interrupts, see section 5, Interrupt Controller. External interrupts Interrupts NMI (1) IRQ7 to IRQ0 (8) WDT* (2) TPU (13) 8-bit timer (6) SCI (12) DTC (1) A/D converter (1) Other (1) Internal interrupts Notes: Numbers in parentheses are the numbers of interrupt sources. * When the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. Figure 4.4 Interrupt Sources and Number of Interrupts 78 4.5 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling CCR Interrupt Control Mode 0 2 I 1 1 UI -- -- I2 to I0 -- -- EXR T -- 0 Legend 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution. 79 4.6 Stack Status after Exception Handling Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP SP CCR CCR* PC (16 bits) EXR Reserved* CCR CCR* PC (16 bits) (a) Interrupt control mode 0 Note: * Ignored on return. (b) Interrupt control mode 2 Figure 4.5 (1) Stack Status after Exception Handling (Normal Modes: Not available in the LSI) SP SP CCR PC (24bits) EXR Reserved* CCR PC (24bits) (a) Interrupt control mode 0 Note: * Ignored on return. (b) Interrupt control mode 2 Figure 4.5 (2) Stack Status after Exception Handling (Advanced Modes) 80 4.7 Notes on Use of the Stack When accessing word data or longword data, the LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.6 shows an example of what happens when the SP value is odd. CCR SP PC SP R1L PC H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFF SP TRAP instruction executed MOV.B R1L, @-ER7 SP set to H'FFFEFF Data saved above SP Contents of CCR lost Legend CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4.6 Operation when SP Value is Odd 81 82 Section 5 Interrupt Controller 5.1 5.1.1 Overview Features The LSI controls interrupts by means of an interrupt controller. The interrupt controller has the following features: * Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times. * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Nine external interrupts (IRQ6 is an interrupt only for the FLEXTM decoder II.) NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ7 to IRQ0. * DTC control DTC activation is performed by means of interrupts. 83 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in Figure 5.1. INTM1 INTM0 SYSCR NMIEG NMI input IRQ input NMI input unit IRQ input unit ISR ISCR IER Priority determination I I2 to I0 Interrupt request Vector number CPU Internal interrupt request SWDTEND to TEI3 IPR Interrupt controller CCR EXR Legend ISCR IER ISR IPR SYSCR : IRQ sense control register : IRQ enable register : IRQ status register : Interrupt priority register : System control register Figure 5.1 Block Diagram of Interrupt Controller 5.1.3 Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Name Nonmaskable interrupt External interrupt requests 7 to 0 Interrupt Controller Pins Symbol NMI IRQ7 to IRQ0 I/O Input Input Function Nonmaskable external interrupt; rising or falling edge can be selected Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected (IRQ6 is a dedicated interrupt for the FLEXTM decoder II) 84 5.1.4 Register Configuration Table 5.2 summarizes the registers of the interrupt controller. Table 5.2 Name System control register IRQ sense control register H IRQ sense control register L IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register I Interrupt priority register J Interrupt priority register K Interrupt priority register O Interrupt Controller Registers Abbreviation SYSCR ISCRH ISCRL IER ISR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRI IPRJ IPRK IPRO R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 2 Initial Value H'01 H'00 H'00 H'00 H'00 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 Address* 1 H'FDE5 H'FE12 H'FE13 H'FE14 H'FE15 H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC4 H'FEC5 H'FEC6 H'FEC8 H'FEC9 H'FECA H'FECE Notes: *1 Lower 16 bits of the address. *2 Can only be written with 0 for flag clearing. 5.2 5.2.1 Bit Register Descriptions System Control Register (SYSCR) : 7 -- 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 -- 0 R/W 1 -- 0 -- 0 RAME 1 R/W Initial value: R/W : SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. 85 Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control Register (SYSCR). SYSCR is initialized to H'01 by a power-on reset and in hardware standby mode. SYSCR is not initialized in software standby mode. Bits 5 and 4--Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes for the interrupt controller. Bit 5 INTM1 0 Bit 4 INTM0 0 1 1 0 1 Interrupt Control Mode 0 -- 2 -- Description Interrupts are controlled by I bit Setting prohibited Interrupts are controlled by bits I2 to I0, and IPR Setting prohibited (Initial value) Bit 3--NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. Bit 3 NMIEG 0 1 Description Interrupt request generated at falling edge of NMI input Interrupt request generated at rising edge of NMI input (Initial value) 5.2.2 Interrupt Priority Registers A to G, I to K, O (IPRA to IPRG, IPRI to IPRK, IPRO) : 7 -- 0 -- 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W 3 -- 0 -- 2 IPR2 1 R/W 1 IPR1 1 R/W 0 IPR0 1 R/W Bit Initial value: R/W : The IPR registers are thirteen 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between IPR settings and interrupt sources is shown in table 5.3. The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI. The IPR registers are initialized to H'77 by a reset and in hardware standby mode. They are not initialized in software standby mode. 86 Bits 7 and 3--Reserved: These bits cannot be modified and are always read as 0. Table 5.3 Correspondence between Interrupt Sources and IPR Settings Bits Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRI IPRJ IPRK IPRO 6 to 4 IRQ0 IRQ2 IRQ3 IRQ6 IRQ7 Watchdog timer 0 PC break TPU channel 0 TPU channel 2 8-bit timer channel 0 --* 1 2 to 0 IRQ1 IRQ4 IRQ5 DTC --* 1 A/D converter, watchdog timer 1 TPU channel 1 --* 2 8-bit timer channel 1 SCI channel 0 --* 2 --* 1 SCI channel 1 SCI channel 3 Notes: *1 Reserved bits. These bits cannot be modified and are always read as 1. *2 Reserved bits. Only 1 may be written to these bits. As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority level, level 7, by setting H'7. When interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to the CPU. 87 5.2.3 Bit IRQ Enable Register (IER) : 7 IRQ7E 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W Initial value: R/W : IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ7 to IRQ0. IER is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0--IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to IRQ0 are enabled or disabled. Bit n IRQnE 0 1 Description IRQn interrupts disabled IRQn interrupts enabled (n = 7 to 0) (Initial value) 5.2.4 ISCRH Bit IRQ Sense Control Registers H and L (ISCRH, ISCRL) : 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value: R/W ISCRL Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W : IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value: R/W : The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0. The ISCR registers are initialized to H'0000 by a reset and in hardware standby mode. 88 They are not initialized in software standby mode. Bits 15 to 0--IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB) Bits 15 to 0 IRQ7SCB to IRQ0SCB 0 IRQ7SCA to IRQ0SCA 0 1 1 0 1 Description Interrupt request generated at IRQ7 to IRQ0 input low level (initial value) Interrupt request generated at falling edge of IRQ7 to IRQ0 input Interrupt request generated at rising edge of IRQ7 to IRQ0 input Interrupt request generated at both falling and rising edges of IRQ7 to IRQ0 input 5.2.5 Bit IRQ Status Register (ISR) : 7 IRQ7F 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* Initial value: R/W : Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. 89 Bits 7 to 0--IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests. Bit n IRQnF 0 Description [Clearing conditions] * * * * 1 (Initial value) Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1) When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA = 0) When a falling edge occurs in IRQn input when falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1) When a rising edge occurs in IRQn input when rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0) When a falling or rising edge occurs in IRQn input when both-edge detection is set (IRQnSCB = IRQnSCA = 1) (n = 7 to 0) [Setting conditions] * * * * 5.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (36 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. These interrupts can be used to restore the LSI from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. The vector number for NMI interrupt exception handling is 7. 90 IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to IRQ0 have the following features: * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ7 to IRQ0. * Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER. * The interrupt priority level can be set with IPR. * The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.2. IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input Clear signal Note: n = 7 to 0 IRQn interrupt S R Q request Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0 Figure 5.3 shows the timing of setting IRQnF. o IRQn input pin IRQnF Figure 5.3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the 91 corresponding DDR to 0 and use the pin as an I/O pin for another function. Since interrupt request flags IRQ7F to IRQ0F are set when the setting condition is satisfied, regardless of the IER setting, only the necessary flags should be referenced. 5.3.2 Internal Interrupts There are 36 sources for internal interrupts from on-chip supporting modules. * For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. * The interrupt priority level can be set by means of IPR. * The DTC can be activated by a TPU, 8-bit timer, SCI, or other interrupt request. When the DTC is activated by an interrupt, the interrupt control mode and interrupt mask bits are not affected. 5.3.3 Interrupt Exception Handling Vector Table Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of the IPR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5.4. 92 Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address* Vector Number 7 16 17 18 19 20 21 22 23 DTC Watchdog timer 0 PC break A/D Watchdog timer 1 -- TPU channel 0 24 25 27 28 29 30 31 32 33 34 35 36 -- 37 38 39 Advanced Mode H'001C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C H'0060 H'0064 H'006C H'0070 H'0074 H'0078 H'007C H'0080 H'0084 H'0088 H'008C H'0090 H'0094 H'0098 H'009C IPRF6 to 4 IPRC2 to 0 IPRD6 to 4 IPRE6 to 4 IPRE2 to 0 IPRA6 to 4 IPRA2 to 0 IPRB6 to 4 IPRB2 to 0 IPRC6 to 4 IPR Priority High Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 (dedicated to the FLEXTM decoder II) IRQ7 SWDTEND (software activation interrupt end) WOVI0 (interval timer 0) PC break ADI (A/D conversion end) WOVI1 (interval timer 1) Reserved TGI0A (TGR0A input capture/compare match) TGI0B (TGR0B input capture/compare match) TGI0C (TGR0C input capture/compare match) TGI0D (TGR0D input capture/compare match) TCI0V (overflow 0) Reserved Origin of Interrupt Source External pin Low 93 Interrupt Source TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B compare match) TCI2V (overflow 2) TCI2U (underflow 2) CMIA0 (compare match A) CMIB0 (compare match B) OVI0 (overflow) Reserved CMIA1 (compare match A) CMIB1 (compare match B) OVI1 (overflow) Reserved ERI0 (receive error 0) RXI0 (reception completed 0) TXI0 (transmit data empty 0) TEI0 (transmission end 0) ERI1 (receive error 1) RXI1 (reception completed 1) TXI1 (transmit data empty 1) TEI1 (transmission end 1) ERI3 (receive error 3) RXI3 (reception completed 3) TXI3 (transmit data empty 3) TEI3 (transmission end 3) Origin of Interrupt Source TPU channel 1 Vector Address* Vector Number 40 41 42 43 Advanced Mode H'00A0 H'00A4 H'00A8 H'00AC H'00B0 H'00B4 H'00B8 H'00BC H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011C H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C H'01E0 H'01E4 H'01E8 H'01EC IPRJ2 to 0 IPRI2 to 0 IPRI6 to 4 IPRG6 to 4 IPR IPRF2 to 0 Priority High TPU channel 2 44 45 46 47 8-bit timer channel 0 -- 8-bit timer channel 1 -- SCI channel 0 64 65 66 67 68 69 70 71 80 81 82 83 84 85 86 87 120 121 122 123 SCI channel 1 IPRK6 to 4 SCI channel 3 IPRO6 to 4 Low Note: * Lower 16 bits of the start address. 94 5.4 5.4.1 Interrupt Operation Interrupt Control Modes and Interrupt Operation Interrupt operations in the LSI differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 5.5 shows the interrupt control modes. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated by the I and UI bits in the CPU's CCR, and bits I2 to I0 in EXR. Table 5.5 Interrupt Control Modes Interrupt Mask Bits I -- I2 to I0 SYSCR Interrupt Priority Setting Control Mode INTM1 INTM0 Registers 0 -- 2 1 0 0 1 0 -- -- IPR Description Interrupt mask control is performed by the I bit. Setting prohibited 8-level interrupt mask control is performed by bits I2 to I0. 8 priority levels can be set with IPR. Setting prohibited -- 1 -- -- 95 Figure 5.4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 I Interrupt acceptance control Interrupt source Default priority determination 8-level mask control Vector number IPR I2 to I0 Interrupt control mode 2 Figure 5.4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5.6 shows the interrupts selected in each interrupt control mode. Table 5.6 Interrupts Selected in Each Interrupt Control Mode (1) Interrupt Mask Bits Interrupt Control Mode 0 I 0 1 2 * Selected Interrupts All interrupts NMI interrupts All interrupts * : Don't care 96 (2) 8-Level Control In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level. Table 5.7 Interrupts Selected in Each Interrupt Control Mode (2) Selected Interrupts All interrupts Highest-priority-level (IPR) interrupt whose priority level is greater than the mask level (IPR > I2 to I0). Interrupt Control Mode 0 2 (3) Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5.8 shows operations and control signal functions in each interrupt control mode. Table 5.8 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Acceptance Control I Default Priority T Determination (Trace) Interrupt Setting Control Mode INTM1 INTM0 8-Level Control I2 to I0 IPR 0 2 0 1 0 0 X IM --* 1 X -- IM --* 2 PR -- T Legend : Interrupt operation control performed X : No operation. (All interrupts enabled) IM : Used as interrupt mask bit PR : Sets priority. -- : Not used. Notes: *1 Set to 1 when interrupt is accepted. *2 Keep the initial setting. 97 5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU's CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. [3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. 98 Program execution status Interrupt generated? Yes Yes No NMI No No I=0 Yes Hold pending No IRQ0 Yes No IRQ1 Yes TEI3 Yes Save PC and CCR I1 Read vector address Branch to interrupt handling routine Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 99 5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5.6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.4 is selected. [3] Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. 100 Program execution status Interrupt generated? Yes Yes NMI No No No Level 7 interrupt? Yes Mask level 6 or below? Yes Level 6 interrupt? No Yes Mask level 5 or below? Yes No Level 1 interrupt? No Yes No Mask level 0? Yes No Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 101 102 Interrupt acceptance Instruction prefetch Stack Vector fetch Internal operation Internal operation Interrupt handling routine instruction prefetch (1) (7) (9) 5.4.4 Interrupt level determination Wait for end of instruction o Interrupt request signal Internal address bus (3) (5) (11) (13) Interrupt Exception Handling Sequence Internal read signal Internal write signal (2) (8) Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Figure 5.7 Interrupt Exception Handling (4) (6) (10) (12) Internal data us (14) (1) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4 (6) (8) Saved PC and saved CCR (9) (11) Vector address (10) (12) Interrupt handling routine start address (vector address contents) (13) Interrupt handling routine start address ((13) = (10) (12)) (14) First instruction of interrupt handling routine 5.4.5 Interrupt Response Times The LSI is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.9 are explained in table 5.10. Table 5.9 Interrupt Response Times Normal Mode* 5 No. 1 2 3 4 5 6 Execution Status Interrupt priority determination* 1 Advanced Mode INTM1 = 0 3 (1 to 19) +2*SI 2*S K 2*S I 2*S I 2 12 to 32 INTM1 = 1 3 (1 to 19) +2*SI 3*S K 2*S I 2*S I 2 13 to 33 INTM1 = 0 3 INTM1 = 1 3 (1 to 19) +2*SI 3*S K SI 2*S I 2 12 to 32 Number of wait states until executing (1 to 19) instruction ends* 2 +2*SI PC, CCR, EXR stack save Vector fetch Instruction fetch* 3 4 2*S K SI 2*S I 2 11 to 31 Internal processing* Total (using on-chip memory) Notes: *1 *2 *3 *4 *5 Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Not available in the LSI. Table 5.10 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8 Bit Bus Symbol Instruction fetch Branch address read Stack manipulation SI SJ SK m: Number of wait states in an external device access. Internal Memory 1 2-State Access 4 3-State Access 6+2m 16 Bit Bus 2-State Access 2 3-State Access 3+m 103 5.5 5.5.1 Usage Notes Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.8 shows and example in which the CMIEA bit in 8-bit timer TCR is cleared to 0. TCR write cycle by CPU CMIA exception handling o Internal address bus TCR address Internal write signal CMIEA CMFA CMIA interrupt signal Figure 5.8 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 104 5.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.5.3 Times when Interrupts are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. 5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 105 5.6 5.6.1 DTC Activation by Interrupt Overview The DTC can be activated by an interrupt. In this case, the following options are available: * Interrupt request to CPU * Activation request to DTC * Selection of a number of the above For details of interrupt requests that can be used with to activate the DTC, see section 8, Data Transfer Controller. 5.6.2 Block Diagram Figure 5.9 shows a block diagram of the DTC interrupt controller. Interrupt request IRQ interrupt Interrupt source clear signal Selection circuit Select signal Clear signal DTCER DTC activation request vector number Control logic Clear signal DTC On-chip supporting module DTVECR SWDTE clear signal Determination of priority Interrupt controller CPU interrupt request vector number CPU I, I2 to I0 Figure 5.9 Interrupt Control for DTC 106 5.6.3 Operation The interrupt controller has three main functions in DTC control. (1) Selection of Interrupt Source: Interrupt sources can be specified as DTC activation requests or CPU interrupt requests by means of the DTCE bit of DTCERA to DTCERF, and DTCERI in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of MRB in the DTC. When the DTC has performed the specified number of data transfers and the transfer counter value is zero, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU after the DTC data transfer. (2) Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 8.3.3, DTC Vector Table, for the respective priorities. (3) Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. Table 5.11 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTCE bit of DTCERA to DTCERF and DTCERI in the DTC, and the DISEL bit of MRB in the DTC. Table 5.11 Interrupt Source Selection and Clearing Control Settings DTC DTCE 0 1 DISEL * 0 1 Interrupt Source Selection/Clearing Control DTC X CPU X Legend : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. X : The relevant bit cannot be used. * : Don't care 107 (4) Usage Note: SCI and A/D converter interrupt sources are cleared when the DTC reads or writes to the prescribed register, and are not dependent on the DTCE and DISEL bits. 108 Section 6 PC Break Controller (PBC) 6.1 Overview The PC break controller (PBC) provides functions that simplify program debugging. Using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. Four break conditions can be set in the PBC: instruction fetch, data read, data write, and data read/write. 6.1.1 Features The PC break controller has the following features: * Two break channels (A and B) * The following can be set as break compare conditions: 24 address bits Bit masking possible Bus cycle Instruction fetch Data access: data read, data write, data read/write Bus master Either CPU or CPU/DTC can be selected * The timing of PC break exception handling after the occurrence of a break condition is as follows: Immediately before execution of the instruction fetched at the set address (instruction fetch) Immediately after execution of the instruction that accesses data at the set address (data access) * Module stop mode can be set The initial setting is for PBC operation to be halted. Register access is enabled by clearing module stop mode. 109 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the PC break controller. BARA BCRA Output control Control logic Match signal Mask control Comparator Internal address Access status PC break interrupt Comparator Match signal Control logic Output control BCRB Mask control BARB Figure 6.1 Block Diagram of PC Break Controller 110 6.1.3 Register Configuration Table 6.1 shows the PC break controller registers. Table 6.1 Name Break address register A Break address register B Break control register A Break control register B Module stop control register C PC Break Controller Registers Abbreviation BARA BARB BCRA BCRB MSTPCRC R/W R/W R/W R(W)* R(W)* R/W 2 2 Initial Value H'000000 H'000000 H'00 H'00 H'FF Address* 1 H'FE00 H'FE04 H'FE08 H'FE09 H'FDEA Notes: *1 Lower 16 bits of the address. *2 Only 0 can be written, to clear the flag. 6.2 6.2.1 Bit Register Descriptions Break Address Register A (BARA) 31 -- *** 24 -- 23 22 21 20 19 18 17 16 *** 7 6 5 4 3 2 1 0 *** BAA BAA BAA BAA BAA BAA BAA BAA 23 22 21 20 19 18 17 16 *** BAA BAA BAA BAA BAA BAA BAA BAA 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Initial value Undefined Read/Write -- *** *** Unde- 0 0 0 0 0 0 0 0 fined -- R/W R/W R/W R/W R/W R/W R/W R/W *** *** R/W R/W R/W R/W R/W R/W R/W R/W BARA is a 32-bit readable/writable register that specifies the channel A break address. BAA23 to BAA0 are initialized to H'000000 by a power-on reset and in hardware standby mode. Bits 31 to 24--Reserved: These bits return an undefined value if read, and cannot be modified. Bits 23 to 0--Break Address A23 to A0 (BAA23 to BAA0): These bits hold the channel A PC break address. 111 6.2.2 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 6.2.3 Bit Break Control Register A (BCRA) : 7 CMFA 6 CDA 0 R/W 5 4 3 2 1 0 BIEA 0 R/W BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value : R/W : 0 R(W)* Note: * Only 0 can be written to bit 7, to clear this flag. BCRA is an 8-bit readable/writable register that controls channel A PC breaks. BCRA (1) selects the break condition bus master, (2) specifies bits subject to address comparison masking, and (3) specifies whether the break condition is applied to an instruction fetch or a data access. It also contains a condition match flag. BCRA is initialized to H'00 by a power-on reset and in hardware standby mode. Bit 7--Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is satisfied. This flag is not cleared to 0. Bit 7 CMFA 0 Description [Clearing condition] When 0 is written to CMFA after reading* CMFA = 1 1 [Setting condition] When a condition set for channel A is satisfied Note: * Read the state wherein CMFA = 1 twice or more, when the CMFA is polled after inhibiting the PC break interrupt. (Initial value) Bit 6--CPU Cycle/DTC Cycle Select A (CDA): Selects the channel A break condition bus master. Bit 6 CDA 0 1 Description PC break is performed when CPU is bus master PC break is performed when CPU or DTC is bus master (Initial value) 112 Bits 5 to 3--Break Address Mask Register A2 to A0 (BAMRA2 to BAMRA0): These bits specify which bits of the break address (BAA23 to BAA0) set in BARA are to be masked. Bit 5 Bit 4 Bit 3 BAMRA2 BAMRA1 BAMRA0 Description 0 0 0 1 1 0 1 1 0 0 1 1 0 1 All BARA bits are unmasked and included in break conditions (Initial value) BAA0 (lowest bit) is masked, and not included in break conditions BAA1 to 0 (lower 2 bits) are masked, and not included in break conditions BAA2 to 0 (lower 3 bits) are masked, and not included in break conditions BAA3 to 0 (lower 4 bits) are masked, and not included in break conditions BAA7 to 0 (lower 8 bits) are masked, and not included in break conditions BAA11 to 0 (lower 12 bits) are masked, and not included in break conditions BAA15 to 0 (lower 16 bits) are masked, and not included in break conditions Bits 2 and 1--Break Condition Select A (CSELA1, CSELA0): These bits selection an instruction fetch, data read, data write, or data read/write cycle as the channel A break condition. Bit 2 CSELA1 0 Bit 1 CSELA0 0 1 1 0 1 Description Instruction fetch is used as break condition Data read cycle is used as break condition Data write cycle is used as break condition Data read/write cycle is used as break condition (Initial value) Bit 0--Break Interrupt Enable A (BIEA): Enables or disables channel A PC break interrupts. Bit 0 BIEA 0 1 Description PC break interrupts are disabled PC break interrupts are enabled (Initial value) 113 6.2.4 Break Control Register B (BCRB) BCRB is the channel B break control register. The bit configuration is the same as for BCRA. 6.2.5 Bit Module Stop Control Register C (MSTPCRC) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : R/W : MSTPCRC is an 8-bit readable/writable register that performs module stop mode control. When the MSTPC4 bit is set to 1, PC break controller operation is stopped at the end of the bus cycle, and module stop mode is entered. Register read/write accesses are not possible in module stop mode. For details, see section 19.5, Module Stop Mode. MSTPCRC is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 4--Module Stop (MSTPC4): Specifies the PC break controller module stop mode. Bit 4 MSTPC4 0 1 Description PC break controller module stop mode is cleared PC break controller module stop mode is set (Initial value) 114 6.3 Operation The operation flow from break condition setting to PC break interrupt exception handling is shown in sections 6.3.1 and 6.3.2, taking the example of channel A. 6.3.1 PC Break Interrupt Due to Instruction Fetch (1) Initial settings Set the break address in BARA. For a PC break caused by an instruction fetch, set the address of the first instruction byte as the break address. Set the break conditions in BCRA. BCRA bit 6 (CDA): With a PC break caused by an instruction fetch, the bus master must be the CPU. Set 0 to select the CPU. BCRA bits 5 to 3 (BAMA2 to 0): Set the address bits to be masked. BCRA bits 2 to 1 (CSELA1 to 0): Set 00 to specify an instruction fetch as the break condition. BCRA bit 0 (BIEA): Set to 1 to enable break interrupts. (2) Satisfaction of break condition When the instruction at the set address is fetched, a PC break request is generated immediately before execution of the fetched instruction, and the condition match flag (CMFA) is set. (3) Interrupt handling After priority determination by the interrupt controller, PC break interrupt exception handling is started. 6.3.2 PC Break Interrupt Due to Data Access (1) Initial settings Set the break address in BARA. For a PC break caused by a data access, set the target ROM, RAM, I/O, or external address space address as the break address. Stack operations and branch address reads are included in data accesses. Set the break conditions in BCRA. BCRA bit 6 (CDA): Select the bus master. BCRA bits 5 to 3 (BAMA2 to 0): Set the address bits to be masked. BCRA bits 2 to 1 (CSELA1 to 0): Set 01, 10, or 11 to specify data access as the break condition. BCRA bit 0 (BIEA): Set to 1 to enable break interrupts. 115 (2) Satisfaction of break condition After execution of the instruction that performs a data access on the set address, a PC break request is generated and the condition match flag (CMFA) is set. (3) Interrupt handling After priority determination by the interrupt controller, PC break interrupt exception handling is started. 6.3.3 Notes on PC Break Interrupt Handling (1) The PC break interrupt is shared by channels A and B. The channel from which the request was issued must be determined by the interrupt handler. (2) The CMFA and CMFB flags are not cleared to 0, so 0 must be written to CMFA or CMFB after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt will be requested after interrupt handling ends. (3) A PC break interrupt generated when the DTC is the bus master is accepted after the bus has been transferred to the CPU by the bus controller. 6.3.4 Operation in Transitions to Power-Down Modes The operation when a PC break interrupt is set for an instruction fetch at the address after a SLEEP instruction is shown below. (1) When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to sleep mode, or from subactive mode to subsleep mode: After execution of the SLEEP instruction, a transition is not made to sleep mode or subsleep mode, and PC break interrupt handling is executed. After execution of PC break interrupt handling, the instruction at the address after the SLEEP instruction is executed (figure 6.2 (A)). (2) When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to subactive mode: After execution of the SLEEP instruction, a transition is made to subactive mode via direct transition exception handling. After the transition, PC break interrupt handling is executed, then the instruction at the address after the SLEEP instruction is executed (figure 6.2 (B)). (3) When the SLEEP instruction causes a transition from subactive mode to high-speed (mediumspeed) mode: After execution of the SLEEP instruction, and following the clock oscillation settling time, a transition is made to high-speed (medium-speed) mode via direct transition exception handling. After the transition, PC break interrupt handling is executed, then the instruction at the address after the SLEEP instruction is executed (figure 6.2 (C)). 116 (4) When the SLEEP instruction causes a transition to software standby mode or watch mode: After execution of the SLEEP instruction, a transition is made to the respective mode, and PC break interrupt handling is not executed. However, the CMFA or CMFB flag is set (figure 6.2 (D)). SLEEP instruction execution SLEEP instruction execution SLEEP instruction execution SLEEP instruction execution PC break exception handling System clock subclock Subclock system clock, oscillation settling time Transition to respective mode (D) Execution of instruction after sleep instruction (A) Direct transition exception handling Subactive mode Direct transition exception handling High-speed (medium-speed) mode PC break exception handling PC break exception handling Execution of instruction after sleep instruction (B) Execution of instruction after sleep instruction (C) Figure 6.2 Operation in Power-Down Mode Transitions 6.3.5 PC Break Operation in Continuous Data Transfer If a PC break interrupt is generated when the following operations are being performed, exception handling is executed on completion of the specified transfer. (1) When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction: PC break exception handling is executed after all data transfers have been completed and the EEPMOV.B instruction has ended. (2) When a PC break interrupt is generated at a DTC transfer address: PC break exception handling is executed after the DTC has completed the specified number of data transfers, or after data for which the DISEL bit is set to 1 has been transferred. 117 6.3.6 When Instruction Execution is Delayed by One State Caution is required in the following cases, as instruction execution is one state later than usual. (1) When the PBC is enabled (i.e. when the break interrupt enable bit is set to 1), execution of a one-word branch instruction (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, or RTS) located in onchip ROM or RAM is always delayed by one state. (2) When break interruption by instruction fetch is set, the set address indicates on-chip ROM or RAM space, and that address is used for data access, the instruction that executes the data access is one state later than in normal operation. (3) When break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction has one of the addressing modes shown below, and that address indicates on-chip ROM or RAM, the instruction will be one state later than in normal operation. @ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24, @aa:32, @(d:8,PC), @(d:16,PC), @@aa:8 (4) When break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction is NOP or SLEEP, or has #xx,Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the instruction will be one state later than in normal operation. 118 6.3.7 Additional Notes (1) When a PC break is set for an instruction fetch at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction: Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the instruction fetch at the next address. (2) When the I bit is set by an LDC, ANDC, ORC, or XORC instruction, a PC break interrupt becomes valid two states after the end of the executing instruction. If a PC break interrupt is set for the instruction following one of these instructions, since interrupts, including NMI, are disabled for a 3-state period in the case of LDC, ANDC, ORC, and XORC, the next instruction is always executed. For details, see section 5, Interrupt Controller. (3) When a PC break is set for an instruction fetch at the address following a Bcc instruction: A PC break interrupt is generated if the instruction at the next address is executed in accordance with the branch condition, but is not generated if the instruction at the next address is not executed. (4) When a PC break is set for an instruction fetch at the branch destination address of a Bcc instruction: A PC break interrupt is generated if the instruction at the branch destination is executed in accordance with the branch condition, but is not generated if the instruction at the branch destination is not executed. 119 120 Section 7 Bus Controller 7.1 Overview The LSI has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU and data transfer controller (DTC). 7.1.1 Features The features of the bus controller are listed below. * Manages external address space in area units Manages the external space as 8 areas of 2-Mbytes Bus specifications can be set independently for each area Burst ROM interface can be set * Basic bus interface Chip select (CS0 to CS3) can be output for areas 0 to 3 8-bit access or 16-bit access can be selected for each area 2-state access or 3-state access can be selected for each area Program wait states can be inserted for each area * Burst ROM interface Burst ROM interface can be set for area 0 Choice of 1- or 2-state burst access * Idle cycle insertion An idle cycle can be inserted in case of an external read cycle between different areas An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle * Bus arbitration function Includes a bus arbiter that arbitrates bus mastership among the CPU and DTC * Other features External bus release function 121 7.1.2 Block Diagram Figure 7.1 shows a block diagram of the bus controller. CS0 to CS3 Area decoder Internal address bus ABWCR External bus control signals ASTCR BCRH BCRL BREQ BACK Bus controller Internal data bus Internal control signals Bus mode signal WAIT Wait controller WCRH WCRL CPU bus request signal DTC bus request signal Bus arbiter CPU bus acknowledge signal DTC bus acknowledge signal Legend ABWCR ASTCR WCRH WCRL BCRH BCRL : Bus width control register : Access state control register : Wait control register H : Wait control register L : Bus control register H : Bus control register L Figure 7.1 Block Diagram of Bus Controller 122 7.1.3 Pin Configuration Table 7.1 summarizes the pins of the bus controller. Table 7.1 Name Address strobe Read High write Bus Controller Pins Symbol AS RD HWR I/O Output Output Output Function Strobe signal indicating that address output on address bus is enabled. Strobe signal indicating that external space is being read. Strobe signal indicating that external space is to be written, and upper half (D15 to D8) of data bus is enabled. Strobe signal indicating that external space is to be written, and lower half (D7 to D0) of data bus is enabled. Strobe signal indicating that areas 0 to 3 are selected. Wait request signal when accessing external 3-state access space. Request signal that releases bus to external device. Acknowledge signal indicating that bus has been released. Low write Chip select 0 to 3 Wait Bus request Bus request acknowledge LWR CS0 to CS3 WAIT BREQ BACK Output Output Input Input Output 123 7.1.4 Register Configuration Table 7.2 summarizes the registers of the bus controller. Table 7.2 Name Bus width control register Access state control register Wait control register H Wait control register L Bus control register H Bus control register L Pin function control register Bus Controller Registers Abbreviation ABWCR ASTCR WCRH WCRL BCRH BCRL PFCR R/W R/W R/W R/W R/W R/W R/W R/W Initial value H'FF/H'00* 2 H'FF H'FF H'FF H'D0 H'08 H'0D/H'00* 3 Address* 1 H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FDEB Notes: *1 Lower 16 bits of the address. *2 Determined by the MCU operating mode. Initialized to H'00 in mode 4, and to H'FF in modes 5 to 7. *3 Initialized to H'0D in modes 4 and 5, and to H'00 in modes 6 and 7. 7.2 7.2.1 Bit Register Descriptions Bus Width Control Register (ABWCR) : 7 ABW7 6 ABW6 1 R/W 0 R/W 5 ABW5 1 R/W 0 R/W 4 ABW4 1 R/W 0 R/W 3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W 1 ABW1 1 R/W 0 R/W 0 ABW0 1 R/W 0 R/W Modes 5 to 7 Initial value : R/W Mode 4 Initial value : R/W : : 1 R/W 0 R/W ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. ABWCR sets the data bus width for the external memory space. The bus width for on-chip memory and internal I/O registers is fixed regardless of the settings in ABWCR. After a power-on reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 5, 6, 7, and to H'00 in mode 4. It is not initialized in software standby mode. 124 Bits 7 to 0--Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the corresponding area is to be designated for 8-bit access or 16-bit access. Bit n ABWn 0 1 Description Area n is designated for 16-bit access Area n is designated for 8-bit access (n = 7 to 0) 7.2.2 Bit Access State Control Register (ASTCR) : 7 AST7 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W 3 AST3 1 R/W 2 AST2 1 R/W 1 AST1 1 R/W 0 AST0 1 R/W Initial value : R/W : ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR. ASTCR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0--Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is to be designated as a 2-state access space or a 3-state access space. Wait state insertion is enabled or disabled at the same time. Bit n ASTn 0 1 Description Area n is designated for 2-state access Wait state insertion in area n external space is disabled Area n is designated for 3-state access Wait state insertion in area n external space is enabled (Initial value) (n = 7 to 0) 125 7.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a power-on reset and in hardware standby mode. They are not initialized in software standby mode. WCRH Bit : 7 W71 Initial value : R/W : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3 W51 1 R/W 2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W Bits 7 and 6--Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1. Bit 7 W71 0 Bit 6 W70 0 1 1 0 1 Description Program wait not inserted when external space area 7 is accessed 1 program wait state inserted when external space area 7 is accessed 2 program wait states inserted when external space area 7 is accessed 3 program wait states inserted when external space area 7 is accessed (Initial value) Bits 5 and 4--Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit 5 W61 0 Bit 4 W60 0 1 1 0 1 Description Program wait not inserted when external space area 6 is accessed 1 program wait state inserted when external space area 6 is accessed 2 program wait states inserted when external space area 6 is accessed 3 program wait states inserted when external space area 6 is accessed (Initial value) 126 Bits 3 and 2--Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 W51 0 Bit 2 W50 0 1 1 0 1 Description Program wait not inserted when external space area 5 is accessed 1 program wait state inserted when external space area 5 is accessed 2 program wait states inserted when external space area 5 is accessed 3 program wait states inserted when external space area 5 is accessed (Initial value) Bits 1 and 0--Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1. Bit 1 W41 0 Bit 0 W40 0 1 1 0 1 Description Program wait not inserted when external space area 4 is accessed 1 program wait state inserted when external space area 4 is accessed 2 program wait states inserted when external space area 4 is accessed 3 program wait states inserted when external space area 4 is accessed (Initial value) WCRL Bit : 7 W31 Initial value : R/W : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3 W11 1 R/W 2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W 127 Bits 7 and 6--Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1. Bit 7 W31 0 Bit 6 W30 0 1 1 0 1 Description Program wait not inserted when external space area 3 is accessed 1 program wait state inserted when external space area 3 is accessed 2 program wait states inserted when external space area 3 is accessed 3 program wait states inserted when external space area 3 is accessed (Initial value) Bits 5 and 4--Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1. Bit 5 W21 0 Bit 4 W20 0 1 1 0 1 Description Program wait not inserted when external space area 2 is accessed 1 program wait state inserted when external space area 2 is accessed 2 program wait states inserted when external space area 2 is accessed 3 program wait states inserted when external space area 2 is accessed (Initial value) Bits 3 and 2--Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 W11 0 Bit 2 W10 0 1 1 0 1 Description Program wait not inserted when external space area 1 is accessed 1 program wait state inserted when external space area 1 is accessed 2 program wait states inserted when external space area 1 is accessed 3 program wait states inserted when external space area 1 is accessed (Initial value) 128 Bits 1 and 0--Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1. Bit 1 W01 0 Bit 0 W00 0 1 1 0 1 Description Program wait not inserted when external space area 0 is accessed 1 program wait state inserted when external space area 0 is accessed 2 program wait states inserted when external space area 0 is accessed 3 program wait states inserted when external space area 0 is accessed (Initial value) 7.2.4 Bit Bus Control Register H (BCRH) : 7 ICIS1 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W 3 0 R/W 2 -- 0 R/W 1 -- 0 R/W 0 -- 0 R/W BRSTRM BRSTS1 BRSTS0 Initial value : R/W : BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1 0 1 Description Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas (Initial value) 129 Bit 6--Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed . Bit 6 ICIS0 0 1 Description Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles (Initial value) Bit 5--Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface. Bit 5 BRSTRM 0 1 Description Area 0 is basic bus interface Area 0 is burst ROM interface (Initial value) Bit 4--Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 0 1 Description Burst cycle comprises 1 state Burst cycle comprises 2 states (Initial value) Bit 3--Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 0 1 Description Max. 4 words in burst access Max. 8 words in burst access (Initial value) Bits 2 to 0--Reserved: Only 0 should be written to these bits. 130 7.2.5 Bit Bus Control Register L (BCRL) : 7 BRLE 0 R/W 6 -- 0 R/W 5 -- 0 -- 4 -- 0 R/W 3 -- 1 R/W 2 -- 0 R/W 1 -- 0 R/W 0 WAITE 0 R/W Initial value : R/W : BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, and enabling or disabling of WAIT pin input. BCRL is initialized to H'08 by a power-on reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Bus Release Enable (BRLE): Enables or disables external bus release. Bit 7 BRLE 0 1 Description External bus release is disabled. BREQ and BACK can be used as I/O ports. (Initial value) External bus release is enabled. Bit 6--Reserved: Only 0 should be written to this bit. Bit 5--Reserved: This bit cannot be modified and is always read as 0. Bit 4--Reserved: Only 0 should be written to this bit. Bit 3--Reserved: Only 1 should be written to this bit. Bits 2 and 1--Reserved: Only 0 should be written to these bits. Bit 0--WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin. Bit 0 WAITE 0 1 Description Wait input by WAIT pin disabled. WAIT pin can be used as I/O port. Wait input by WAIT pin enabled (Initial value) 131 7.2.6 Bit Pin Function Control Register (PFCR) : 7 -- 6 -- 0 0 R/W 5 BUZZE 0 0 R/W 4 -- 0 0 R/W 3 AE3 1 0 R/W 2 AE2 1 0 R/W 1 AE1 0 0 R/W 0 AE0 1 0 R/W Modes 4 and 5 Initial value Modes 6 and 7 Initial value R/W : : 0 R/W : 0 PFCR is an 8-bit readable/writable register that performs address output control in external expanded mode. PFCR is initialized to H'0D (modes 4 and 5) or H'00 (modes 6 and 7) by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. Bits 7 and 6--Reserved: Only 0 should be written to these bits. Bit 5--BUZZ Output Enable (BUZZE): Enables or disables BUZZ output from the PF1 pin. The WDT1 input clock selected with bits PSS and CKS2 to CKS0 is output as the BUZZ signal. Bit 5 BUZZE 0 1 Description Functions as PF1 I/O pin Functions as BUZZ output pin (Initial value) Bit 4--Reserved: Only 0 should be written to this bit. Bits 3 to 0--Address Output Enable 3 to 0 (AE3 to AE0): These bits select enabling or disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is enabled for address output, the address is output regardless of the corresponding DDR setting. When a pin is disabled for address output, it becomes an output port when the corresponding DDR bit is set to 1. 132 Bit 3 AE3 0 Bit 2 AE2 0 Bit 1 AE1 0 Bit 0 AE0 0 1 Description A8 to A23 output disabled A8 output enabled; A9 to A23 output disabled A8, A9 output enabled; A10 to A23 output disabled A8 to A10 output enabled; A11 to A23 output disabled A8 to A11 output enabled; A12 to A23 output disabled A8 to A12 output enabled; A13 to A23 output disabled A8 to A13 output enabled; A14 to A23 output disabled A8 to A14 output enabled; A15 to A23 output disabled A8 to A15 output enabled; A16 to A23 output disabled A8 to A16 output enabled; A17 to A23 output disabled A8 to A17 output enabled; A18 to A23 output disabled A8 to A18 output enabled; A19 to A23 output disabled A8 to A19 output enabled; A20 to A23 output disabled A8 to A20 output enabled; A21 to A23 output disabled (Initial value* 2) A8 to A21 output enabled; A22, A23 output disabled A8 to A23 output enabled (Initial value* 1) 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Notes: *1 In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000. In expanded mode with ROM, address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to 1. *2 In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101. In ROMless expanded mode, address pins A0 to A7 are always made address output. 133 7.3 7.3.1 Overview of Bus Control Area Partitioning In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode, it controls a 64-kbyte address space comprising part of area 0 (not available in the LSI). Figure 7.2 shows an outline of the memory map. Chip select signals (CS0 to CS3) can be output for areas 0 to 3. H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) H'FFFFFF (1) Advanced mode (2) Normal mode* H'FFFF H'0000 Note: * Not available in the LSI. Figure 7.2 Overview of Area Partitioning 134 7.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. (1) Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is always set. (2) Number of Access States: Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3state access is selected functions as a 3-state access space. With the burst ROM interface, the number of access states may be determined without regard to ASTCR. When 2-state access space is designated, wait insertion is disabled. (3) Number of Program Wait States: When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected. Table 7.3 shows the bus specifications for each basic bus interface area. 135 Table 7.3 ABWCR ABWn 0 Bus Specifications for Each Area (Basic Bus Interface) ASTCR ASTn 0 1 WCRH, WCRL Wn1 -- 0 Wn0 -- 0 1 1 0 1 Bus Specifications (Basic Bus Interface) Bus Width 16 Program Wait Access States States 2 3 0 0 1 2 3 8 2 3 0 0 1 2 3 (n = 7 to 0) 1 0 1 -- 0 -- 0 1 1 0 1 7.3.3 Memory Interfaces The LSI memory interfaces comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on, and a burst ROM interface (for area 0 only) that allows direct connection of burst ROM. An area for which the basic bus interface is designated functions as normal space, and an area for which the burst ROM interface is designated functions as burst ROM space. 7.3.4 Interface Specifications for Each Area The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (7.4 and 7.5) should be referred to for further details. Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external space. When area 0 external space is accessed, the CS0 signal can be output. Either basic bus interface or burst ROM interface can be selected for area 0. 136 Areas 1 to 6: In external expansion mode, all of areas 1 to 6 is external space. When area 1 to 6 external space is accessed, the CS1 to CS3 pin signals respectively can be output. Only the basic bus interface can be used for areas 1 to 6. Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space. Only the basic bus interface can be used for the area 7. 7.3.5 Chip Select Signals The LSI can output chip select signals (CS0 to CS3) to areas 0 to 3, the signal being driven low when the corresponding external space area is accessed. Figure 7.3 shows an example of CSn (n = 0 to 3) output timing. Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR) for the port corresponding to the particular CSn pin. In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset. Pins CS1 to CS3 are placed in the input state after a power-on reset, and so the corresponding DDR should be set to 1 when outputting signals CS1 to CS3. In ROM-enabled expansion mode, pins CS0 to CS3 are all placed in the input state after a poweron reset, and so the corresponding DDR should be set to 1 when outputting signals CS0 to CS3. For details, see section 9, I/O Ports. 137 Bus cycle T1 o T2 T3 Address bus Area n external address CSn Figure 7.3 CSn Signal Output Timing (n = 0 to 3) 138 7.4 7.4.1 Basic Bus Interface Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 7.3). 7.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-Bit Access Space: Figure 7.4 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses. Upper data bus Lower data bus D15 D8 D7 D0 Byte size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Word size Figure 7.4 Access Sizes and Data Alignment Control (8-Bit Access Space) 16-Bit Access Space: Figure 7.5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. 139 In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Lower data bus Upper data bus D15 D8 D7 D0 Byte size Byte size Word size Longword size 1st bus cycle 2nd bus cycle * Even address * Odd address Figure 7.5 Access Sizes and Data Alignment Control (16-Bit Access Space) 7.4.3 Valid Strobes Table 7.4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 7.4 Area 8-bit access space Data Buses Used and Valid Strobes Access Read/ Size Write Byte Read Write Read Address -- -- Even Odd Write Even Odd Word Read Write -- -- HWR LWR RD Valid Strobe RD HWR RD Valid Invalid Valid Hi-Z Valid Upper Data Bus (D15 to D8) Valid Lower data bus (D7 to D0) Invalid Hi-Z Invalid Valid Hi-Z Valid Valid Valid 16-bit access Byte space HWR, LWR Valid Hi-Z: High impedance. Invalid: Input state; input value is ignored. 140 7.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 7.6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed , the upper half (D15 to D8) of the data bus is used. Wait states cannot be inserted. Bus cycle T1 o T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR (16-bit bus mode) Write LWR (8-bit bus mode) High High impedance D15 to D8 Valid D7 to D0 High impedance Note: n = 0 to 3 Figure 7.6 Bus Timing for 8-Bit 2-State Access Space 141 8-Bit 3-State Access Space: Figure 7.7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted. Bus cycle T1 o T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR (16-bit bus mode) Write LWR (8-bit bus mode) D15 to D8 High High impedance Valid High impedance D7 to D0 Note: n = 0 to 3 Figure 7.7 Bus Timing for 8-Bit 3-State Access Space 142 16-Bit 2-State Access Space: Figures 7.8 to 7.10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted. Bus cycle T1 o T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Note: n = 0 to 3 Figure 7.8 Bus Timing for 16-Bit 2-State Access Space (Even Address Byte Access) 143 Bus cycle T1 o T2 Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Valid Note: n = 0 to 3 Figure 7.9 Bus Timing for 16-Bit 2-State Access Space (Odd Address Byte Access) 144 Bus cycle T1 o T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 3 Figure 7.10 Bus Timing for 16-Bit 2-State Access Space (Word Access) 145 16-Bit 3-State Access Space: Figures 7.11 to 7.13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted. Bus cycle T1 o T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid High impedance D7 to D0 Note: n = 0 to 3 Figure 7.11 Bus Timing for 16-Bit 3-State Access Space (Even Address Byte Access) 146 Bus cycle T1 o T2 T3 Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Note: n = 0 to 3 Valid Figure 7.12 Bus Timing for 16-Bit 3-State Access Space (Odd Address Byte Access) 147 Bus cycle T1 o T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Note: n = 0 to 3 Valid Figure 7.13 Bus Timing for 16-Bit 3-State Access Space (Word Access) 148 7.4.5 Wait Control When accessing external space, the LSI can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings of WCRH and WCRL. Pin Wait Insertion Setting the WAITE bit in BCRH to 1 enables wait insertion by means of the WAIT pin. When external space is accessed in this state, program wait insertion is first carried out according to the settings in WCRH and WCRL. Then , if the WAIT pin is low at the falling edge of o in the last T2 or Tw state, a Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. This is useful when inserting four or more Tw states, or when changing the number of Tw states for different external devices. The WAITE bit setting applies to all areas. 149 Figure 7.14 shows an example of wait state insertion timing. By program wait By WAIT pin T1 o T2 Tw Tw Tw T3 WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Note: indicates the timing of WAIT pin sampling. Figure 7.14 Example of Wait State Insertion Timing The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT input disabled. 150 7.5 7.5.1 Burst ROM Interface Overview With the LSI, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only. One or two states can be selected for burst access. 7.5.2 Basic Timing The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state insertion is possible. One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst ROM space, it becomes 16-bit access space regardless of the setting of the ABW0 bit in ABWCR. When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when the BRSTS0 bit is set to 1, burst access of up to 8 words is performed. The basic access timing for burst ROM space is shown in figures 7.15 (a) and (b). The timing shown in figure 7.15 (a) is for the case where the AST0 and BRSTS1 bits are both set to 1, and that in figure 7.15 (b) is for the case where both these bits are cleared to 0. 151 Full access T1 o T2 T3 T1 Burst access T2 T1 T2 Address bus Only lower address changed CS0 AS RD Data bus Read data Read data Read data Figure 7.15 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) 152 Full access Burst access T1 T2 T1 T1 o Address bus Only lower address changed CS0 AS RD Data bus Read data Read data Read data Figure 7.15 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 7.5.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 7.4.5, Wait Control. Wait states cannot be inserted in a burst cycle. 153 7.6 7.6.1 Idle Cycle Operation When the LSI accesses external space , it can insert a 1-state idle cycle (TI) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on. (1) Consecutive Reads between Different Areas If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read cycle. Figure 7.16 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 o Address bus CS (area A) CS (area B) RD Data bus T2 T3 Bus cycle B T1 T2 o Address bus CS (area A) Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 , CS (area B) RD Data bus Data collision (b) Idle cycle inserted (Initial value ICIS1 = 1) Long output floating time (a) Idle cycle not inserted (ICIS1 = 0) Figure 7.16 Example of Idle Cycle Operation (1) 154 (2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 7.17 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 o Address bus CS (area A) CS (area B) RD HWR Data bus T2 T3 Bus cycle B T1 T2 o Address bus CS (area A) Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Long output floating time , CS (area B) RD HWR Data bus Data collision (b) Idle cycle inserted (Initial value ICIS0 = 1) (a) Idle cycle not inserted (ICIS0 = 0) Figure 7.17 Example of Idle Cycle Operation (2) (3) Relationship between Chip Select (CS) Signal and Read (RD) Signal Depending on the system's load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 7.18. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the initial state after reset release, idle cycle insertion (b) is set. 155 Bus cycle A T1 o Address bus CS (area A) CS (area B) RD T2 T3 Bus cycle B T1 T2 o Address bus CS (area A) CS (area B) RD Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Possibility of overlap between CS (area B) and RD (a) Idle cycle not inserted (ICIS1 = 0) (b) Idle cycle inserted (Initial value ICIS1 = 1) Figure 7.18 Relationship between Chip Select (CS) and Read (RD) 7.6.2 Pin States in Idle Cycle Table 7.5 shows pin states in an idle cycle. Table 7.5 Pins A23 to A0 D15 to D0 CSn AS RD HWR LWR Pin States in Idle Cycle Pin State Contents of next bus cycle High impedance High High High High High (n = 0 to 3) 156 7.7 7.7.1 Bus Release Overview The LSI can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. 7.7.2 Operation In external expansion mode, the bus can be released to an external device by setting the BRLE bit in BCRL to 1. Driving the BREQ pin low issues an external bus request to the LSI. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus-released state. In the external bus released state, an internal bus master can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request from the external bus master to be dropped. When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the external bus released state is terminated. In the event of simultaneous external bus release request and external access request generation, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low) 157 7.7.3 Pin States in External Bus Released State Table 7.6 shows pin states in the external bus released state. Table 7.6 Pins A23 to A0 D15 to D0 CSn AS RD HWR LWR Pin States in Bus Released State Pin State High impedance High impedance High impedance High impedance High impedance High impedance High impedance (n = 0 to 3) 158 7.7.4 Transition Timing Figure 7.19 shows the timing for transition to the bus-released state. CPU cycle CPU cycle T0 o T1 T2 External bus released state High impedance Address bus Address High impedance Data bus CSn High impedance High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK Minimum 1 state [1] [2] [3] [4] [5] [1] [2] [3] [4] [5] Low level of BREQ pin is sampled at rise of T2 state. BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master. BREQ pin state is still sampled in external bus released state. High level of BREQ pin is sampled. BACK pin is driven high, ending bus release cycle. Note: n = 0 to 3 Figure 7.19 Bus-Released State Transition Timing 159 7.7.5 Usage Note When MSTPCR is set to H'FFFFFF and a transition is made to sleep mode, the external bus release function halts. Therefore, MSTPCR should not be set to H'FFFFFF if the external bus release function is to be used in sleep mode. 7.8 7.8.1 Bus Arbitration Overview The LSI has a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU and DTC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. 7.8.2 Operation The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) DTC > CPU (Low) An internal bus access by an internal bus master, and external bus release, can be executed in parallel. In the event of simultaneous external bus release request, and internal bus master external access request generation, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low) 160 7.8.3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: * The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. See Appendix A.5, Bus States During Instruction Execution, for timings at which the bus is not transferred. * If the CPU is in sleep mode, it transfers the bus immediately. DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). 7.8.4 External Bus Release Usage Note External bus release can be performed on completion of an external bus cycle. The CS signal remains low until the end of the external bus cycle. Therefore, when external bus release is performed, the CS signal may change from the low level to the high-impedance state. 7.9 Resets and the Bus Controller In a power-on reset, the LSI, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. 161 162 Section 8 Data Transfer Controller (DTC) 8.1 Overview The LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 8.1.1 Features The features of the DTC are: * Transfer possible over any number of channels Transfer information is stored in memory One activation source can trigger a number of data transfers (chain transfer) * Wide range of transfer modes Normal, repeat, and block transfer modes available Incrementing, decrementing, and fixing of source and destination addresses can be selected * Direct specification of 16-Mbyte address space possible 24-bit transfer source and destination addresses can be specified * Transfer can be set in byte or word units * A CPU interrupt can be requested for the interrupt that activated the DTC An interrupt request can be issued to the CPU after one data transfer ends An interrupt request can be issued to the CPU after the specified data transfers have completely ended * Activation by software is possible * Module stop mode can be set The initial setting enables DTC registers to be accessed. DTC operation is halted by setting module stop mode. 163 8.1.2 Block Diagram Figure 8.1 shows a block diagram of the DTC. The DTC's register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1. Internal address bus Interrupt controller DTC Register information On-chip RAM DTCERA to DTCERF, DTCERI CPU interrupt request Legend MRA, MRB CRA, CRB SAR DAR DTCERA to DTCERF, DTCERI DTVECR DTC service request : DTC mode registers A and B : DTC transfer count registers A and B : DTC source address register : DTC destination address register : DTC enable registers A to F and I : DTC vector register Figure 8.1 Block Diagram of DTC 164 MRA MRB CRA CRB DAR SAR Interrupt request Control logic DTVECR Internal data bus 8.1.3 Register Configuration Table 8.1 summarizes the DTC registers. Table 8.1 Name DTC mode register A DTC mode register B DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B DTC enable registers DTC vector register Module stop control register A DTC Registers Abbreviation MRA MRB SAR DAR CRA CRB DTCER DTVECR MSTPCRA R/W --* 2 --* 2 --* 2 --* 2 --* 2 --* 2 R/W R/W R/W Initial Value Undefined Undefined Undefined Undefined Undefined Undefined H'00 H'00 H'3F Address* 1 --* 3 --* 3 --* 3 --* 3 --* 3 --* 3 H'FE16 to H'FE1A, H'FE1E H'FE1F H'FDE8 Notes: *1 Lower 16 bits of the address. *2 Registers within the DTC cannot be read or written to directly. *3 Register information is located in on-chip RAM addresses H'EBC0 to H'EFBF. It cannot be located in external memory space. When the DTC is used, do not clear the RAME bit in SYSCR to 0. 165 8.2 8.2.1 Bit Register Descriptions DTC Mode Register A (MRA) : 7 SM1 Undefined -- 6 SM0 Undefined -- 5 DM1 Undefined -- 4 DM0 Undefined -- 3 MD1 Undefined -- 2 MD0 Undefined -- 1 DTS Undefined -- 0 Sz Undefined -- Initial value : R/W : MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6--Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer. Bit 7 SM1 0 1 Bit 6 SM0 -- 0 1 Description SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) Bits 5 and 4--Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented, decremented, or left fixed after a data transfer. Bit 5 DM1 0 1 Bit 4 DM0 -- 0 1 Description DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) 166 Bits 3 and 2--DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 MD1 0 Bit 2 MD0 0 1 1 0 1 Description Normal mode Repeat mode Block transfer mode -- Bit 1--DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. Bit 1 DTS 0 1 Description Destination side is repeat area or block area Source side is repeat area or block area Bit 0--DTC Data Transfer Size (Sz): Specifies the size of data to be transferred. Bit 0 Sz 0 1 Description Byte-size transfer Word-size transfer 8.2.2 Bit DTC Mode Register B (MRB) : 7 CHNE Undefined -- 6 DISEL Undefined -- 5 -- Undefined -- 4 -- Undefined -- 3 -- Undefined -- 2 -- Undefined -- 1 -- Undefined -- 0 -- Undefined -- Initial value: R/W : MRB is an 8-bit register that controls the DTC operating mode. Bit 7--DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. 167 In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER is not performed. Bit 7 CHNE 0 1 Description End of DTC data transfer (activation waiting state is entered) DTC chain transfer (new register information is read, then data is transferred) Bit 6--DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are disabled or enabled after a data transfer. Bit 6 DISEL 0 1 Description After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 (the DTC clears the interrupt source flag of the activating interrupt to 0) After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the interrupt source flag of the activating interrupt to 0) Bits 5 to 0--Reserved: These bits have no effect on DTC operation in the LSI, and should always be written with 0. 8.2.3 Bit DTC Source Address Register (SAR) : 23 22 21 20 19 4 3 2 1 0 Initial value: R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 168 8.2.4 Bit DTC Destination Address Register (DAR) : 23 22 21 20 19 4 3 2 1 0 Initial value : R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. 8.2.5 Bit DTC Transfer Count Register A (CRA) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -------------------------------- CRAH CRAL CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is repeated. 8.2.6 Bit DTC Transfer Count Register B (CRB) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -------------------------------- CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. 169 8.2.7 Bit DTC Enable Registers (DTCER) : 7 DTCE7 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTCE0 0 R/W Initial value: R/W : The DTC enable registers comprise six 8-bit readable/writable registers, DTCERA to DTCERE and DTCERI, with bits corresponding to the interrupt sources that can control enabling and disabling of DTC activation. These bits enable or disable DTC service for the corresponding interrupt sources. The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode. Bit n--DTC Activation Enable (DTCEn) Bit n DTCEn 0 Description DTC activation by this interrupt is disabled [Clearing conditions] * * 1 When the DISEL bit is 1 and the data transfer has ended When the specified number of transfers have ended (Initial value) DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended (n = 7 to 0) A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources and DTCE bits is shown in table 8.4, together with the vector number generated for each interrupt controller. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. 170 8.2.8 Bit DTC Vector Register (DTVECR) : 7 0 R/(W)*1 6 0 R/(W)*2 5 0 R/(W)*2 4 0 R/(W)*2 3 0 R/(W)*2 2 0 R/(W)*2 1 0 R/(W)*2 0 0 R/(W)*2 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value: R/W : Notes: *1 Only 1 can be written to the SWDTE bit. *2 Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0. DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. DTVECR is initialized to H'00 by a reset and in hardware standby mode. Bit 7--DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. Bit 7 SWDTE 0 Description DTC software activation is disabled [Clearing conditions] * * When the DISEL bit is 0 and the specified number of transfers have not ended When 0 is written to the DISEL bit after a software-activated data transfer end interrupt (SWDTEND) request has been sent to the CPU (Initial value) 1 DTC software activation is enabled [Holding conditions] * * * When the DISEL bit is 1 and data transfer has ended When the specified number of transfers have ended During data transfer due to software activation Bits 6 to 0--DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit leftshift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420. 171 8.2.9 Bit Module Stop Control Register A (MSTPCRA) : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : MSTPCRA is an 8-bit readable/writable register that performs module stop mode control. When the MSTPA6 bit in MSTPCRA is set to 1, the DTC operation stops at the end of the bus cycle and a transition is made to module stop mode. However, 1 cannot be written in the MSTPA6 bit while the DTC is operating. For details, see section 19.5, Module Stop Mode. MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 6--Module Stop (MSTPA6): Specifies the DTC module stop mode. Bit 6 MSTPA6 0 1 Description DTC module stop mode cleared DTC module stop mode set (Initial value) 172 8.3 8.3.1 Operation Overview When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to memory. Pre-storage of register information in memory makes it possible to transfer data over any required number of channels. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single activation. Figure 8.2 shows a flowchart of DTC operation. Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE=1 No Yes Transfer Counter= 0 or DISEL= 1 No Clear an activation flag Yes Clear DTCER End Interrupt exception handling Figure 8.2 Flowchart of DTC Operation 173 The DTC transfer mode can be normal mode, repeat mode, or block transfer mode. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed. Table 8.2 outlines the functions of the DTC. Table 8.2 DTC Functions Address Registers Transfer Mode * Normal mode One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 Up to 65,536 transfers possible Repeat mode One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 After the specified number of transfers (1 to 256), the initial state resumes and operation continues Block transfer mode One transfer request transfers a block of the specified size Block size is from 1 to 256 bytes or words Up to 65,536 transfers possible A block area can be designated at either the source or destination Activation Source * * * * * * IRQ TPU TGI 8-bit timer CMI SCI TXI or RXI A/D converter ADI Software Transfer Source 24 bits Transfer Destination 24 bits * * 174 8.3.2 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a CPU interrupt source when the bit is cleared to 0. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared. Table 8.3 shows activation source and DTCER clearance. The activation source flag, in the case of RXI0, for example, is the RDRF flag of SCI0. Table 8.3 Activation Source and DTCER Clearance When the DISEL Bit Is 1, or when the Specified Number of Transfers Have Ended The SWDTE bit remains set to 1 An interrupt is issued to the CPU Interrupt activation The corresponding DTCER bit remains set to 1 The activation source flag is cleared to 0 The corresponding DTCER bit is cleared to 0 The activation source flag remains set to 1 A request is issued to the CPU for the activation source interrupt When the DISEL Bit Is 0 and the Specified Number of Activation Source Transfers Have Not Ended Software activation The SWDTE bit is cleared to 0 Figure 8.3 shows a block diagram of activation source control. For details see section 5, Interrupt Controller. Source flag cleared Clear controller Clear DTCER Clear request Select On-chip supporting module IRQ interrupt Interrupt request Selection circuit DTC DTVECR Interrupt controller Interrupt mask CPU Figure 8.3 Block Diagram of DTC Activation Source Control 175 When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities. 8.3.3 DTC Vector Table Figure 8.4 shows the correspondence between DTC vector addresses and register information. Table 8.4 shows the correspondence between activation and vector addresses. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] << 1) (where << 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector address is H'0420. The DTC reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. The register information can be placed at predetermined addresses in the on-chip RAM. The start address of the register information should be an integral multiple of four. The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip RAM. Note: * Not available in the LSI. 176 Table 8.4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Interrupt Source Software Vector Number DTVECR Vector Address H'0400+ (DTVECR [6:0] <<1) H'0420 H'0422 H'0424 H'0426 H'0428 H'042A H'042C H'042E H'0438 H'0440 H'0442 H'0444 H'0446 H'0450 H'0452 H'0458 H'045A H'0480 H'0482 H'0488 H'048A Interrupt Source Write to DTVECR DTCE*1 -- Priority High IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6* IRQ7 ADI (A/D conversion end) TGI0A (GR0A compare match/ input capture) TGI0B (GR0B compare match/ input capture) TGI0C (GR0C compare match/ input capture) TGI0D (GR0D compare match/ input capture) TGI1A (GR1A compare match/ input capture) TGI1B (GR1B compare match) TGI2A (GR2A compare match/ input capture) TGI2B (GR2B compare match) CMIA0 (compare match A) CMIB0 (compare match B) CMIA1 (compare match A) CMIB1 (compare match B) 2 External pin 16 17 18 19 20 21 22 23 DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC7 DTCEC6 DTCED3 DTCED2 DTCED1 DTCED0 Low A/D TPU channel 0 28 32 33 34 35 TPU channel 1 40 41 TPU channel 2 44 45 8-bit timer channel 0 8-bit timer channel 1 64 65 68 69 177 Interrupt Source RXI0 (reception complete 0) TXI0 (transmit data empty 0) RXI1 (reception complete 1) TXI1 (transmit data empty 1) RXI3 (reception complete 3) TXI3 (transmit data empty 3) Origin of Interrupt Source SCI channel 0 SCI channel 1 SCI channel 3 Vector Number 81 82 85 86 121 122 Vector Address H'04A2 H'04A4 H'04AA H'04AC H'04F2 H'04F4 DTCE*1 DTCEE3 DTCEE2 DTCEE1 DTCEE0 DTCEI7 DTCEI6 Priority High Low Notes: *1 DTCE bits with no corresponding interrupt are reserved, and should be written with 0. *2 IRQ6 is a dedicated interrupt source for the FLEXTM decoder II. DTC vector address Register information start address Register information Chain transfer Figure 8.4 Correspondence between DTC Vector Address and Register Information 178 8.3.4 Location of Register Information in Address Space Figure 8.5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (contents of the vector address). In the case of chain transfer, register information should be located in consecutive areas. Locate the register information in the on-chip RAM (addresses: H'FFEBC0 to H'FFEFBF). Lower address Register information start address 0 MRA MRB CRA MRA MRB CRA 4 bytes SAR DAR CRB Register information for 2nd transfer in chain transfer 1 2 SAR DAR CRB Register information 3 Chain transfer Figure 8.5 Location of Register Information in Address Space 179 8.3.5 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 8.5 lists the register information in normal mode and figure 8.6 shows memory mapping in normal mode. Table 8.5 Name DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B Register Information in Normal Mode Abbreviation SAR DAR CRA CRB Function Designates source address Designates destination address Designates transfer count Not used SAR Transfer DAR Figure 8.6 Memory Mapping in Normal Mode 180 8.3.6 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 8.6 lists the register information in repeat mode and figure 8.7 shows memory mapping in repeat mode. Table 8.6 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Information in Repeat Mode Abbreviation SAR DAR CRAH CRAL CRB Function Designates source address Designates destination address Holds number of transfers Designates transfer count Not used SAR or DAR Repeat area Transfer DAR or SAR Figure 8.7 Memory Mapping in Repeat Mode 181 8.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt is requested. Table 8.7 lists the register information in block transfer mode and figure 8.8 shows memory mapping in block transfer mode. Table 8.7 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Information in Block Transfer Mode Abbreviation SAR DAR CRAH CRAL CRB Function Designates source address Designates destination address Holds block size Designates block size count Transfer count 182 First block SAR or DAR * * * Block area Transfer DAR or SAR Nth block Figure 8.8 Memory Mapping in Block Transfer Mode 183 8.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8.9 shows the memory map for chain transfer. Source Destination Register information CHNE = 1 DTC vector address Register information start address Register information CHNE = 0 Source Destination Figure 8.9 Chain Transfer Memory Map In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. 184 8.3.9 Operation Timing Figures 8.10 to 8.12 show an example of DTC operation timing. o DTC activation request DTC request Data transfer Vector read Address Transfer information read Read Write Transfer information write Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) o DTC activation request DTC request Vector read Address Transfer information read Data transfer Read Write Read Write Transfer information write Figure 8.11 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) 185 o DTC activation request DTC request Data transfer Vector read Address Transfer information read Read Write Read Write Data transfer Transfer Transfer information information write read Transfer information write Figure 8.12 DTC Operation Timing (Example of Chain Transfer) 8.3.10 Number of DTC Execution States Table 8.8 lists execution statuses for a single DTC data transfer, and table 8.9 shows the number of states required for each execution status. Table 8.8 DTC Execution Statuses Vector Read I 1 1 1 Register Information Read/Write Data Read J K 6 6 6 1 1 N Data Write L 1 1 N Internal Operations M 3 3 3 Mode Normal Repeat Block transfer N: Block size (initial setting of CRAH and CRAL) 186 Table 8.9 Number of States Required for Each Execution Status OnChip RAM 32 1 SI SJ -- 1 OnChip ROM 16 1 1 -- On-Chip I/O Registers 8 2 -- -- 16 2 -- -- Object to be Accessed Bus width Access states Vector read Execution status Register information read/write Byte data read Word data read Byte data write Word data write Internal operation External Devices 8 2 4 -- 8 3 6+2m -- 16 2 2 -- 16 3 3+m -- SK SK SL SL SM 1 1 1 1 1 1 1 1 1 1 2 4 2 4 1 2 2 2 2 1 2 4 2 4 1 3+m 6+2m 3+m 6+2m 1 2 2 2 2 1 3+m 3+m 3+m 3+m 1 m: Number of wait states in external device access The number of execution states is calculated from the formula below. Note that means the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I * SI + (J * SJ + K * SK + L * SL ) + M * SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from the on-chip ROM to an internal I/O register, the time required for the DTC operation is 13 states. The time from activation to the end of the data write is 10 states. 8.3.11 Procedures for Using DTC Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. 187 [5] After the end of one data transfer, or after the specified number of data transfers have ended, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. Activation by Software: The procedure for using the DTC with software activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Check that the SWDTE bit is 0. [4] Write 1 to SWDTE bit and the vector number to DTVECR. [5] Check the vector number written to DTVECR. [6] After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the SWDTE bit is held at 1 and a CPU interrupt is requested. 8.3.12 Examples of Use of the DTC (1) Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. [1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. [2] Set the start address of the register information at the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. [5] Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 188 [6] When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine should perform wrap-up processing. (2) Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. [1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. [2] Set the start address of the register information at the DTC vector address (H'04C0). [3] Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software. [4] Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. [5] Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. [6] If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. [7] After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform other wrap-up processing. 189 8.4 Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control. In the case of activation by software, a software activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers have ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine should clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1. 8.5 Usage Notes Module Stop: DTC operation can be disabled or enabled using the module stop control register. The initial setting is for DTC operation to be enabled. Register access is disabled by setting module stop mode. Module stop mode cannot be set during DTC operation. For details, refer to section 19, Power-Down Modes. On-Chip RAM: The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0. DTCE Bit Setting: For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. 190 Section 9 I/O Ports 9.1 Overview The LSI has nine I/O ports (ports 1, 3, and A to G), and one input-only port (port 4). Also it has one internal 4-bit I/O port (port 7), one internal 1-bit I/O port (port 36), and one input-only port (port G0) for the FLEXTM decoder II interface. Table 9.1 summarizes the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output (not provided for the input-only ports), a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. Ports A to E have a built-in MOS input pull-up function, and in addition to DR and DDR, have a MOS input pull-up control register (PCR) to control the on/off status of the MOS input pull-ups. Ports 3 and A include an open-drain control register (ODR) that controls the on/off status of the output buffer PMOS. All the ports can drive a single TTL load and 30 pF capacitive load. The IRQ pins are Schmitt-triggered inputs. Block diagrams of each port are give in Appendix C, I/O Port Block Diagrams. 191 Table 9.1 H8S/2276 Series Port Functions Port Description Pins P16/TIOCA2/IRQ1 P14/TIOCA1/IRQ0 P13/TIOCD0/TCLKB/A23 P12/TIOCC0/TCLKA/A22 P11/TIOCB0/A21 P10/TIOCA0/A20 Mode 4 Mode 5 Mode 6 Mode 7 6-bit I/O port also functioning as TPU I/O pins (TCLKA, TCLKB, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCA2) and interrupt input pins (IRQ0, IRQ1) Port 1 * 6-bit I/O port * Schmitt-triggered input (IRQ0, IRQ1) 6-bit I/O port also functioning as TPU I/O pins (TCLKA, TCLKB, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCA2), interrupt input pins (IRQ0, IRQ1), and address output (A20 to A23) Port 3 * 6-bit I/O port * Open-drain output capability * Schmitt-triggered input (IRQ4, IRQ5) * 1-bit I/O port (dedicated internal I/O port for the FLEXTM decoder II interface) Port 4 * 8-bit input port P35/SCK1/IRQ5 P34/RxD1 P33/TxD1 P32/SCK0/IRQ4 P31/RxD0 P30/TxD0 P36 6-bit I/O port also functioning as SCI (channel 0 and 1) I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1) and interrupt input pins (IRQ4, IRQ5) 1-bit I/O port P47/AN7 P46/AN6 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 P77/TxD3 P76/RxD3 P75/SCK3 P74 PA3/A19 to PA0/A16 8-bit input port also functioning as A/D converter analog input (AN7 to AN0) Port 7 * 4-bit I/O port (dedicated I/O port for the FLEXTM decoder II interface) Port A * 4-bit I/O port * Built-in MOS input pull-up * Open-drain output capability Port B * 8-bit I/O port * Built-in MOS input pull-up Port C * 8-bit I/O port * Built-in MOS input pull-up Port D * 8-bit I/O port * Built-in MOS input pull-up 4-bit I/O port also functioning as SCI (channel 3) I/O pins (TxD3, RxD3, SCK3) 4-bit I/O port also functioning as address output (A19 to A16) 4-bit I/O port PB7/A15 to PB0/A8 8-bit I/O port also functioning as address output (A15 to A8) 8-bit I/O port PC7/A7 to PC0/A0 Address output (A7 to A0) When DDR = 0: 8-bit I/O port Input port When DDR = 1: Address output 8-bit I/O port PD7/D15 to PD0/D8 Data bus input/output (D15 to D8) 192 Port Description Pins PE7/D7 to PE0/D0 Mode 4 Mode 5 Mode 6 Mode 7 8-bit I/O port Port E * 8-bit I/O port * Built-in MOS input pull-up Port F * 8-bit I/O port * Schmitt-triggered input (IRQ3, IRQ2) In 8-bit bus mode: 8-bit I/O port In 16-bit bus mode: Data bus input/output (D7 to D0) When DDR = 0: Input port When DDR = 1 (after reset): o output PF7/o When DDR = 0 (after reset): Input port When DDR = 1: o output 3-bit I/O port PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 AS, RD, HWR output In 16-bit bus mode: LWR output In 8-bit bus mode: I/O port also functioning as interrupt input pin (IRQ3) and A/D converter input (ADTRG) I/O port also functioning as interrupt input pin (IRQ3) and A/D converter input (ADTRG) I/O port I/O ports also functioning as WDT output pin (BUZZ) and interrupt input pin (IRQ2) I/O port I/O ports also functioning as interrupt input pin (IRQ7) PF2/WAIT PF1/BACK/BUZZ PF0/BREQ/IRQ2 When WAITE = 0 (after reset): I/O port When WAITE = 1: WAIT input When BRLE = 0 (after reset): I/O ports also functioning as WDT output pin (BUZZ) and interrupt input pin (IRQ2) When BRLE = 1: BREQ input, BACK output, and interrupt input pin (IRQ2) When DDR = 0* 1 : Input port When DDR = 1* 2 : CS0 output When DDR = 0 (after reset): Input ports also functioning as interrupt input pin (IRQ7) When DDR = 1: CS1, CS2, CS3 output and interrupt input pin (IRQ7) Port G * 4-bit I/O port * Schmitt-triggered input (IRQ7) PG4/CS0 PG3/CS1 PG2/CS2 PG1/CS3/IRQ7 PG0/IRQ6 * 1-bit input port (dedicated internal I/O port for the FLEXTM decoder II interface) Input port also functioning as interrupt input pin (IRQ6) Notes: *1 After mode 6 reset *2 After mode 4 or 5 reset 193 9.2 9.2.1 Port 1 Overview Port 1 is a 6-bit I/O port. Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, and TIOCA2), external interrupt pins (IRQ0 and IRQ1), and address bus output pins (A23 to A20). Port 1 pin functions depend on the operating mode. The interrupt input pins (IRQ0 and IRQ1) are Schmitt-triggered inputs. Figure 9.1 shows the port 1 pin configuration. Port 1 pins: Pin functions in modes 4 to 6 P16 (input/output)/TIOCA2 (input/output)/IRQ1 (input) P14 (input/output)/TIOCA1 (input/output)/IRQ0 (input) Port 1 P13 (input/output)/TIOCD0 (input/output)/TCLKB (input)/A23 (output) P12 (input/output)/TIOCC0 (input/output)/TCLKA (input)/A22 (output) P11 (input/output)/TIOCB0 (input/output)/A21(output) P10 (input/output)/TIOCA0 (input/output)/A20(output) Pin functions in mode 7 P16 (input/output)/TIOCA2 (input/output)/IRQ1 (input) P14 (input/output)/TIOCA1 (input/output)/IRQ0 (input) P13 (input/output)/TIOCD0 (input/output)/TCLKB (input) P12 (input/output)/TIOCC0 (input/output)/TCLKA (input) P11 (input/output)/TIOCB0 (input/output) P10 (input/output)/TIOCA0 (input/output) Figure 9.1 Port 1 Pin Functions 194 9.2.2 Register Configuration Table 9.2 shows the port 1 register configuration. Table 9.2 Name Port 1 data direction register Port 1 data register Port 1 register Notes: *1 Lower 16 bits of the address. *2 Value of bits 6 and 4 to 0. Port 1 Registers Abbreviation P1DDR P1DR PORT1 R/W W R/W R Initial Value* 2 Address* 1 H'00 H'00 Undefined H'FE30 H'FF00 H'FFB0 Port 1 Data Direction Register (P1DDR) Bit : 7 -- Initial value : Undefined R/W : W 6 P16DDR 0 W 5 -- Undefined W 4 3 2 1 0 P14DDR P13DDR P12DDR P11DDR P10DDR 0 W 0 W 0 W 0 W 0 W P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read. Bits 7 and 5 are reserved; these bits should always be written with 0. P1DDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. (a) Modes 4, 5, and 6 If address output is enabled by the setting of bits AE3 to AE0 in PFCR, pins P13 to P10 are address outputs. Pins P16 and P15, and pins P13 to P10 when address output is disabled, are output ports when the corresponding P1DDR bits are set to 1, and input ports when the corresponding P1DDR bits are cleared to 0. (b) Mode 7 Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output port, while clearing the bit to 0 makes the pin an input port. 195 Port 1 Data Register (P1DR) Bit : 7 -- Initial value : Undefined R/W : R/W 6 P16DR 0 R/W 5 -- Undefined R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P16, P14 to P10). Bits 7 and 5 are reserved; these bits should always be written with 0 and will return an undefined value if read. P1DR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. Port 1 Register (PORT1) Bit : 7 -- Initial value : Undefined R/W : -- 6 P16 --* R 5 -- Undefined -- 4 P14 --* R 3 P13 --* R 2 P12 --* R 1 P11 --* R 0 P10 --* R Note: * Determined by the state of pins P16, P14 to P10. PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 1 pins (P16, P14 to P10) must always be performed on P1DR. Bits 7 and 5 are reserved; these bits will return an undefined value if read. If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while P1DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT1 contents are determined by the pin states, as P1DDR and P1DR are initialized. PORT1 retains its previous state in software standby mode. 196 9.2.3 Pin Functions Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, and TIOCA2), external interrupt input pins (IRQ0 and IRQ1), and address output pins (A23 to A20). Port 1 pin functions are shown in table 9.3. Table 9.3 Pin P16/ TIOCA2/ IRQ1 Port 1 Pin Functions Pin Functions and Selection Method The pin function is switched as shown below according to the combination of the TPU channel 2 settings (bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 in TIOR2, and bits CCLR1 and CCLR0 in TCR2) and bit P16DDR. TPU channel 2 settings P16DDR Pin function (1) in table below -- TIOCA2 output 0 P16 input (2) in table below 1 P16 output TIOCA2 input* 1 IRQ1 input* 2 Notes: *1 TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1. *2 When used as an external interrupt pin, do not use for another function. TPU channel 2 settings MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01xx (2) (1) (1) B'0011 Other than B'xx00 (2) B'001x B'0010 B'0000 B'0001 to B'0011 B'xx00 Other B'0100 B'0101 to B'0111 than B'1xxx B'xx00 -- -- -- Output compare output -- -- -- CCLR1, CCLR0 Output function Other than B'01 B'01 -- PWM PWM mode 2 mode 1 output output x: Don't care 197 Pin P14/ TIOCA1/ IRQ0 Pin Functions and Selection Method The pin function is switched as shown below according to the combination of the TPU channel 1 settings (bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1) and bit P14DDR. TPU channel 1 settings P14DDR Pin function (1) in table below -- TIOCA1 output 0 P14 input (2) in table below 1 P14 output TIOCA1 input* 1 IRQ0 input* 2 Notes: *1 TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0= B'10xx. *2 When used as an external interrupt pin, do not use for another function. TPU channel 1 settings MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01xx (2) (1) (1) B'0011 Other than B'xx00 (2) B'001x B'0010 B'0000 B'0001 to B'0011 B'xx00 Other B'0100 B'0101 to B'0111 than B'1xxx B'xx00 -- -- -- Output compare output -- -- -- CCLR1, CCLR0 Output function Other than B'01 B'01 -- PWM PWM mode 2 mode 1 output output x: Don't care 198 Pin P13/ TIOCD0/ TCLKB/ A23 Pin Functions and Selection Method The pin function is switched as shown below according to the combination of the operating mode, the TPU channel 0 settings (bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, bits AE3 to AE0 in PFCR, and bit P13DDR. Operating mode AE3 to AE0 TPU channel 0 settings P13DDR Pin function Modes 4, 5, 6 Other than B'1111 (1) (2) in table below in table below -- TIOCD0 output 0 1 B'1111 -- -- -- -- A23 output Mode 7 -- (1) (2) in table below in table below -- TIOCD0 output 0 1 P13 P13 input output TIOCD0 input* 1 P13 P13 input output TIOCD0 input* 1 TCLKB input* 2 TCLKB input* 2 Notes: *1 TIOCD0 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx. *2 TCLKB input when the setting for any of TCR0 to TCR2 is: TPSC2 to TPSC0 = B'101. Also, TCLKB input when channel 1 is set to phase counting mode. TPU channel 0 settings MD3 to MD0 IOD3 to IOD0 (2) (1) B'0000 B'0000 B'0001 to B'0011 B'0100 B'0101 to B'0111 B'1xxx -- -- -- Output compare output (2) B'0010 -- B'xx00 (2) (1) B'0011 Other than B'xx00 (2) CCLR2 to CCLR0 Output function -- -- -- -- Other than B'110 PWM mode 2 output B'110 -- x: Don't care 199 Pin P12/ TIOCC0/ TCLKA/ A22 Pin Functions and Selection Method The pin function is switched as shown below according to the combination of the operating mode, the TPU channel 0 settings (bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, bits AE3 to AE0 in PFCR, and bit P12DDR. Operating mode AE3 to AE0 TPU channel 0 settings P12DDR Pin function Modes 4, 5, 6 Other than B'1111 (1) (2) in table below in table below -- TIOCC0 output 0 1 B'1111 -- -- -- -- A22 output Mode 7 -- (1) (2) in table below in table below -- TIOCC0 output 0 1 P12 P12 input output TIOCC0 input* 1 P12 P12 input output TIOCC0 input* 1 TCLKA input* 2 TCLKA input* 2 Notes: *1 TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx. *2 TCLKA input when the setting for any of TCR0 to TCR2 is: TPSC2 to TPSC0 = B'100. Also, TCLKA input when channel 1 is set to phase counting mode. TPU channel 0 settings MD3 to MD0 IOC3 to IOC0 (2) (1) B'0000 (2) (1) (1) B'0011 Other than B'xx00 (2) B'001x B'0010 B'0000 B'0001 to B'0011 B'xx00 Other B'0100 B'0101 to B'0111 than B'1xxx B'xx00 -- -- -- Output compare output -- -- -- CCLR2 to CCLR0 Output function Other than B'101 B'101 -- PWM PWM mode 2 mode 1 output output* 3 Note: x: Don't care *3 Output is disabled for TIOCD0. When BFA = 1 or BFB = 1 in TMDR0, output is disabled and the settings in (2) apply. 200 Pin P11/ TIOCB0/ A21 Pin Functions and Selection Method The pin function is switched as shown below according to the combination of the operating mode, the TPU channel 0 settings (bits MD3 to MD0 in TMDR0 and bits IOB3 to IOB0 in TIOR0H), bits AE3 to AE0 in PFCR, and bit P11DDR. Operating mode AE3 to AE0 TPU channel 0 settings P11DDR Pin function Modes 4, 5, 6 Other than B'111x (1) (2) in table below in table below -- TIOCB0 output 0 1 B'111x -- -- -- A21 output Mode 7 -- (1) (2) in table below in table below -- TIOCB0 output 0 1 P11 P11 input output TIOCB0 input* P11 P11 input output TIOCB0 input* Note: * TIOCB0 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx. TPU channel 0 settings MD3 to MD0 IOB3 to IOB0 (2) (1) B'0000 B'0000 B'0001 to B'0011 B'0100 B'0101 to B'0111 B'1xxx -- -- -- Output compare output (2) B'0010 -- B'xx00 (2) (1) B'0011 Other than B'xx00 (2) CCLR2 to CCLR0 Output function -- -- -- -- Other than B'010 PWM mode 2 output B'010 -- x: Don't care 201 Pin P10/ TIOCA0/ A20 Pin Functions and Selection Method The pin function is switched as shown below according to the combination of the operating mode, the TPU channel 0 settings (bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bits AE3 to AE0 in PFCR, and bit P10DDR. Operating mode AE3 to AE0 Modes 4, 5, 6 Other than (B'1101 or B'111x) B'1101 or B'111x (1) (2) in table below in table below -- TIOCA0 output 0 1 -- -- -- A20 output Mode 7 -- TPU channel 0 settings P10DDR Pin function (1) (2) in table below in table below -- TIOCA0 output 0 1 P10 P10 input output TIOCA0 input* 1 P10 P10 input output TIOCA0 input* 1 Note: *1 TIOCA0 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx. (2) (1) B'0000 (2) (1) (1) B'0011 Other than B'xx00 (2) TPU channel 0 settings MD3 to MD0 IOA3 to IOA0 B'001x B'0010 B'0000 B'0001 to B'0011 B'xx00 Other B'0100 B'0101 to B'0111 than B'1xxx B'xx00 -- -- -- Output compare output -- -- -- CCLR2 to CCLR0 Output function Other than B'001 B'001 -- PWM PWM mode 2 mode 1 output output* 2 x: Don't care Note: *2 Output is disabled for TIOCB0. 202 9.3 Port 3* Note: * P36, only is a internal I/O port. 9.3.1 Overview Port 3 consists of a 6-bit I/O port and on-chip 1-bit I/O port that is a dedicated port for the FLEXTM decoder II interface. Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1) and external interrupt input pins (IRQ4 and IRQ5). Port 3 pin functions are the same in all operating modes. The interrupt input pins (IRQ4 and IRQ5) are Schmitt-triggered inputs. Figure 9.2 shows the port 3 pin configuration. Port 3 pins P36 (input/output) P35 (input/output)/SCK1(input/output)/IRQ5 (input) P34 (input/output)/RxD1 (input) Port 3 P33 (input/output)/TxD1 (output) P32 (input/output)/SCK0(input/output)/IRQ4 (input) P31 (input/output)/RxD0 (input) P30 (input/output)/TxD0 (output) Note: : Connected inside the chip (P36 only) FLEXTM decoder II SS Figure 9.2 Port 3 Pin Functions 203 9.3.2 Register Configuration Table 9.4 shows the port 3 register configuration. Table 9.4 Name Port 3 data direction register Port 3 data register Port 3 register Port 3 open-drain control register Notes: *1 Lower 16 bits of the address. *2 Value of bits 6 to 0. Port 3 Registers Abbreviation P3DDR P3DR PORT3 P3ODR R/W W R/W R R/W Initial Value* 2 Address* 1 H'00 H'00 H'00 H'00 H'FE32 H'FF02 H'FFB2 H'FE46 Port 3 Data Direction Register (P3DDR) Bit : 7 -- Initial value : R/W : Undefined 6 5 4 3 2 1 0 P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR 0 W 0 W 0 W 0 W 0 W 0 W 0 W -- P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 3. P3DDR cannot be read; if it is, an undefined value will be returned. Bit 7 is reserved; this bit cannot be modified and will return an undefined value if read. Setting a P3DDR bit to 1 makes the corresponding port 3 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P3DDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. 204 Port 3 Data Register (P3DR) Bit : 7 -- Initial value : R/W : Undefined 6 P36DR 0 R/W 5 P35DR 0 R/W 4 P34DR 0 R/W 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 P30DR 0 R/W -- P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P36 to P30). Bit 7 is reserved; this bit cannot be modified and will return an undefined value if read. P3DR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. Port 3 Register (PORT3) Bit : 7 -- Initial value : R/W : 6 -- 5 P35 --* R 4 P34 --* R 3 P33 --* R 2 P32 --* R 1 P31 --* R 0 P30 --* R Undefined Undefined -- R Note: * Determined by the state of pins P35 to P30. PORT3 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 3 pins (P35 to P30) must always be performed on P3DR. Bits 7 and 6 are reserved; these bits will return an undefined value if read. If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 3 read is performed while P3DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT3 contents are determined by the pin states, as P3DDR and P3DR are initialized. PORT3 retains its previous state in software standby mode. 205 Port 3 Open-Drain Control Register (P3ODR) Bit : 7 -- Initial value : R/W : 6 -- 5 4 3 2 1 0 P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Undefined Undefined -- R/W P3ODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port 3 pin (P35 to P30). Bits 7 and 6 are reserved; these bits should always be written with 0 and will return an undefined value if read. Setting a P3ODR bit to 1 makes the corresponding port 3 pin an NMOS open-drain output pin, while clearing the bit to 0 makes the pin a CMOS output pin. P3ODR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. 9.3.3 Pin Functions Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1) and interrupt input pins (IRQ4 and IRQ5). Port 3 pin functions are shown in table 9.5. 206 Table 9.5 Pin Port 3 Pin Functions Pin Functions and Selection Method P36 The pin function is switched as shown below according to the setting of bit P36DDR. (dedicated internal I/O port for the P36DDR 0 1 FLEXTM decoder II Pin function P36 input P36 output interface) P35/SCK1/ The pin function is switched as shown below according to the combination of bit C/A in IRQ5 SMR, bits CKE0 and CKE1 in SCR of SCI1, and bit P35DDR. CKE1 C/A CKE0 P35DDR Pin function 0 P35 input 0 1 1 0 0 1 -- 1 1 1 -- -- 1 -- -- -- P35 output* SCK1 output* SCK1 output* SCK1 input IRQ5 input* 2 Notes: *1 NMOS open-drain output when P35ODR = 1. *2 When used as an external interrupt pin, do not use for another function. P34/RxD1 The pin function is switched as shown below according to the combination of bit RE in SCR of SCI1 and bit P34DDR. RE P34DDR Pin function 0 P34 input 0 1 P34 output* 1 -- RxD1 input Note: * NMOS open-drain output when P34ODR = 1. P33/TxD1 The pin function is switched as shown below according to the combination of bit TE in SCR of SCI1 and bit P33DDR. TE P33DDR Pin function 0 P33 input 0 1 P33 output* 1 -- TxD1 output* Note: * NMOS open-drain output when P33ODR = 1. 207 Pin Pin Functions and Selection Method P32/SCK0/ The pin function is switched as shown below according to the combination of bit C/A in IRQ4 SMR, bits CKE0 and CKE1 in SCR of SCI0, and bit P32DDR. CKE1 C/A CKE0 P32DDR Pin function 0 P32 input 0 1 P32 output* 1 0 0 1 -- SCK0 output* 1 IRQ4 input* 2 1 -- -- SCK0 output* 1 1 -- -- -- SCK0 input Notes: *1 NMOS open-drain output when P32ODR = 1. *2 When used as an external interrupt pin, do not use for another function. P31/RxD0 The pin function is switched as shown below according to the combination of bit RE in SCR of SCI0 and bit P31DDR. RE P31DDR Pin function 0 P31 input 0 1 P31 output* 1 -- RxD0 input Note: * NMOS open-drain output when P31ODR = 1. P30/TxD0 The pin function is switched as shown below according to the combination of bit TE in SCR of SCI0 and bit P30DDR. TE P30DDR Pin function 0 P30 input 0 1 P30 output* 1 -- TxD0 output* Note: * NMOS open-drain output when P30ODR = 1. 9.4 9.4.1 Port 4 Overview Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins (AN0 to AN7). Port 4 pin functions are the same in all operating modes. Figure 9.3 shows the port 4 pin configuration. 208 Port 4 pins P47 (input) /AN7 (input) P46 (input) /AN6 (input) P45 (input) /AN5 (input) Port 4 P44 (input) /AN4 (input) P43 (input) /AN3 (input) P42 (input) /AN2 (input) P41 (input) /AN1 (input) P40 (input) /AN0 (input) Figure 9.3 Port 4 Pin Functions 9.4.2 Register Configuration Table 9.6 shows the port 4 register configuration. Port 4 is an input-only register, and does not have a data direction register or data register. Table 9.6 Name Port 4 register Note: * Lower 16 bits of the address. Port 4 Registers Abbreviation PORT4 R/W R Initial Value Undefined Address* H'FFB3 Port 4 Register (PORT4) Bit : 7 P47 Initial value : R/W : --* R 6 P46 --* R 5 P45 --* R 4 P44 --* R 3 P43 --* R 2 P42 --* R 1 P41 --* R 0 P40 --* R Note: * Determined by the state of pins P47 to P40. PORT4 is an 8-bit read-only register. The pin states are always read when a port 4 read is performed. This register cannot be written to. 9.4.3 Pin Functions Port 4 pins also function as A/D converter analog input pins (AN0 to AN7). 209 9.5 9.5.1 Port 7 [Internal I/O Port] Overview Port 7 is a 4-bit on-chip dedicated I/O port for the FLEXTM decoder II. Port 7 pins also function as SCI I/O pins (SCK3, RxD3, and TxD3). The functions of pins P77 to P74 are the same in all operating mode. Figure 9.4 shows the port 7 pin configuration. Port 7 pins P77 (input/output)/TxD3 (output) P76 (input)/RxD3 (input) Port 7 P75 (input/output)/SCK3 (output) P74 (input/output) MOSI MOSO SCK RESET FLEXTM decoder II Note: : Connected inside the chip Figure 9.4 Port 7 Pin Functions 210 9.5.2 Register Configuration Table 9.7 shows the port 7 register configuration. Table 9.7 Name Port 7 data direction register Port 7 data register Port 7 register Notes: *1 Lower 16 bits of the address. *2 Value of bits 7, 5, and 4. Port 7 Registers Abbreviation P7DDR P7DR PORT7 R/W W R/W R Initial Value* 2 Address* 1 H'00 H'00 Undefined H'FE36 H'FF06 H'FFB6 Port 7 Data Direction Register (P7DDR) Bit : 7 P77DDR Initial value : R/W : 0 W 6 -- Undefined 5 4 3 -- 2 -- 1 -- 0 -- P75DDR P74DDR 0 W 0 W Undefined Undefined Undefined Undefined W W W W W P7DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 7. P7DDR cannot be read; if it is, an undefined value will be read. Bits 6, 3 to 0 are reserved; these bits should always be written with 0. Setting a P7DDR bit to 1 makes the corresponding port 7 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P7DDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. Port 7 Data Register (P7DR) Bit : 7 P77DR Initial value : R/W : 0 R/W 6 -- Undefined 5 P75DR 0 R/W 4 P74DR 0 R/W 3 -- 2 -- 1 -- 0 -- Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W P7DR is an 8-bit readable/writable register that stores output data for the port 7 pins (P77, P75, P74). Bits 6, 3 to 0 are reserved; these bits should always be written with 0 and will return an undefined value if read. 211 P7DR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. Port 7 Register (PORT7) Bit : 7 -- Initial value : R/W : Undefined 6 P76 --* R 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- Undefined Undefined Undefined Undefined Undefined Undefined R R R R R R R Note: * Determined by the state of MISO of FLEXTM decoder II. PORT7 is an 8-bit read-only register. The state of MISO of FLEXTM decoder II is always read when a port 7 read is performed. It cannot be written to. Writing of output data for the port 7 pins (P77, P75, P74) must always be performed on P7DR. Bits 7, 5 to 0 are reserved; these bits will return an undefined value if read. 212 9.5.3 Pin Functions Port 7 pins also function as SCI I/O pins (SCK3, RxD3, and TxD3). Port 7 pin functions are shown in table 9.8. Table 9.8 Pin P77/TxD3 Port 7 Pin Functions Pin Functions and Selection Method The pin function is switched as shown below according to the combination of bit TE in SCR of SCI3 and bit P77DDR. TE P77DDR Pin function 0 P77 input 0 1 P77 output 1 TxD3 output 1 0 Setting prohibited P76/RxD3 The pin function is switched as shown below according to the setting of bit RE in SCR of SCI3. RE Pin function 0 P76 input 1 RxD3 input P75/SCK3 The pin function is switched as shown below according to the combination of bit C/A in SMR, bits CKE0 and CKE1 of SCR of SCI3, and bit P75DDR. CKE1 P75DDR C/A CKE0 Pin function 0 P75 input 0 1 0 1 -- 0 P75 output 0 1 SCK3 output 0 1 1 -- 1 -- -- -- Setting prohibited SCK3 Setting output prohibited P74 The pin function is switched as shown below according to the setting of the bit P74DDR. P74DDR Pin function 0 P74 input 1 P74 output 213 9.6 9.6.1 Port A Overview Port A is a 4-bit I/O port. Port A pins also function as address bus outputs. The pin functions depend on the operating mode. Port A has a built-in MOS input pull-up function that can be controlled by software. Figure 9.5 shows the port A pin configuration. Port A pins PA3/A19 Port A PA2/ A18 PA1/ A17 PA0/ A16 Pin functions in modes 4, 5, and 6 PA3 (input/output) /A19 (output) PA2 (input/output) /A18 (output) PA1 (input/output) /A17 (output) PA0 (input/output)/A16 (output) Pin functions in mode 7 PA3 (input/output) PA2 (input/output) PA1 (input/output) PA0 (input/output) Figure 9.5 Port A Pin Functions 9.6.2 Register Configuration Table 9.9 shows the port A register configuration. Table 9.9 Name Port A data direction register Port A data register Port A register Port A MOS pull-up control register Port A open-drain control register Notes: *1 Lower 16 bits of the address. *2 Value of bits 3 to 0. 214 Port A Registers Abbreviation PADDR PADR PORTA PAPCR PAODR R/W W R/W R R/W R/W Initial Value*2 H'0 H'0 Undefined H'0 H'0 Address*1 H'FE39 H'FF09 H'FFB9 H'FE40 H'FE47 Port A Data Direction Register (PADDR) Bit : 7 -- Initial value : R/W : 6 -- 5 -- 4 -- 3 2 1 0 PA3DDR PA2DDR PA1DDR PA0DDR 0 W 0 W 0 W 0 W Undefined Undefined Undefined Undefined -- -- -- -- PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bits 7 to 4 are reserved; these bits cannot be modified. PADDR is initialized to H'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. (a) Modes 4, 5, and 6 If address output is enabled by the setting of bits AE3 to AE0 in PFCR, the corresponding port A pins are address outputs. When address output is disabled, setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin an input port. (b) Mode 7 Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin an input port. Port A Data Register (PADR) Bit : 7 -- Initial value : R/W : 6 -- 5 -- 4 -- 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 PA0DR 0 R/W Undefined Undefined Undefined Undefined -- -- -- -- PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA3 to PA0). Bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read. PADR is initialized to H'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. 215 Port A Register (PORTA) Bit : 7 -- Initial value : R/W : 6 -- 5 -- 4 -- 3 PA3 --* R 2 PA2 --* R 1 PA1 --* R 0 PA0 --* R Undefined Undefined Undefined Undefined -- -- -- -- Note: * Determined by the state of pins PA3 to PA0. PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port A pins (PA3 to PA0) must always be performed on PADR. Bits 7 to 4 are reserved; these bits will return an undefined value if read. If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A read is performed while PADDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTA contents are determined by the pin states, as PADDR and PADR are initialized. PORTA retains its previous state in software standby mode. Port A MOS Pull-Up Control Register (PAPCR) Bit : 7 -- Initial value : R/W : 6 -- 5 -- 4 -- 3 2 1 0 PA3PCR PA2PCR PA1PCR PA0PCR 0 R/W 0 R/W 0 R/W 0 R/W Undefined Undefined Undefined Undefined -- -- -- -- PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port A on a bit-by-bit basis. Bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read. PAPCR is valid for port input pins. When a PADDR bit is cleared to 0 (input port setting), setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PAPCR is initialized to H'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. 216 Port A Open-Drain Control Register (PAODR) Bit : 7 -- Initial value : R/W : 6 -- 5 -- 4 -- 3 2 1 0 PA3ODR PA2ODR PA1ODR PA0ODR 0 R/W 0 R/W 0 R/W 0 R/W Undefined Undefined Undefined Undefined -- -- -- -- PAODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port A pin (PA3 to PA0). Bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read. PAODR is valid for port output. Setting a PAODR bit to 1 makes the corresponding port A pin an NMOS open-drain output pin, while clearing the bit to 0 makes the pin a CMOS output pin. PAODR is initialized to H'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. 217 9.6.3 Pin Functions Port A pins also function as address output pins (A19 to A16). Port A pin functions are shown in table 9.10. Table 9.10 Port A Pin Functions Pin PA3/A19 Pin Functions and Selection Method The pin function is switched as shown below according to the combination of the operating mode, PFCR setting, and bit PA3DDR. Operating mode AE3 to AE0 in PFCR PA3DDR Pin function 11xx -- A19 output Modes 4 to 6 Other than 11xx 0 PA3 input 1 PA3 output* 0 PA3 input Mode 7 -- 1 PA3 output* x: Don't care Note: * NMOS open-drain output when PA3ODR = 1 in PAODR. PA2/A18 The pin function is switched as shown below according to the combination of the operating mode, PFCR setting, and bit PA2DDR. Operating mode AE3 to AE0 in PFCR PA2DDR Pin function 1011 or 11xx -- A18 output Modes 4 to 6 Other than (1011 or 11xx) 0 PA2 input 1 PA2 output* 0 PA2 input Mode 7 -- 1 PA2 output* x: Don't care Note: * NMOS open-drain output when PA2ODR = 1 in PAODR. PA1/A17 The pin function is switched as shown below according to the combination of the operating mode, PFCR setting, and bit PA1DDR. Operating mode AE3 to AE0 in PFCR PA1DDR Pin function 101x or 11xx -- A17 output Modes 4 to 6 Other than (101x or 11xx) 0 PA1 input 1 PA1 output* 0 PA1 input Mode 7 -- 1 PA1 output* x: Don't care Note: * NMOS open-drain output when PA1ODR = 1 in PAODR. 218 Pin PA0/A16 Pin Functions and Selection Method The pin function is switched as shown below according to the combination of the operating mode, PFCR setting, and bit PA0DDR. Operating mode AE3 to AE0 in PFCR PA1DDR Pin function Modes 4 to 6 Other than (0xxx or 1000) -- A16 output 0xxx or 1000 0 PA0 input 1 PA0 output* 0 PA0 input Mode 7 -- 1 PA0 output* x: Don't care Note: * NMOS open-drain output when PA0ODR = 1 in PAODR. 9.6.4 MOS Input Pull-Up Function Port A has a built-in MOS input pull-up function that can be controlled by software. MOS input pull-up can be specified as on or off for individual bits. With port input pins, when a PADDR bit is cleared to 0, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset and in hardware standby mode. The previous state is retained in software standby mode. Table 9.11 summarizes the MOS input pull-up states. Table 9.11 MOS Input Pull-Up States (Port A) Pins Address output, port output Port input Power-On Reset OFF OFF Hardware Standby Mode OFF OFF Software Standby Mode OFF ON/OFF In Other Operations OFF ON/OFF Legend: OFF: MOS input pull-up is always off. ON/OFF: On when PADDR = 0 and PAPCR = 1; otherwise off. 219 9.7 9.7.1 Port B Overview Port B is an 8-bit I/O port. Port B pins also function as address bus outputs. The pin functions depend on the operating mode. Port B has a built-in MOS input pull-up function that can be controlled by software. Figure 9.6 shows the port B pin configuration. Port B pins PB7/A15 PB6/A14 PB5/A13 Port B PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 Pin functions in modes 4, 5, and 6 PB7 (input/output) /A15 (output) PB6 (input/output) /A14 (output) PB5 (input/output) /A13 (output) PB4 (input/output) /A12 (output) PB3 (input/output) /A11 (output) PB2 (input/output) /A10 (output) PB1 (input/output) /A9 (output) PB0 (input/output) /A8 (output) Pin functions in mode 7 PB7 (input/output) PB6 (input/output) PB5 (input/output) PB4 (input/output) PB3 (input/output) PB2 (input/output) PB1 (input/output) PB0 (input/output) Figure 9.6 Port B Pin Functions 220 9.7.2 Register Configuration Table 9.12 shows the port B register configuration. Table 9.12 Port B Registers Name Port B data direction register Port B data register Port B register Port B MOS pull-up control register Note: * Lower 16 bits of the address. Abbreviation PBDDR PBDR PORTB PBPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* H'FE3A H'FF0A H'FFBA H'FE41 Port B Data Direction Register (PBDDR) Bit : 7 6 5 4 3 2 1 0 PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port B. PBDDR cannot be read; if it is, an undefined value will be read. PBDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 4, 5, and 6 If address output is enabled by the setting of bits AE3 to AE0 in PFCR, the corresponding port B pins are address outputs. When address output is disabled, setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin an input port. * Mode 7 Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin an input port. 221 Port B Data Register (PBDR) Bit : 7 PB7DR Initial value : R/W : 0 R/W 6 PB6DR 0 R/W 5 PB5DR 0 R/W 4 PB4DR 0 R/W 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W 0 PB0DR 0 R/W PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to PB0). PBDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. Port B Register (PORTB) Bit : 7 PB7 Initial value : R/W : --* R 6 PB6 --* R 5 PB5 --* R 4 PB4 --* R 3 PB3 --* R 2 PB2 --* R 1 PB1 --* R 0 PB0 --* R Note: * Determined by the state of pins PB7 to PB0. PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port B pins (PB7 to PB0) must always be performed on PBDR. If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B read is performed while PBDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTB contents are determined by the pin states, as PBDDR and PBDR are initialized. PORTB retains its previous state in software standby mode. Port B MOS Pull-Up Control Register (PBPCR) Bit : 7 6 5 4 3 2 1 0 PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port B on a bit-by-bit basis. 222 PBPCR is valid for port input pins. When a PBDDR bit is cleared to 0 (input port setting), setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PBPCR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. 9.7.3 Pin Functions Port B pins also function as address output pins (A15 to A8). Port B pin functions are shown in table 9.13. 223 Table 9.13 Port B Pin Functions Pin PB7/A15 Pin Functions and Selection Method The pin function is switched as shown below according to the combination of the operating mode, PFCR setting, and bit PB7DDR. Operating mode AE3 to AE0 in PFCR PB7DDR Pin function B'1xxx -- A15 output Modes 4 to 6 Other than B'1xxx 0 PB7 input 1 PB7 output 0 PB7 input Mode 7 -- 1 PB7 output x: Don't care PB6/A14 The pin function is switched as shown below according to the combination of the operating mode, PFCR setting, and bit PB6DDR. Operating mode AE3 to AE0 in PFCR PB6DDR Pin function B'0111 or B'1xxx -- A14 output Modes 4 to 6 Other than (B'0111 or B'1xxx) 0 PB6 input 1 PB6 output 0 PB6 input Mode 7 -- 1 PB6 output x: Don't care PB5/A13 The pin function is switched as shown below according to the combination of the operating mode, PFCR setting, and bit PB5DDR. Operating mode AE3 to AE0 in PFCR PB5DDR Pin function B'011x or B'1xxx -- A13 output Modes 4 to 6 Other than (B'011x or B'1xxx) 0 PB5 input 1 PB5 output 0 PB5 input Mode 7 -- 1 PB5 output x: Don't care PB4/A12 The pin function is switched as shown below according to the combination of the operating mode, PFCR setting, and bit PB4DDR. Operating mode AE3 to AE0 in PFCR PB4DDR Pin function B'0100 or B'00xx -- A12 output Modes 4 to 6 Other than (B'0100 or B'00xx) 0 PB4 input 1 PB4 output 0 PB4 input Mode 7 -- 1 PB4 output x: Don't care 224 Pin PB3/A11 Pin Functions and Selection Method The pin function is switched as shown below according to the combination of the operating mode, PFCR setting, and bit PB3DDR. Operating mode AE3 to AE0 in PFCR PB3DDR Pin function B'00xx -- A11 output Modes 4 to 6 Other than B'00xx 0 PB3 input 1 PB3 output 0 PB3 input Mode 7 -- 1 PB3 output x: Don't care PB2/A10 The pin function is switched as shown below according to the combination of the operating mode, PFCR setting, and bit PB2DDR. Operating mode AE3 to AE0 in PFCR PB2DDR Pin function B'0010 or B'000x -- A10 output Modes 4 to 6 Other than B'0010 or B'000x 0 PB2 input 1 PB2 output 0 PB2 input Mode 7 -- 1 PB2 output x: Don't care PB1/A9 The pin function is switched as shown below according to the combination of the operating mode, PFCR setting, and bit PB1DDR. Operating mode AE3 to AE0 in PFCR PB1DDR Pin function B'000x -- A9 output Modes 4 to 6 Other than B'000x 0 PB1 input 1 PB1 output 0 PB1 input Mode 7 -- 1 PB1 output x: Don't care PB0/A8 The pin function is switched as shown below according to the combination of the operating mode, PFCR setting, and bit PB0DDR. Operating mode AE3 to AE0 in PFCR PB0DDR Pin function B'0000 -- A8 output Modes 4 to 6 Other than B'0000 0 PB0 input 1 PB0 output 0 PB0 input Mode 7 -- 1 PB0 output 225 9.7.4 MOS Input Pull-Up Function Port B has a built-in MOS input pull-up function that can be controlled by software. MOS input pull-up can be specified as on or off for individual bits. With port input pins, when a PBDDR bit is cleared to 0, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset and in hardware standby mode. The previous state is retained in software standby mode. Table 9.14 summarizes the MOS input pull-up states. Table 9.14 MOS Input Pull-Up States (Port B) Pins Address output, port output Port input Power-On Reset OFF OFF Hardware Standby Mode OFF OFF Software Standby Mode OFF ON/OFF In Other Operations OFF ON/OFF Legend: OFF: MOS input pull-up is always off. ON/OFF: On when PBDDR = 0 and PBPCR = 1; otherwise off. 226 9.8 9.8.1 Port C Overview Port C is an 8-bit I/O port. Port C pins also function as address bus outputs. The pin functions depend on the operating mode. Port C has a built-in MOS input pull-up function that can be controlled by software. Figure 9.7 shows the port C pin configuration. Port C pins PC7/ A7 PC6/ A6 PC5/ A5 Port C PC4/ A4 PC3/ A3 PC2/ A2 PC1/ A1 PC0/ A0 Pin functions in mode 6 PC7 (input)/A7 (output) PC6 (input)/A6 (output) PC5 (input)/A5 (output) PC4 (input)/A4 (output) PC3 (input)/A3 (output) PC2 (input)/A2 (output) PC1 (input)/A1 (output) PC0 (input)/A0 (output) Pin functions in modes 4 and 5 A7 (output) A6 (output) A5 (output) A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Pin functions in mode 7 PC7 (input/output) PC6 (input/output) PC5 (input/output) PC4 (input/output) PC3 (input/output) PC2 (input/output) PC1 (input/output) PC0 (input/output) Figure 9.7 Port C Pin Functions 227 9.8.2 Register Configuration Table 9.15 shows the port C register configuration. Table 9.15 Port C Registers Name Port C data direction register Port C data register Port C register Port C MOS pull-up control register Note: * Lower 16 bits of the address. Abbreviation PCDDR PCDR PORTC PCPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* H'FE3B H'FF0B H'FFBB H'FE42 Port C Data Direction Register (PCDDR) Bit : 7 6 5 4 3 2 1 0 PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W PCDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port C. PCDDR cannot be read; if it is, an undefined value will be read. PCDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 4 and 5 Port C pins are address outputs regardless of the PCDDR settings. * Mode 6 Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while clearing the bit to 0 makes the pin an input port. * Mode 7 Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing the bit to 0 makes the pin an input port. 228 Port C Data Register (PCDR) Bit : 7 PC7DR Initial value : R/W : 0 R/W 6 PC6DR 0 R/W 5 PC5DR 0 R/W 4 PC4DR 0 R/W 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W 0 PC0DR 0 R/W PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to PC0). PCDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. Port C Register (PORTC) Bit : 7 PC7 Initial value : R/W : --* R 6 PC6 --* R 5 PC5 --* R 4 PC4 --* R 3 PC3 --* R 2 PC2 --* R 1 PC1 --* R 0 PC0 --* R Note: * Determined by the state of pins PC7 to PC0. PORTC is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port C pins (PC7 to PC0) must always be performed on PCDR. If a port C read is performed while PCDDR bits are set to 1, the PCDR values are read. If a port C read is performed while PCDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTC contents are determined by the pin states, as PCDDR and PCDR are initialized. PORTC retains its previous state in software standby mode. Port C MOS Pull-Up Control Register (PCPCR) Bit : 7 6 5 4 3 2 1 0 PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port C on a bit-by-bit basis. PCPCR is valid for port input (modes 6 and 7). 229 When a PCDDR bit is cleared to 0 (input port setting), setting the corresponding PCPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PCPCR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. 9.8.3 Pin Functions in Each Mode Modes 4 and 5 In modes 4 and 5, port C pins function as address outputs automatically. Port C pin functions in modes 4 and 5 are shown in figure 9.8. A7 (output) A6 (output) A5 (output) Port C A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Figure 9.8 Port C Pin Functions (Modes 4 and 5) 230 Mode 6 In mode 6, port C pins function as address outputs or input ports, and input or output can be specified bit by bit. Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while clearing the bit to 0 makes the pin an input port. Port C pin functions in mode 6 are shown in figure 9.9. When PCDDR = 1 A7 (output) A6 (output) A5 (output) Port C A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) When PCDDR = 0 PC7 (input) PC6 (input) PC5 (input) PC4 (input) PC3 (input) PC2 (input) PC1 (input) PC0 (input) Figure 9.9 Port C Pin Functions (Mode 6) Mode 7 In mode 7, port C functions as an I/O port, and input or output can be specified bit by bit. Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing the bit to 0 makes the pin an input port. Port C pin functions in mode 7 are shown in figure 9.10. PC7 (input/output) PC6 (input/output) PC5 (input/output) Port C PC4 (input/output) PC3 (input/output) PC2 (input/output) PC1 (input/output) PC0 (input/output) Figure 9.10 Port C Pin Functions (Mode 7) 231 9.8.4 MOS Input Pull-Up Function Port C has a built-in MOS input pull-up function that can be controlled by software. MOS input pull-up can be used in modes 6 and 7, and can be specified as on or off for individual bits. With the port input pin function (modes 6 and 7), when a PCDDR bit is cleared to 0, setting the corresponding PCPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset and in hardware standby mode. The previous state is retained in software standby mode. Table 9.16 summarizes the MOS input pull-up states. Table 9.16 MOS Input Pull-Up States (Port C) Pins Address output (modes 4 and 5), port output (modes 6 and 7) Port input (modes 6 and 7) Power-On Reset OFF OFF Hardware Standby Mode OFF OFF Software Standby Mode OFF ON/OFF In Other Operations OFF ON/OFF Legend: OFF: MOS input pull-up is always off. ON/OFF: On when PCDDR = 0 and PCPCR = 1; otherwise off. 232 9.9 9.9.1 Port D Overview Port D is an 8-bit I/O port. Port D pins also function as data bus input/output pins. The pin functions depend on the operating mode. Port D has a built-in MOS input pull-up function that can be controlled by software. Figure 9.11 shows the port D pin configuration. Port D pin PD7/ D15 PD6/ D14 PD5/ D13 Port D PD4/ D12 PD3/ D11 PD2/ D10 PD1/ D9 PD0/ D8 Pin functions in modes 4 to 6 D15 (input/output) D14 (input/output) D13 (input/output) D12 (input/output) D11 (input/output) D10 (input/output) D9 (input/output) D8 (input/output) Pin functions in mode 7 PD7 (input/output) PD6 (input/output) PD5 (input/output) PD4 (input/output) PD3 (input/output) PD2 (input/output) PD1 (input/output) PD0 (input/output) Figure 9.11 Port D Pin Functions 233 9.9.2 Register Configuration Table 9.17 shows the port D register configuration. Table 9.17 Port D Registers Name Port D data direction register Port D data register Port D register Port D MOS pull-up control register Note: * Lower 16 bits of the address. Abbreviation PDDDR PDDR PORTD PDPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* H'FE3C H'FF0C H'FFBC H'FE43 Port D Data Direction Register (PDDDR) Bit : 7 6 5 4 3 2 1 0 PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port D. PDDDR cannot be read; if it is, an undefined value will be read. PDDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. * Modes 4 to 6 The input/output direction settings in PDDDR are ignored, and port D pins automatically function as data input/output pins. * Mode 7 Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port. 234 Port D Data Register (PDDR) Bit : 7 PD7DR Initial value : R/W : 0 R/W 6 PD6DR 0 R/W 5 PD5DR 0 R/W 4 PD4DR 0 R/W 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W 0 PD0DR 0 R/W PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to PD0). PDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. Port D Register (PORTD) Bit : 7 PD7 Initial value : R/W : --* R 6 PD6 --* R 5 PD5 --* R 4 PD4 --* R 3 PD3 --* R 2 PD2 --* R 1 PD1 --* R 0 PD0 --* R Note: * Determined by the state of pins PD7 to PD0. PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port D pins (PD7 to PD0) must always be performed on PDDR. If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D read is performed while PDDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTD contents are determined by the pin states, as PDDDR and PDDR are initialized. PORTD retains its previous state in software standby mode. Port D MOS Pull-Up Control Register (PDPCR) Bit : 7 6 5 4 3 2 1 0 PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port D on a bit-by-bit basis. 235 PDPCR is valid for port input pins (mode 7). When a PDDDR bit is cleared to 0 (input port setting), setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PDPCR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. 9.9.3 Pin Functions in Each Mode Modes 4 to 6 In modes 4 to 6, port D pins function as data input/output pins automatically. Port D pin functions in modes 4 to 6 are shown in figure 9.12. D15 (input/output) D14 (input/output) D13 (input/output) Port D D12 (input/output) D11 (input/output) D10 (input/output) D9 (input/output) D8 (input/output) Figure 9.12 Port D Pin Functions (Modes 4 to 6) Mode 7 In mode 7, port D functions as an I/O port, and input or output can be specified bit by bit. Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port. Port D pin functions in mode 7 are shown in figure 9.13. 236 PD7 (input/output) PD6 (input/output) PD5 (input/output) Port D PD4 (input/output) PD3 (input/output) PD2 (input/output) PD1 (input/output) PD0 (input/output) Figure 9.13 Port D Pin Functions (Mode 7) 9.9.4 MOS Input Pull-Up Function Port D has a built-in MOS input pull-up function that can be controlled by software. MOS input pull-up can be used in mode 7, and can be specified as on or off for individual bits. With the port input pin function (mode 7), when a PDDDR bit is cleared to 0, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset and in hardware standby mode. The previous state is retained in software standby mode. Table 9.18 summarizes the MOS input pull-up states. Table 9.18 MOS Input Pull-Up States (Port D) Pins Data input/output (modes 4 to 6), port output (mode 7) Port input (mode 7) Power-On Reset OFF OFF Hardware Standby Mode OFF OFF Software Standby Mode OFF ON/OFF In Other Operations OFF ON/OFF Legend: OFF: MOS input pull-up is always off. ON/OFF: On when PDDDR = 0 and PDPCR = 1; otherwise off. 237 9.10 9.10.1 Port E Overview Port E is an 8-bit I/O port. Port E pins also function as data bus input/output pins. The pin functions depend on the operating mode and on whether 8-bit or 16-bit bus mode is used. Port E has a built-in MOS input pull-up function that can be controlled by software. Figure 9.14 shows the port E pin configuration. Port E pins PE7/ D7 PE6/ D6 PE5/ D5 Port E PE4/ D4 PE3/ D3 PE2/ D2 PE1/ D1 PE0/ D0 Pin functions in modes 4 to 6 PE7 (input/output)/D7 (input/output) PE6 (input/output)/D6 (input/output) PE5 (input/output)/D5 (input/output) PE4 (input/output)/D4 (input/output) PE3 (input/output)/D3 (input/output) PE2 (input/output)/D2 (input/output) PE1 (input/output)/D1 (input/output) PE0 (input/output)/D0 (input/output) Pin functions in mode 7 PE7 (input/output) PE6 (input/output) PE5 (input/output) PE4 (input/output) PE3 (input/output) PE2 (input/output) PE1 (input/output) PE0 (input/output) Figure 9.14 Port E Pin Functions 238 9.10.2 Register Configuration Table 9.19 shows the port E register configuration. Table 9.19 Port E Registers Name Port E data direction register Port E data register Port E register Port E MOS pull-up control register Note: * Lower 16 bits of the address. Abbreviation PEDDR PEDR PORTE PEPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* H'FE3D H'FF0D H'FFBD H'FE44 Port E Data Direction Register (PEDDR) Bit : 7 6 5 4 3 2 1 0 PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port E. PEDDR cannot be read; if it is, an undefined value will be read. PEDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. * Modes 4 to 6 When 8-bit bus mode is selected, port E functions as an I/O port. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. When 16-bit bus mode is selected, the input/output direction settings in PEDDR are ignored, and port E pins automatically function as data input/output pins. For details of the 8-bit and 16-bit bus modes, see section 7, Bus Controller. * Mode 7 Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. 239 Port E Data Register (PEDR) Bit : 7 PE7DR Initial value : R/W : 0 R/W 6 PE6DR 0 R/W 5 PE5DR 0 R/W 4 PE4DR 0 R/W 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W 0 PE0DR 0 R/W PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0). PEDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. Port E Register (PORTE) Bit : 7 PE7 Initial value : R/W : --* R 6 PE6 --* R 5 PE5 --* R 4 PE4 --* R 3 PE3 --* R 2 PE2 --* R 1 PE1 --* R 0 PE0 --* R Note: * Determined by the state of pins PE7 to PE0. PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port E pins (PE7 to PE0) must always be performed on PEDR. If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E read is performed while PEDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTE contents are determined by the pin states, as PEDDR and PEDR are initialized. PORTE retains its previous state in software standby mode. Port E MOS Pull-Up Control Register (PEPCR) Bit : 7 6 5 4 3 2 1 0 PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port E on a bit-by-bit basis. PEPCR is valid for port input pins (modes 4 to 6 in 8-bit bus mode, or mode 7). 240 When a PEDDR bit is cleared to 0 (input port setting), setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PEPCR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. 9.10.3 Pin Functions in Each Mode Modes 4 to 6 In modes 4 to 6, if 8-bit access space is designated and 8-bit bus mode is selected, port E functions as an I/O port. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. When 16-bit bus mode is selected, the input/output direction settings in PEDDR are ignored, and port E pins function as data input/output pins. Port E pin functions in modes 4 to 6 are shown in figure 9.15. 8-bit bus mode PE7 (input/output) PE6 (input/output) PE5 (input/output) Port E PE4 (input/output) PE3 (input/output) PE2 (input/output) PE1 (input/output) PE0 (input/output) 16-bit bus mode D7 (input/output) D6 (input/output) D5 (input/output) D4 (input/output) D3 (input/output) D2 (input/output) D1 (input/output) D0 (input/output) Figure 9.15 Port E Pin Functions (Modes 4 to 6) 241 Mode 7 In mode 7, port E functions as an I/O port, and input or output can be specified bit by bit. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. Port E pin functions in mode 7 are shown in figure 9.16. PE7 (input/output) PE6 (input/output) PE5 (input/output) Port E PE4 (input/output) PE3 (input/output) PE2 (input/output) PE1 (input/output) PE0 (input/output) Figure 9.16 Port E Pin Functions (Mode 7) 9.10.4 MOS Input Pull-Up Function Port E has a built-in MOS input pull-up function that can be controlled by software. MOS input pull-up can be used in modes 4 to 6 in 8-bit bus mode, or in mode 7, and can be specified as on or off for individual bits. With the port input pin function (modes 4 to 6 in 8-bit bus mode, or mode 7), when a PEDDR bit is cleared to 0, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset and in hardware standby mode. The previous state is retained in software standby mode. Table 9.20 summarizes the MOS input pull-up states. 242 Table 9.20 MOS Input Pull-Up States (Port E) Pins Data input/output (modes 4 to 6 with 16-bit bus), port output (modes 4 to 6 with 8-bit bus, mode 7) Port input (modes 4 to 6 with 8-bit bus, mode 7) Power-On Reset OFF Hardware Software In Other Standby Mode Standby Mode Operations OFF OFF OFF OFF OFF ON/OFF ON/OFF Legend: OFF: MOS input pull-up is always off. ON/OFF: On when PEDDR = 0 and PEPCR = 1; otherwise off. 9.11 9.11.1 Port F Overview Port F is an 8-bit I/O port. Port F pins also function as external interrupt input pins (IRQ2 and IRQ3), the BUZZ output pin, the A/D trigger input pin (ADTRG), bus control signal I/O pins (AS, RD, HWR, LWR, WAIT, BREQ, and BACK), and the system clock (o) output pin. The interrupt input pins (IRQ2 and IRQ3) are Schmitt-triggered inputs. Figure 9.17 shows the port F pin configuration. 243 Port F pins PF7/o PF6/AS PF5/RD Port F PF4/HWR PF3/LWR/ ADTRG/ IRQ3 PF2/WAIT PF1/BACK/ BUZZ PF0/BREQ/ I RQ2 Pin functions in mode 7 PF7 (input)/o (output) PF6 (input/output) PF5 (input/output) PF4 (input/output) PF3 (input/output)/ ADTRG (input)/ IRQ3 (input) PF2 (input/output) PF1 (input/output)/ B U Z Z (output) PF0 (input/output)/ IRQ2 (input) Pin functions in modes 4 to 6 PF7 (input)/o (output) AS (output) RD (output) HWR (output) PF3 (input/output)/ LWR (output)/ ADTRG (input)/IRQ3 (input) PF2 (input/output)/WAIT (input) PF1 (input/output)/BACK (output)/ B U Z Z (output) PF0 (input/output)/BREQ (input)/ IRQ2 (input) Figure 9.17 Port F Pin Functions 9.11.2 Register Configuration Table 9.21 shows the port F register configuration. Table 9.21 Port F Registers Name Port F data direction register Port F data register Port F register Abbreviation PFDDR PFDR PORTF R/W W R/W R Initial Value H'80/H'00* 2 H'00 Undefined Address* 1 H'FE3E H'FF0E H'FFBE Notes: *1 Lower 16 bits of the address. *2 Initial value depends on the mode. PFDDR is initialized to H'80 in modes 4 to 6, and to H'00 in mode 7. 244 Port F Data Direction Register (PFDDR) Bit : 7 6 5 4 3 2 1 0 PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Modes 4 to 6 Initial value : R/W Mode 7 Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W : 1 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port F. PFDDR cannot be read; if it is, an undefined value will be read. PFDDR is initialized to H'80 (modes 4 to 6) or H'00 (mode 7) by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain their output state or become highimpedance when a transition is made to software standby mode. * Modes 4 to 6 Pin PF7 functions as the o output pin when the corresponding PFDDR bit is set to 1, and as an input port when the bit is cleared to 0. The input/output direction specification in PFDDR is ignored for pins PF6 to PF4, which are automatically designated as bus control outputs (AS, RD, and HWR). When 8-bit bus mode selected, pin PF3 is made bus control output (LWR). When 16-bit bus mode selected, setting a PF3DDR bit to 1 makes the pin an output port, while clearing the bit to 0 makes the pin an input port. Pins PF2 to PF0 are made bus control input/output pins (WAIT, BACK, and BREQ) by bus controller settings. Otherwise, setting a PFDDR bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. * Mode 7 Setting a PFDDR bit to 1 makes the corresponding port F pin PF6 to PF0 an output port, or in the case of pin PF7, the o output pin. Clearing the bit to 0 makes the pin an input port. 245 Port F Data Register (PFDR) Bit : 7 PF7DR Initial value : R/W : 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4 PF4DR 0 R/W 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W 0 PF0DR 0 R/W PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0). PFDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. Port F Register (PORTF) Bit : 7 PF7 Initial value : R/W : --* R 6 PF6 --* R 5 PF5 --* R 4 PF4 --* R 3 PF3 --* R 2 PF2 --* R 1 PF1 --* R 0 PF0 --* R Note: * Determined by the state of pins PF7 to PF0. PORTF is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port F pins (PF7 to PF0) must always be performed on PFDR. If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F read is performed while PFDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTF contents are determined by the pin states, as PFDDR and PFDR are initialized. PORTF retains its previous state in software standby mode. 9.11.3 Pin Functions Port F pins also function as external interrupt input pins (IRQ2 and IRQ3), the BUZZ output pin, the A/D trigger input pin (ADTRG), bus control signal I/O pins (AS, RD, HWR, LWR, WAIT, BREQ, and BACK), and the system clock (o) output pin. The pin functions differ between modes 4 to 6 and mode 7. Port F pin functions are shown in table 9.22. 246 Table 9.22 Port F Pin Functions Pin PF7/o Pin Functions and Selection Method The pin function is switched as shown below according to bit PF7DDR. PF7DDR Pin function PF6/AS 0 PF7 input 1 o output The pin function is switched as shown below according to the operating mode and bit PF6DDR. Operating mode PF6DDR Pin function Modes 4 to 6 -- AS output 0 PF6 input Mode 7 1 PF6 output PF5/RD The pin function is switched as shown below according to the operating mode and bit PF5DDR. Operating mode PF5DDR Pin function Modes 4 to 6 -- RD output 0 PF5 input Mode 7 1 PF5 output PF4/HWR The pin function is switched as shown below according to the operating mode and bit PF4DDR. Operating mode PF4DDR Pin function Modes 4 to 6 -- HWR output 0 PF4 input Mode 7 1 PF4 output PF3/LWR/ The pin function is switched as shown below according to the operating mode, the bus ADTRG/ mode, A/D converter bits TRGS1 and TRGS0, and bit PF3DDR. IRQ3 Operating mode Modes 4 to 6 Mode 7 Bus mode PF3DDR Pin function 16-bit bus mode -- LWR output 8-bit bus mode 0 PF3 input 1 PF3 output 0 PF3 input 1 -- 1 PF3 output ADTRG input* IRQ3 input* 2 Notes: *1 ADTRG input when TRGS0 = TRGS1 = 1. *2 When used as an external interrupt input pin, do not use as an I/O pin for another function. 247 Pin Pin Functions and Selection Method PF2/WAIT The pin function is switched as shown below according to the operating mode, bit WAITE in BCRL, and bit PF2DDR. Operating mode WAITE PF2DDR Pin function 0 PF2 input Modes 4 to 6 0 1 PF2 output 1 -- WAIT input 0 PF2 input Mode 7 -- 1 PF2 output PF1/BACK/ The pin function is switched as shown below according to the operating mode, bit BUZZ BRLE in BCRL, bit BUZZE in PFCR, and bit PF1DDR. Operating mode BRLE BUZZE PF1DDR Pin function 0 PF1 input 0 1 PF1 output Modes 4 to 6 0 1 -- BUZZ output 1 -- -- BACK output 0 PF1 input 0 1 PF1 output Mode 7 -- 1 -- BUZZ output PF0/BREQ/ The pin function is switched as shown below according to the operating mode, bit IRQ2 BRLE in BCRL, and bit PF0DDR. Operating mode BRLE PF0DDR Pin function 0 PF0 input Modes 4 to 6 0 1 1 -- 0 PF0 input Mode 7 -- 1 PF0 output PF0 output BREQ input IRQ2 input* Note: * When used as an external interrupt input pin, do not use as an I/O pin for another function. 9.12 Port G* Note: * PG0/IRQ6, only is a internal input port. 9.12.1 Overview Port G consists of a 4-bit I/O port and on-chip 1-bit input port that is a dedicated port for the FLEXTM decoder II interface. Port G pins also function as external interrupt input pins (IRQ6 (dedicated to the interrupt from the FLEXTM decoder II) and IRQ7) and bus control signal output pins (CS0 to CS3). The interrupt input pin (IRQ7) is Schmitt-triggered input. 248 Figure 9.18 shows the port G pin configuration. Port G pins PG4/ CS0 Port G PG3/ CS1 PG2/ CS2 PG1/ CS3/ IRQ7 PG0/ IRQ6 READY FLEXTM decoder II Pin functions in modes 4 to 6 PG4 (input)/CS0 (output) PG3 (input)/CS1 (output) PG2 (input)/CS2 (output) PG1 (input)/CS3 (output)/IRQ7 (input) PG0 (input)/IRQ6 (input) Note: Pin functions in mode 7 PG4 (input/output) PG3 (input/output) PG2 (input/output) PG1 (input/output)/ IRQ7 (input) PG0 (input/output)/ IRQ6 (input) : Connected inside the chip (PG0/IRQ6 only) Figure 9.18 Port G Pin Functions 9.12.2 Register Configuration Table 9.23 shows the port G register configuration. Table 9.23 Port G Registers Name Port G data direction register Port G data register Port G register Abbreviation PGDDR PGDR PORTG R/W W R/W R Initial Value* 2 Address* 1 H'10/H'00* 3 H'00 Undefined H'FE3F H'FF0F H'FFBF Notes: *1 Lower 16 bits of the address. *2 Value of bits 4 to 0. *3 Initial value depends on the mode. PGDDR is initialized to H'10 in modes 4 and 5, and to H'00 in modes 6 and 7. 249 Port G Data Direction Register (PGDDR) Bit : 7 -- Modes 4 and 5 Initial value : R/W : Undefined Undefined Undefined 6 -- 5 -- 4 3 2 1 0 -- PG4DDR PG3DDR PG2DDR PG1DDR 1 W 0 W 0 W 0 W Undefined -- -- -- W Modes 6 and 7 Initial value : R/W : Undefined Undefined Undefined 0 W 0 W 0 W 0 W Undefined -- -- -- W PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port G. PGDDR cannot be read. Also, bits 7 to 5 are reserved, and cannot be modified. Bit 0 is reserved, and should always be written with 0. Bit PG4DDR is initialized to 1 (modes 4 and 5) or 0 (modes 6 and 7) by a power-on reset and in hardware standby mode. PGDDR retains its previous state in software standby mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 4 to 6 Pins PG4 to PG1 function as bus control signal output pins (CS0 to CS3) when the corresponding PGDDR bits are set to 1, and as input ports when the bits are cleared to 0. Pin PG0 functions as an output port when the corresponding PGDDR bit is set to 1, and as an input port when the bit is cleared to 0. * Mode 7 Setting a PGDDR bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Port G Data Register (PGDR) Bit : 7 -- Initial value : R/W : 6 -- 5 -- 4 PG4DR 0 R/W 3 PG3DR 0 R/W 2 PG2DR 0 R/W 1 PG1DR 0 R/W 0 -- Undefined Undefined Undefined Undefined -- -- -- R/W PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG4 to PG1). Bits 7 to 5 are reserved; these bits cannot be modified and will return an undefined value if read. 250 Bit 0 is reserved: this bit should always be written with 0 and will return an undefined value if read. PGDR is initialized to H'00 (bits 4 to 0) by a power-on reset and in hardware standby mode. It retains its previous state in software standby mode. Port G Register (PORTG) Bit : 7 -- Initial value : R/W : 6 -- 5 -- 4 PG4 --* R 3 PG3 --* R 2 PG2 --* R 1 PG1 --* R 0 PG0 --* R Undefined Undefined Undefined -- -- -- Note: * Determined by the state of pins PG4 to PG1, and of READY of FLEXTM decoder II. PORTG is an 8-bit read-only register that shows the pin states and READY of FLEXTM decoder II. It cannot be written to. Writing of output data for the port G pins (PG4 to PG1) must always be performed on PGDR. Bits 7 to 5 are reserved; these bits will return an undefined value if read. If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G read is performed while PGDDR bits are cleared to 0, the pin states are read. Note that the READY state of the FLEXTM decoder II is always read for PG0. After a power-on reset and in hardware standby mode, PORTG contents are determined by the pin states, as PGDDR and PGDR are initialized. PORTG retains its previous state in software standby mode. 9.12.3 Pin Functions Port G pins also function as external interrupt input pins (IRQ6 dedicated to the interrupt from the FLEXTM decoder II and IRQ7) and bus control signal output pins (CS0 to CS3). The pin functions differ between modes 4 to 6 and mode 7. Port G pin functions are shown in table 9.24. 251 Table 9.24 Port G Pin Functions Pin PG4/CS0 Pin Functions and Selection Method The pin function is switched as shown below according to the operating mode and bit PG4DDR. Operating mode PG4DDR Pin function 0 PG4 input Modes 4 to 6 1 CS0 output 0 PG4 input Mode 7 1 PG4 output PG3/CS1 The pin function is switched as shown below according to the operating mode and bit PG3DDR. Operating mode PG3DDR Pin function 0 PG3 input Modes 4 to 6 1 CS1 output 0 PG3 input Mode 7 1 PG3 output PG2/CS2 The pin function is switched as shown below according to the operating mode and bit PG2DDR. Operating mode PG2DDR Pin function 0 PG2 input Modes 4 to 6 1 CS2 output 0 PG2 input Mode 7 1 PG2 output PG1/CS3/ The pin function is switched as shown below according to the operating mode and bit IRQ7 PG1DDR. Operating mode PG1DDR Pin function 0 PG1 input Modes 4 to 6 1 CS3 output 0 PG1 input Mode 7 1 PG1 output IRQ7 input* Note: * When used as an external interrupt input pin, do not use as an I/O pin for another function. PG0/IRQ6 PG0 is an input-only pin and can be used as the PG0 or IRQ6 input pin. When used as an external interrupt pin (IRQ6), do not use it as an input pin for another function. (on-chip dedicated I/O port for the FLEXTM decoder II interface) 252 Section 10 16-Bit Timer Pulse Unit (TPU) 10.1 Overview The LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises three 16-bit timer channels. 10.1.1 Features * Maximum 6-pulse input/output capability A total of 8 timer general registers (TGRs) are provided (four for channel 0 and two each for channels 1 and 2), each of which can be set independently as an output compare/input capture register TGRC and TGRD for channel 0 can also be used as buffer registers * Selection of one of six clocks as the counter input for channel 0, and one of seven clocks for channels 1 and 2 * The following operations can be set for each channel: Waveform output at compare match: Selection of 0, 1, or toggle output Input capture function: Selection of rising edge, falling edge, or both edge detection Counter clear operation: Counter clearing possible by compare match or input capture Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture possible Register simultaneous input/output possible by counter synchronous operation PWM mode: Any PWM output duty can be set Maximum of 6-phase PWM output possible by combination with synchronous operation * Buffer operation settable for channel 0 Input capture register double-buffering possible Automatic rewriting of output compare register possible * Phase counting mode settable for channel 1 Two-phase encoder pulse up/down-count possible * Fast access via internal 16-bit bus Fast access is possible via a 16-bit bus interface 253 * 13 interrupt sources For channel 0, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently For channels 1 and 2, one compare match/input capture dual-function interrupt one compare match interrupt, one overflow interrupt, and one underflow interrupt can be requested independently * Automatic transfer of register data Block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer controller (DTC) activation * A/D converter conversion start trigger can be generated Channel 0 to 2 compare match A/input capture A signals can be used as A/D converter conversion start trigger * Module stop mode can be set As the initial setting, TPU operation is halted. Register access is enabled by exiting module stop mode. Table 10.1 lists the functions of the TPU. 254 Table 10.1 TPU Functions Item Count clock Channel 0 o/1 o/4 o/16 o/64 TCLKA TCLKB TGR0A TGR0B TGR0C TGR0D TIOCA0 TIOCB0 TIOCC0 TIOCD0 Channel 1 o/1 o/4 o/16 o/64 o/256 TCLKA TCLKB TGR1A TGR1B -- TIOCA1 Channel 2 o/1 o/4 o/16 o/64 o/1024 TCLKA TCLKB TGR2A TGR2B -- TIOCA2 General registers General registers/ buffer registers I/O pins Counter clear function TGR compare match TGR compare match TGR compare match or input capture or TGR1A input or TGR2A input capture capture Compare match output 0 output 1 output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation DTC activation -- -- -- -- TGR compare match TGR compare match TGR compare match or input capture or TGR1A input or TGR2A input capture capture TGR0A compare match or input capture TGR1A compare match or input capture TGR2A compare match or input capture A/D converter trigger Legend : Possible -- : Not possible 255 Item Interrupt sources Channel 0 5 sources * Compare match or input capture 0A * Compare match or input capture 0B * Compare match or input capture 0C * Compare match or input capture 0D * Overflow Channel 1 4 sources * Compare match or input capture 1A * Overflow * Underflow Channel 2 4 sources * Compare match or input capture 2A * Overflow * Underflow * Compare match 1B * Compare match 1B 256 10.1.2 Block Diagram Figure 10.1 shows a block diagram of the TPU. Clock input Internal clock: o/1 o/4 o/16 o/64 o/256 o/1024 External clock: TCLKA TCLKB TSTR TSYR Bus interface Common Control logic Internal data bus A/D conversion start request signal TMDR Channel 2 TSR TGRA Module data bus TIOR TIER TCR TGRB TCNT Control logic for channels 0 to 2 TIOR TIORH TIORL TMDR Channel 0 TSR TIER Input/output pins TIOCA0 Channel 0: TIOCB0 TIOCC0 TIOCD0 TIOCA1 Channel 1: TIOCA2 Channel 2: Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U TMDR Channel 1 TSR TGRA TCR TGRB TGRC TGRD TGRB TCNT TCNT Legend TSTR: Timer start register TSYR: Timer synchro register TCR: Timer control register TMDR: Timer mode register TIOR (H, L): TIER: TSR: TGR (A, B, C, D): TCNT: TIER TCR Timer I/O control registers (H, L) Timer interrupt enable register Timer status register Timer general registers (A, B, C, D) Timer counter Figure 10.1 Block Diagram of TPU TGRA 257 10.1.3 Pin Configuration Table 10.2 summarizes the TPU pins. Table 10.2 TPU Pins Channel All Name Clock input A Symbol TCLKA I/O Input Function External clock A input pin (Channel 1 phase counting mode A phase input) External clock B input pin (Channel 1 phase counting mode B phase input) TGR0A input capture input/output compare output/PWM output pin TGR0B input capture input/output compare output/PWM output pin TGR0C input capture input/output compare output/PWM output pin TGR0D input capture input/output compare output/PWM output pin TGR1A input capture input/output compare output/PWM output pin TGR2A input capture input/output compare output/PWM output pin Clock input B TCLKB Input 0 Input capture/out TIOCA0 compare match A0 Input capture/out TIOCB0 compare match B0 Input capture/out TIOCC0 compare match C0 Input capture/out TIOCD0 compare match D0 I/O I/O I/O I/O I/O I/O 1 2 Input capture/out TIOCA1 compare match A1 Input capture/out TIOCA2 compare match A2 258 10.1.4 Register Configuration Table 10.3 summarizes the TPU registers. Table 10.3 TPU Registers Channel Name 0 Timer control register 0 Timer mode register 0 Timer I/O control register 0H Timer I/O control register 0L Abbreviation TCR0 TMDR0 TIOR0H TIOR0L R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W 2 2 Initial Value H'00 H'C0 H'00 H'00 H'40 H'C0 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'00 H'C0 H'00 H'40 Address* 1 H'FF10 H'FF11 H'FF12 H'FF13 H'FF14 H'FF15 H'FF16 H'FF18 H'FF1A H'FF1C H'FF1E H'FF20 H'FF21 H'FF22 H'FF24 H'FF25 H'FF26 H'FF28 H'FF2A H'FF30 H'FF31 H'FF32 H'FF34 H'FF35 H'FF36 H'FF38 H'FF3A Timer interrupt enable register 0 TIER0 Timer status register 0 Timer counter 0 Timer general register 0A Timer general register 0B Timer general register 0C Timer general register 0D 1 Timer control register 1 Timer mode register 1 Timer I/O control register 1 TSR0 TCNT0 TGR0A TGR0B TGR0C TGR0D TCR1 TMDR1 TIOR1 Timer interrupt enable register 1 TIER1 Timer status register 1 Timer counter 1 Timer general register 1A Timer general register 1B 2 Timer control register 2 Timer mode register 2 Timer I/O control register 2 TSR1 TCNT1 TGR1A TGR1B TCR2 TMDR2 TIOR2 R/(W) * H'C0 R/W R/W R/W R/W R/W R/W R/W 2 H'0000 H'FFFF H'FFFF H'00 H'C0 H'00 H'40 Timer interrupt enable register 2 TIER2 Timer status register 2 Timer counter 2 Timer general register 2A Timer general register 2B TSR2 TCNT2 TGR2A TGR2B R/(W) * H'C0 R/W R/W R/W H'0000 H'FFFF H'FFFF 259 Channel Name All Timer start register Timer synchro register Module stop control register A Abbreviation TSTR TSYR MSTPCRA R/W R/W R/W R/W Initial Value H'00 H'00 H'3F Address* 1 H'FEB0 H'FEB1 H'FDE8 Notes: *1 Lower 16 bits of the address. *2 Can only be written with 0 for flag clearing. 10.2 10.2.1 Register Descriptions Timer Control Register (TCR) Channel 0: TCR0 Bit : 7 CCLR2 Initial value : R/W : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W CKEG1 CKEG0 Channel 1: TCR1 Channel 2: TCR2 Bit : 7 -- Initial value : R/W : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W CKEG1 CKEG0 The TCR registers are 8-bit registers that control the TCNT channels. The TPU has three TCR registers, one for each of channels 0 to 2. The TCR registers are initialized to H'00 by a reset, and in hardware standby mode. 260 Bits 7 to 5--Counter Clear 2 to 0 (CCLR2 to CCLR0): These bits select the TCNT counter clearing source. Bit 7 Channel 0 CCLR2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled (Initial value) TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation* 1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture* 2 TCNT cleared by TGRD compare match/input capture* 2 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation* 1 1 0 0 1 1 0 1 Bit 7 Channel 1, 2 3 Bit 6 Bit 5 CCLR0 0 1 Description TCNT clearing disabled (Initial value) Reserved* CCLR1 0 0 TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation* 1 1 0 1 Notes: *1 Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. *2 When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. *3 Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified. 261 Bits 4 and 3--Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. o/4 both edges = o/2 rising edge). If phase counting mode is used on channel 1, this setting is ignored and the phase counting mode setting has priority. Bit 4 CKEG1 0 Bit 3 CKEG0 0 1 1 -- Description Count at rising edge Count at falling edge Count at both edges (Initial value) Note: Internal clock edge selection is valid when the input clock is o/4 or slower. This setting is ignored if the input clock is o/1, or when overflow/underflow of another channel is selected. Bits 2 to 0--Time Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT counter clock. The clock source can be selected independently for each channel. Table 10.4 shows the clock sources that can be set for each channel. Table 10.4 TPU Clock Sources Internal Clock Channel 0 1 2 o/1 o/4 o/16 o/64 o/256 o/1024 External Clock TCLKA TCLKB Overflow/Underflow on Another Channel Legend : Setting Blank : No setting 262 Bit 2 Channel 0 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 Description Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Setting disabled Setting disabled (Initial value) 1 0 1 1 0 0 1 1 0 1 Bit 2 Channel 1 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 Description Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on o/256 Setting disabled (Initial value) 1 0 1 1 0 0 1 1 0 1 Note: This setting is ignored when channel 1 is in phase counting mode. Bit 2 Channel 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Setting disabled Internal clock: counts on o/1024 (Initial value) 263 10.2.2 Timer Mode Register (TMDR) Channel 0: TMDR0 Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 BFB 0 R/W 4 BFA 0 R/W 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W Channel 1: TMDR1 Channel 2: TMDR2 Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. The TPU has three TMDR registers, one for each channel. The TMDR registers are initialized to H'C0 by a reset, and in hardware standby mode. Bits 7 and 6--Reserved: Read-only bits, always read as 1. Bit 5--Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 BFB 0 1 Description TGRB operates normally TGRB and TGRD used together for buffer operation (Initial value) 264 Bit 4--Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. Bit 4 BFA 0 1 Description TGRA operates normally TGRA and TGRC used together for buffer operation (Initial value) Bits 3 to 0--Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode. Bit 3 MD3* 1 0 Bit 2 MD2* 2 0 Bit 1 MD1 0 Bit 0 MD0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Setting disabled (Initial value) *: Don't care Notes: *1 MD3 is a reserved bit. In a write, it should always be written with 0. *2 Phase counting mode cannot be set for channels 0 and 2. In this case, 0 should always be written to MD2. 265 10.2.3 Timer I/O Control Register (TIOR) Channel 0: TIOR0H Channel 1: TIOR1 Channel 2: TIOR2 Bit : 7 IOB3 Initial value : R/W : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W Channel 0: TIOR0L Bit : 7 IOD3 Initial value : R/W : 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. The TIOR registers are 8-bit registers that control the TGR registers. The TPU has four TIOR registers, two for channel 0, and one each for channels 1 and 2. The TIOR registers are initialized to H'00 by a reset, and in hardware standby mode. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. 266 Bits 7 to 4-- I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0): Bits IOB3 to IOB0 specify the function of TGRB. Bits IOD3 to IOD0 specify the function of TGRD. Bit 7 Bit 6 Bit 5 Bit 4 Channel 0 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0B is Capture input source is input TIOCB0 pin capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR0B is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT1 source is channel count- up/count-down* 1 1/count clock *: Don't care Note: *1 When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and o/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. 267 Bit 7 Bit 6 Bit 5 Bit 4 Channel 0 IOD3 IOD2 IOD1 IOD0 Description 0 0 0 0 1 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 * * * TGR0D is Capture input source is input TIOCD0 pin capture register* 2 Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR0D is Output disabled output Initial output is 0 compare output 2 register* (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT1 source is channel count-up/count-down* 1 1/count clock *: Don't care Notes: *1 When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and o/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. *2 When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 268 Bit 7 Bit 6 Bit 5 Bit 4 Channel 1 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 * * * -- Setting disabled *: Don't care Bit 7 Bit 6 Bit 5 Bit 4 Channel 2 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 1 0 1 0 1 1 0 0 1 1 0 1 1 * * * -- Setting disabled *: Don't care Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR2B is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR1B is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match 269 Bits 3 to 0-- I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC. Bit 3 Bit 2 Bit 1 Bit 0 Channel 0 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0A is Capture input source is input TIOCA0 pin capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR0A is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT1 source is channel count-up/count-down 1/ count clock *: Don't care 270 Bit 3 Bit 2 Bit 1 Bit 0 Channel 0 IOC3 IOC2 IOC1 IOC0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0C is Capture input source is input TIOCC0 pin capture register* 1 Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR0C is Output disabled output Initial output is 0 compare output register* 1 (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT1 source is channel count-up/count-down 1/count clock *: Don't care Note: *1 When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 271 Bit 3 Bit 2 Bit 1 Bit 0 Channel 1 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR1A is Capture input source is input TIOCA1 pin capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR1A is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at generation of Capture input source is TGR0A channel 0/TGR0A compare compare match/ match/input capture input capture *: Don't care Bit 3 Bit 2 Bit 1 Bit 0 Channel 2 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * TGR2A is Capture input source is input TIOCA2 pin capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care TGR2A is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match 272 10.2.4 Timer Interrupt Enable Register (TIER) Channel 0: TIER0 Bit : 7 TTGE Initial value : R/W : 0 R/W 6 -- 1 -- 5 -- 0 -- 4 TCIEV 0 R/W 3 TGIED 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W Channel 1: TIER1 Channel 2: TIER2 Bit : 7 TTGE Initial value : R/W : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 -- 0 -- 2 -- 0 -- 1 TGIEB 0 R/W 0 TGIEA 0 R/W The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for each channel. The TPU has three TIER registers, one for each channel. The TIER registers are initialized to H'40 by a reset, and in hardware standby mode. Bit 7--A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. Bit 7 TTGE 0 1 Description A/D conversion start request generation disabled A/D conversion start request generation enabled (Initial value) Bit 6--Reserved: Read-only bit, always read as 1. Bit 5--Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channel 0, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 TCIEU 0 1 Description Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled (Initial value) 273 Bit 4--Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. Bit 4 TCIEV 0 1 Description Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled (Initial value) Bit 3--TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channel 0. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3 TGIED 0 1 Description Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled (Initial value) Bit 2--TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channel 0. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified. Bit 2 TGIEC 0 1 Description Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled (Initial value) Bit 1--TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. Bit 1 TGIEB 0 1 Description Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled (Initial value) 274 Bit 0--TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. Bit 0 TGIEA 0 1 Description Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled (Initial value) 10.2.5 Timer Status Register (TSR) Channel 0: TSR0 Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 0 -- 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* Channel 1: TSR1 Channel 2: TSR2 Bit : 7 TCFD Initial value : R/W : 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 -- 0 -- 2 -- 0 -- 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* Note: * Can only be written with 0 for flag clearing. The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has three TSR registers, one for each channel. The TSR registers are initialized to H'C0 by a reset, and in hardware standby mode. Bit 7--Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT counts in channels 1 and 2. In channel 0, bit 7 is reserved. It is always read as 1 and cannot be modified. Bit 7 TCFD 0 1 Description TCNT counts down TCNT counts up (Initial value) 275 Bit 6--Reserved: Read-only bit, always read as 1 and cannot be modified. Bit 5--Underflow Flag (TCFU): Status flag that indicates that TCNT underflow has occurred when channel 1 is set to phase counting mode. In channels 0 and 2, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 TCFU 0 1 Description [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) (Initial value) Bit 4--Overflow Flag (TCFV): Status flag that indicates that TCNT overflow has occurred. Bit 4 TCFV 0 Description [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) (Initial value) Bit 3--Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the occurrence of TGRD input capture or compare match in channel 0. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3 TGFD 0 Description [Clearing conditions] * * 1 * * (Initial value) When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFD after reading TGFD = 1 [Setting conditions] When TCNT = TGRD while TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register Bit 2--Input Capture/Output Compare Flag C (TGFC): Status flag that indicates the occurrence of TGRC input capture or compare match in channel 0. 276 In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified. Bit 2 TGFC 0 Description [Clearing conditions] * * 1 * * (Initial value) When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] When TCNT = TGRC while TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register Bit 1--Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the occurrence of TGRB input capture (only for channel 0) or compare match. Bit 1 TGFB 0 Description [Clearing conditions] * * 1 * * (Initial value) When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] When TCNT = TGRB while TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register (only for channel 0) Bit 0--Input Capture/Output Compare Flag A (TGFA): Status flag that indicates the occurrence of TGRA input capture or compare match. Bit 0 TGFA 0 Description [Clearing conditions] * * 1 (Initial value) When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * * When TCNT = TGRA while TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 277 10.2.6 Timer Counter (TCNT) Channel 0: TCNT0 (up-counter) Channel 1: TCNT1 (up/down-counter*) Channel 2: TCNT2 (up/down-counter*) Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. In other cases they function as up-counters. The TCNT registers are 16-bit counters. The TPU has three TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 10.2.7 Bit Timer General Register (TGR) : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The TGR registers are 16-bit registers with a dual function as output compare and input capture registers. The TPU has eight TGR registers, four for channel 0 and two each for channels 1 and 2. TGRC and TGRD for channel 0 can also be designated for operation as buffer registers*. The TGR registers are initialized to H'FFFF by a reset, and in hardware standby mode. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. Note: * TGR buffer register combinations are TGRA-TGRC and TGRB-TGRD. 278 10.2.8 Bit Timer Start Register (TSTR) : 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W Initial value : R/W : TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 2. TSTR is initialized to H'00 by a reset, and in hardware standby mode. TCNT counter operation must be halted before setting the operating mode in TMDR, or setting the TCNT count clock in TCR. Bits 7 to 3--Reserved: Should always be written with 0. Bits 2 to 0--Counter Start 2 to 0 (CST2 to CST0): These bits select operation or stoppage for TCNT. Bit n CSTn 0 1 Description TCNTn count operation is stopped TCNTn performs count operation (Initial value) n = 2 to 0 Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 279 10.2.9 Bit Timer Synchro Register (TSYR) : 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W Initial value : R/W : TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 2 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. TSYR is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 to 3--Reserved: Should always be written with 0. Bits 2 to 0--Timer Synchro 2 to 0 (SYNC2 to SYNC0): These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels*1, and synchronous clearing through counter clearing on another channel* 2 are possible. Bit n SYNCn 0 1 Description TCNTn operates independently (TCNT presetting/clearing is unrelated to other channels) (Initial value) TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible n = 2 to 0 Notes: *1 To set synchronous operation, the SYNC bits for at least two channels must be set to 1. *2 To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 280 10.2.10 Bit Module Stop Control Register A (MSTPCRA) : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : MSTPCRA is an 8-bit readable/writable register that performs module stop mode control. When the MSTPA5 bit in MSTPCR is set to 1, TPU operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 19.5, Module Stop Mode. MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 5--Module Stop (MSTPA5): Specifies the TPU module stop mode. Bit 5 MSTPA5 0 1 Description TPU module stop mode cleared TPU module stop mode set (Initial value) 281 10.3 10.3.1 Interface to Bus Master 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 10.2. Internal data bus H Bus master Module data bus L Bus interface TCNTH TCNTL Figure 10.2 16-Bit Register Access Operation [Bus Master TCNT (16 Bits)] 10.3.2 8-Bit Registers Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit units. Examples of 8-bit register access operation are shown in figures 10.3, 10.4, and 10.5. Internal data bus H Bus master Module data bus L Bus interface TCR Figure 10.3 8-Bit Register Access Operation [Bus Master TCR (Upper 8 Bits)] 282 Internal data bus H Bus master Module data bus L Bus interface TMDR Figure 10.4 8-Bit Register Access Operation [Bus Master TMDR (Lower 8 Bits)] Internal data bus H Bus master Module data bus L Bus interface TCR TMDR Figure 10.5 8-Bit Register Access Operation [Bus Master TCR and TMDR (16 Bits)] 283 10.4 10.4.1 Operation Overview Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register (excepted TGR1B and TGR2B) or output compare register. Synchronous Operation: When synchronous operation is designated for a channel, TCNT for that channel performs synchronous presetting. That is, when TCNT for a channel designated for synchronous operation is rewritten, the TCNT counters for the other channels are also rewritten at the same time. Synchronous clearing of the TCNT counters is also possible by setting the timer synchronization bits in TSYR for channels designated for synchronous operation. Buffer Operation * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the relevant channel is transferred to TGR. * When TGR (excepted TGR1B and TGR2B) is an input capture register When input capture occurs, the value in TCNT is transfer to TGR and the value previously held in TGR is transferred to the buffer register. PWM Mode: In this mode, a PWM waveform is output. The output level can be set by means of TIOR. A PWM waveform with a duty of between 0% and 100% can be output, according to the setting of each TGR register. Phase Counting Mode: In this mode, TCNT is incremented or decremented by detecting the phases of two clocks input from the external clock input pins in channel 1. When phase counting mode is set, the corresponding TCLK pin functions as the clock pin, and TCNT performs up- or down-counting. This can be used for two-phase encoder pulse input. 284 10.4.2 Basic Functions Counter Operation: When one of bits CST0 to CST2 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. * Example of count operation setting procedure Figure 10.6 shows an example of the count operation setting procedure. Operation selection Select counter clock [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Free-running counter [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. Start count operation Periodic counter Select counter clearing source [2] Select output compare register [3] Set period [4] Start count operation [5] Figure 10.6 Example of Counter Operation Setting Procedure 285 * Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 10.7 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 10.7 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts up-count operation as periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. 286 Figure 10.8 illustrates periodic counter operation. Counter cleared by TGR compare match TCNT value TGR H'0000 Time CST bit Flag cleared by software or DTC activation TGF Figure 10.8 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. * Example of setting procedure for waveform output by compare match Figure 10.9 shows an example of the setting procedure for waveform output by compare match. [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. Set output timing [2] Output selection Select waveform output mode [1] [3] Set the CST bit in TSTR to 1 to start the count operation. Start count operation [3] There is no output compare output pin (TIOC) corresponding to TGR1B and TGR2B. They must be used as a compare match interrupt source or a compare match function in PWM mode. Figure 10.9 Example Of Setting Procedure For Waveform Output By Compare Match 287 * Examples of waveform output operation Figure 10.10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB H'0000 No change TIOCA TIOCB* Note: * Applied to channel 0 No change No change No change 1 output 0 output Time Figure 10.10 Example of 0 Output/1 Output Operation Figure 10.11 shows an example of toggle output. In this example TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 TIOCB* TIOCA Note: * Applied to channel 0 Time Toggle output Toggle output Figure 10.11 Example of Toggle Output Operation 288 Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0 and 1, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channel 0, o/1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if o/1 is selected. * Example of input capture operation setting procedure Figure 10.12 shows an example of the input capture operation setting procedure. [1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [1] Input selection Select input capture input [2] Set the CST bit in TSTR to 1 to start the count operation. Start count [2] Figure 10.12 Example of Input Capture Operation Setting Procedure 289 * Example of input capture operation Figure 10.13 shows an example of input capture operation of channel 0. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 H'0000 Time TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 10.13 Example of Input Capture Operation 290 10.4.3 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 2 can all be designated for synchronous operation. Example of Synchronous Operation Setting Procedure: Figure 10.14 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Synchronous clearing Set TCNT [2] Clearing sourcegeneration channel? Yes Select counter clearing source Start count No [3] Set synchronous counter clearing Start count [4] [5] [5] [1] [2] [3] [4] [5] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 10.14 Example of Synchronous Operation Setting Procedure 291 Example of Synchronous Operation: Figure 10.15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGR0B compare match, is performed for channel 0 to 2 TCNT counters, and the data set in TGR0B is used as the PWM cycle. For details of PWM modes, see section 10.4.5, PWM Modes. Synchronous clearing by TGR0B compare match TCNT0 to TCNT2 values TGR0B TGR1B TGR0A TGR2B TGR1A TGR2A H'0000 Time TIOC0A TIOC1A TIOC2A Figure 10.15 Example of Synchronous Operation 292 10.4.4 Buffer Operation Buffer operation, provided for channel 0, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 10.5 shows the register combinations used in buffer operation. Table 10.5 Register Combinations in Buffer Operation Channel 0 Timer General Register TGR0A TGR0B Buffer Register TGR0C TGR0D * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 10.16. Compare match signal Buffer register Timer general register Comparator TCNT Figure 10.16 Compare Match Buffer Operation 293 * When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 10.17. Input capture signal Timer general register Buffer register TCNT Figure 10.17 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure: Figure 10.18 shows an example of the buffer operation setting procedure. [1] Designate TGR as an input capture register or output compare register by means of TIOR. [1] Buffer operation Select TGR function [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 to start the count operation. Set buffer operation [2] Start count [3] Figure 10.18 Example of Buffer Operation Setting Procedure 294 Examples of Buffer Operation * When TGR is an output compare register Figure 10.19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare match A occurs. For details of PWM modes, see section 10.4.5, PWM Modes. TCNT value TGR0B H'0200 TGR0A H'0000 TGR0C H'0200 Transfer TGR0A H'0200 H'0450 H'0450 H'0520 Time H'0520 H'0450 TIOCA Figure 10.19 Example of Buffer Operation (1) 295 * When TGR is an input capture register Figure 10.20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 H'0F07 H'09FB TGRC H'0532 H'0F07 Figure 10.20 Example of Buffer Operation (2) 10.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. 296 There are two PWM modes, as described below. * PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 4-phase PWM output is possible. * PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 6-phase PWM output is possible by combined use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 10.6. Table 10.6 PWM Output Registers and Output Pins Output Pins Channel 0 Registers TGR0A TGR0B TGR0C TGR0D 1 TGR1A TGR1B 2 TGR2A TGR2B TIOCA2 TIOCA1 TIOCC0 PWM Mode 1 TIOCA0 PWM Mode 2 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 -- TIOCA2 -- Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. There is no output pins corresponding to TGR1B and TGR2B in PWM mode 2. They must be used as cycle registers. 297 Example of PWM Mode Setting Procedure: Figure 10.21 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. Select counter clearing source [2] PWM mode Select counter clock [1] Select waveform output level [3] [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other the TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. Set TGR [4] Set PWM mode [5] [6] Set the CST bit in TSTR to 1 to start the count operation. Start count [6] Figure 10.21 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation: Figure 10.22 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in TGRB registers as the duty. 298 TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 Time TIOCA Figure 10.22 Example of PWM Mode Operation (1) Figure 10.23 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM waveform. In this case, the value set in TGR1B is used as the cycle, and the values set in the other TGRs as the duty. Counter cleared by TGR1B compare match TCNT value TGR1B TGR1A TGR0D TGR0C TGR0B TGR0A H'0000 Time TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 Figure 10.23 Example of PWM Mode Operation (2) 299 Figure 10.24 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRA TGRB rewritten TGRB H'0000 0% duty TGRB rewritten TGRB rewritten Time TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty TGRB rewritten Time TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty 0% duty TGRB rewritten Time TIOCA Figure 10.24 Example of PWM Mode Operation (3) 300 10.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channel 1. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 10.7 shows the correspondence between external clock pins and channels. Table 10.7 Phase Counting Mode Clock Input Pins External Clock Pins Channels When channel 1 is set to phase counting mode A-Phase TCLKA B-Phase TCLKB Example of Phase Counting Mode Setting Procedure: Figure 10.25 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Phase counting mode Select phase counting mode [1] Start count [2] Figure 10.25 Example of Phase Counting Mode Setting Procedure 301 Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. * Phase counting mode 1 Figure 10.26 shows an example of phase counting mode 1 operation, and table 10.8 summarizes the TCNT up/down-count conditions. TCLKA TCLKB TCNT value Up-count Down-count Time Figure 10.26 Example of Phase Counting Mode 1 Operation Table 10.8 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA High level Low level Low level High level High level Low level High level Low level Legend : Rising edge : Falling edge Down-count TCLKB Operation Up-count 302 * Phase counting mode 2 Figure 10.27 shows an example of phase counting mode 2 operation, and table 10.9 summarizes the TCNT up/down-count conditions. TCLKA TCLKB TCNT value Up-count Down-count Time Figure 10.27 Example of Phase Counting Mode 2 Operation Table 10.9 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA High level Low level Low level High level High level Low level High level Low level Legend : Rising edge : Falling edge TCLKB Operation Don't care Don't care Don't care Up-count Don't care Don't care Don't care Down-count 303 * Phase counting mode 3 Figure 10.28 shows an example of phase counting mode 3 operation, and table 10.10 summarizes the TCNT up/down-count conditions. TCLKA TCLKB TCNT value Up-count Down-count Time Figure 10.28 Example of Phase Counting Mode 3 Operation Table 10.10 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA High level Low level Low level High level High level Low level High level Low level Legend : Rising edge : Falling edge TCLKB Operation Don't care Don't care Don't care Up-count Down-count Don't care Don't care Don't care 304 * Phase counting mode 4 Figure 10.29 shows an example of phase counting mode 4 operation, and table 10.11 summarizes the TCNT up/down-count conditions. TCLKA TCLKB TCNT value Down-count Up-count Time Figure 10.29 Example of Phase Counting Mode 4 Operation Table 10.11 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA High level Low level Low level High level High level Low level High level Low level Legend : Rising edge : Falling edge Don't care Down-count Don't care TCLKB Operation Up-count Phase Counting Mode Application Example: Figure 10.30 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGR0C compare match; TGR0A and TGR0C are used for the compare match function, and are set with the speed control period and position 305 control period. TGR0B is used for input capture, with TGR0B and TGR0D operating in buffer mode. The channel 1 counter input clock is designated as the TGR0B input capture source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed. TGR1A and TGR1B for channel 1 are designated for input capture, channel 0 TGR0A and TGR0C compare matches are selected as the input capture source, and store the up/down-counter values for the control periods. This procedure enables accurate position/speed detection to be achieved. Channel 1 TCLKA TCLKB Edge detection circuit TCNT1 TGR1A (speed period capture) TGR1B (position period capture) TCNT0 + TGR0A (speed control period) - TGR0C (position control period) + - TGR0B (pulse width capture) TGR0D (buffer operation) Channel 0 Figure 10.30 Phase Counting Mode Application Example 306 10.5 10.5.1 Interrupts Interrupt Sources and Priorities There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. For details, see section 5, Interrupt Controller. Table 10.12 lists the TPU interrupt sources. Table 10.12 TPU Interrupts Channel 0 Interrupt Source TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U Description TGR0A input capture/compare match TGR0B input capture/compare match TGR0C input capture/compare match TGR0D input capture/compare match TCNT0 overflow TGR1A input capture/compare match TGR1B compare match TCNT1 overflow TCNT1 underflow TGR2A input capture/compare match TGR2B compare match TCNT2 overflow TCNT2 underflow DTC Activation Possible Possible Possible Possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Low Priority High Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. 307 Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has eight input capture/compare match interrupts, four for channel 0, and two each for channels 1 and 2. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has three overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has two underflow interrupts, one each for channels 1 and 2. 10.5.2 DTC Activation DTC Activation: The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 8, Data Transfer Controller (DTC). A total of 8 TPU input capture/compare match interrupts can be used as DTC activation sources, four for channel 0, and two each for channels 1 and 2. 10.5.3 A/D Converter Activation The A/D converter can be activated by the TGRA input capture/compare match for a channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. In the TPU, a total of three TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. 308 10.6 10.6.1 Operation Timing Input/Output Timing TCNT Count Timing: Figure 10.31 shows TCNT count timing in internal clock operation, and figure 10.32 shows TCNT count timing in external clock operation. o Internal clock Falling edge Rising edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 10.31 Count Timing in Internal Clock Operation o External clock Falling edge Rising edge Falling edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 10.32 Count Timing in External Clock Operation 309 Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 10.33 shows output compare output timing. o TCNT input clock TCNT N N+1 TGR N Compare match signal TIOC pin Figure 10.33 Output Compare Output Timing Input Capture Signal Timing: Figure 10.34 shows input capture signal timing. o Input capture input Input capture signal TCNT N N+1 N+2 TGR N N+2 Figure 10.34 Input Capture Input Signal Timing 310 Timing for Counter Clearing by Compare Match/Input Capture: Figure 10.35 shows the timing when counter clearing by compare match occurrence is specified, and figure 10.36 shows the timing when counter clearing by input capture occurrence is specified. o Compare match signal Counter clear signal N H'0000 TCNT TGR N Figure 10.35 Counter Clear Timing (Compare Match) o Input capture signal Counter clear signal N H'0000 TCNT TGR N Figure 10.36 Counter Clear Timing (Input Capture) 311 Buffer Operation Timing: Figures 10.37 and 10.38 show the timing in buffer operation. o TCNT n n+1 Compare match signal TGRA, TGRB TGRC, TGRD n N N Figure 10.37 Buffer Operation Timing (Compare Match) o Input capture signal TCNT TGRA, TGRB TGRC, TGRD N N+1 n N N+1 n N Figure 10.38 Buffer Operation Timing (Input Capture) 312 10.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 10.39 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. o TCNT input clock TCNT N N+1 TGR N Compare match signal TGF flag TGI interrupt Figure 10.39 TGI Interrupt Timing (Compare Match) 313 TGF Flag Setting Timing in Case of Input Capture: Figure 10.40 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. o Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 10.40 TGI Interrupt Timing (Input Capture) 314 TCFV Flag/TCFU Flag Setting Timing: Figure 10.41 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 10.42 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing. o TCNT input clock TCNT (overflow) Overflow signal TCFV flag H'FFFF H'0000 TCIV interrupt Figure 10.41 TCIV Interrupt Setting Timing o TCNT input clock TCNT (underflow) Underflow signal H'0000 H'FFFF TCFU flag TCIU interrupt Figure 10.42 TCIU Interrupt Setting Timing 315 Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is activated, the flag is cleared automatically. Figure 10.43 shows the timing for status flag clearing by the CPU, and figure 10.44 shows the timing for status flag clearing by the DTC. TSR write cycle T1 T2 o Address TSR address Write signal Status flag Interrupt request signal Figure 10.43 Timing for Status Flag Clearing by CPU DTC read cycle T1 o T2 DTC write cycle T1 T2 Address Source address Destination address Status flag Interrupt request signal Figure 10.44 Timing for Status Flag Clearing by DTC Activation 316 10.7 Usage Notes Note that the kinds of operation and contention described below occur during TPU operation. Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.45 shows the input clock conditions in phase counting mode. Phase Phase differdifference Overlap ence Overlap TCLKA Pulse width Pulse width TCLKB Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more : 2.5 states or more Pulse width Figure 10.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= Where o (N + 1) f : Counter frequency o : Operating frequency N : TGR set value 317 Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10.46 shows the timing in this case. TCNT write cycle T1 T2 o Address TCNT address Write signal Counter clear signal TCNT N H'0000 Figure 10.46 Contention between TCNT Write and Clear Operations 318 Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 10.47 shows the timing in this case. TCNT write cycle T1 T2 o Address TCNT address Write signal TCNT input clock N TCNT write data M TCNT Figure 10.47 Contention between TCNT Write and Increment Operations 319 Contention between TGR Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 10.48 shows the timing in this case. TGR write cycle T1 T2 o Address TGR address Write signal Compare match signal TCNT N N+1 Inhibited TGR N TGR write data M Figure 10.48 Contention between TGR Write and Compare Match 320 Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 10.49 shows the timing in this case. TGR write cycle T1 T2 o Address Buffer register address Write signal Compare match signal Buffer register write data Buffer register TGR N M N Figure 10.49 Contention between Buffer Register Write and Compare Match 321 Contention between TGR Read and Input Capture: If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 10.50 shows the timing in this case. TGR read cycle T1 T2 o Address TGR address Read signal Input capture signal TGR X M Internal data bus M Figure 10.50 Contention between TGR Read and Input Capture 322 Contention between TGR Write and Input Capture: If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10.51 shows the timing in this case. TGR write cycle T1 T2 o Address TGR address Write signal Input capture signal TCNT M TGR M Figure 10.51 Contention between TGR Write and Input Capture 323 Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10.52 shows the timing in this case. Buffer register write cycle T1 T2 o Address Buffer register address Write signal Input capture signal TCNT N TGR Buffer register M N M Figure 10.52 Contention between Buffer Register Write and Input Capture 324 Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10.53 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. o TCNT input clock TCNT Counter clear signal TGF Disabled TCFV H'FFFF H'0000 Figure 10.53 Contention between Overflow and Counter Clearing 325 Contention between TCNT Write and Overflow/Underflow: If there is an up-count or downcount in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set . Figure 10.54 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T1 T2 o Address TCNT address Write signal TCNT write data H'FFFF Disabled M TCNT TCFV flag Figure 10.54 Contention between TCNT Write and Overflow Multiplexing of I/O Pins: In the LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin and the TCLKB input pin with the TIOCD0 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. 326 Section 11 8-Bit Timers (TMR) 11.1 Overview The LSI includes an 8-bit timer module with two channels (TMR0, TMR1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB). 11.1.1 Features The features of the 8-bit timer module are listed below. * Selection of three clock sources The counters can be driven by one of three internal clock signals (o/8, o/64, or o/8192). * Selection of two ways to clear the counters The counters can be cleared on compare match A or B. * Provision for cascading of two channels Operation as a 16-bit timer is possible, using channel 0 for the upper 8 bits and channel 1 for the lower 8 bits (16-bit count mode). Channel 1 can be used to count channel 0 compare matches (compare match count mode). * Three independent interrupts Compare match A and B and overflow interrupts can be requested independently. * A/D converter conversion start trigger can be generated Channel 0 compare match A signal can be used as an A/D converter conversion start trigger. * Module stop mode can be set As the initial setting, 8-bit timer operation is halted. Register access is enabled by exiting module stop mode. 327 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the 8-bit timer module in case of TMR0 and TMR1. Internal clock sources o/8 o/64 o/8192 Clock select Clock 1 Clock 0 TCORA0 Compare match A1 Compare match A0 Comparator A0 Overflow 1 Overflow 0 Clear 0 Compare match B1 Compare match B0 Comparator B0 Internal bus Clear 1 TCORA1 Comparator A1 TCNT0 TCNT1 A/D conversion start request signal Control logic Comparator B1 TCORB0 TCORB1 TCSR0 TCSR1 TCR0 CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt signals TCR1 Figure 11.1 Block Diagram of 8-Bit Timer 328 11.1.3 Register Configuration Table 11.1 summarizes the registers of the 8-bit timer module. Table 11.1 8-Bit Timer Registers Channel 0 Name Timer control register 0 Abbreviation TCR0 R/W R/W R/(W)* R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W 2 2 Initial value H'00 H'00 H'FF H'FF H'00 H'00 H'10 H'FF H'FF H'00 H'3F Address* 1 H'FF68 H'FF6A H'FF6C H'FF6E H'FF70 H'FF69 H'FF6B H'FF6D H'FF6F H'FF71 H'FDE8 Timer control/status register 0 TCSR0 Time constant register A0 Time constant register B0 Timer counter 0 1 Timer control register 1 TCORA0 TCORB0 TCNT0 TCR1 Timer control/status register 1 TCSR1 Time constant register A1 Time constant register B1 Timer counter 1 TCORA1 TCORB1 TCNT1 Common Module stop control register A MSTPCRA Notes: *1 Lower 16 bits of the address *2 Only 0 can be written to bits 7 to 5, to clear these flags. Each pair of registers for channel 0 and channel 1 is a 16-bit register with the upper 8 bits for channel 0 and the lower 8 bits for channel 1, so they can be accessed together by word transfer instruction. 329 11.2 11.2.1 Register Descriptions Timer Counters 0 and 1 (TCNT0, TCNT1) TCNT0 TCNT1 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Bit : 15 0 14 0 13 0 12 0 11 0 Initial value: R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT0 and TCNT1 are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. This clock source is selected by clock select bits CKS2 to CKS0 of TCR. The CPU can read or write to TCNT0 and TCNT1 at all times. TCNT0 and TCNT1 comprise a single 16-bit register, so they can be accessed together by a word transfer instruction. TCNT0 and TCNT1 can be cleared by a compare match signal. Which signal is to be used for clearing is selected by clock clear bits CCLR1 and CCLR0 of TCR. When a timer counter overflows from H'FF to H'00, OVF in TCSR is set to 1. TCNT0 and TCNT1 are each initialized to H'00 by a reset and in hardware standby mode. 11.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1) TCORA0 Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 TCORA1 4 1 3 1 2 1 1 1 0 1 Initial value: R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORA0 and TCORA1 are 8-bit readable/writable registers. TCORA0 and TCORA1 comprise a single 16-bit register so they can be accessed together by word transfer instruction. TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding CMFA flag in TCSR is set to 1. Note, however, that comparison is disabled during the T2 state of a TCOR write cycle. TCORA0 and TCORA1 are each initialized to H'FF by a reset and in hardware standby mode. 330 11.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1) TCORB0 TCORB1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 1 14 1 13 1 12 1 11 1 Initial value: R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB0 and TCORB1 are 8-bit readable/writable registers. TCORB0 and TCORB1 comprise a single 16-bit register so they can be accessed together by word transfer instruction. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding CMFB flag in TCSR is set to 1. Note, however, that comparison is disabled during the T2 state of a TCOR write cycle. TCORB0 and TCORB1 are each initialized to H'FF by a reset and in hardware standby mode. 11.2.4 Bit Timer Control Registers 0 and 1 (TCR0, TCR1) : 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value: R/W : TCR0 and TCR1 are 8-bit readable/writable registers that select the input clock source and the time at which TCNT is cleared, and enable interrupts. TCR0 and TCR1 are each initialized to H'00 by a reset and in hardware standby mode. For details of this timing, see section 11.3, Operation. 331 Bit 7--Compare Match Interrupt Enable B (CMIEB): Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag of TCSR is set to 1. Bit 7 CMIEB 0 1 Description CMFB interrupt requests (CMIB) are disabled CMFB interrupt requests (CMIB) are enabled (Initial value) Bit 6--Compare Match Interrupt Enable A (CMIEA): Selects whether CMFA interrupt requests (CMIA) are enabled or disabled when the CMFA flag of TCSR is set to 1. Bit 6 CMIEA 0 1 Description CMFA interrupt requests (CMIA) are disabled CMFA interrupt requests (CMIA) are enabled (Initial value) Bit 5--Timer Overflow Interrupt Enable (OVIE): Selects whether OVF interrupt requests (OVI) are enabled or disabled when the OVF flag of TCSR is set to 1. Bit 5 OVIE 0 1 Description OVF interrupt requests (OVI) are disabled OVF interrupt requests (OVI) are enabled (Initial value) Bits 4 and 3--Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select the method by which TCNT is cleared: by compare match A or B. Bit 4 CCLR1 0 Bit 3 CCLR0 0 1 1 0 1 Description Clear is disabled Clear by compare match A Clear by compare match B Setting disabled (Initial value) 332 Bits 2 to 0--Clock Select 2 to 0 (CKS2 to CKS0): These bits select the clock input to TCNT is an internal clock. Three internal clocks can be selected, all divided from the system clock (o): o/8, o/64, and o/8192. The falling edge of the selected internal clock triggers the count. Some functions differ between channel 0 and channel 1. Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 Description Clock input disabled Internal clock, counted at falling edge of o/8 Internal clock, counted at falling edge of o/64 Internal clock, counted at falling edge of o/8192 For channel 0: count at TCNT1 overflow signal* For channel 1: count at TCNT0 compare match A* 1 1 0 1 Setting disabled Setting disabled Setting disabled (Initial value) Note: * If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting. 333 11.2.5 TCSR0 Bit Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1) : 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ADTE 0 R/W 3 -- 0 R/W 2 -- 0 R/W 1 -- 0 R/W 0 -- 0 R/W Initial value : R/W : TCSR1 Bit : 7 CMFB Initial value : R/W : 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 -- 1 -- 3 -- 0 R/W 2 -- 0 R/W 1 -- 0 R/W 0 -- 0 R/W Note: * Only 0 can be written to bits 7 to 5, to clear these flags. TCSR0 and TCSR1 are 8-bit registers that display compare match and overflow statuses, and control compare match output. TCSR0 is initialized to H'00, and TCSR1 to H'10, by a reset and in hardware standby mode. Bit 7--Compare Match Flag B (CMFB): Status flag indicating whether the values of TCNT and TCORB match. Bit 7 CMFB 0 Description [Clearing conditions] * * 1 Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 (Initial value) [Setting condition] Set when TCNT matches TCORB 334 Bit 6--Compare Match Flag A (CMFA): Status flag indicating whether the values of TCNT and TCORA match. Bit 6 CMFA 0 Description [Clearing conditions] * * 1 Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0 (Initial value) [Setting condition] Set when TCNT matches TCORA Bit 5--Timer Overflow Flag (OVF): Status flag indicating that TCNT has overflowed (changed from H'FF to H'00). Bit 5 OVF 0 Description [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 to OVF 1 [Setting condition] Set when TCNT overflows from H'FF to H'00 (Initial value) Bit 4--A/D Trigger Enable (ADTE) (TCSR0 Only): Selects enabling or disabling of A/D converter start requests by compare-match A. TCSR1 is reserved bit. When TCSR1 is read, always 1 is read off. It cannot be modified. Bit 4 ADTE 0 1 Description A/D converter start requests by compare match A are disabled A/D converter start requests by compare match A are enabled (Initial value) Bits 3 to 0--Reserved: Only 0 may be written to these bits. 335 11.2.6 Bit Module Stop Control Register A (MSTPCRA) : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : MSTPCRA is an 8-bit readable/writable register that performs module stop mode control. When the MSTPA4 bit in MSTPCRA is set to 1, the 8-bit timer operation stops at the end of the bus cycle and a transition is made to module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 4--Module Stop (MSTPA4): Specifies the TMR0 and TMR1 module stop mode. Bit 4 MSTPA4 0 1 Description TMR0, TMR1 module stop mode cleared TMR0, TMR1 module stop mode set (Initial value) Bit 0--Reserved: Only 1 may be written to this bit. 336 11.3 11.3.1 Operation TCNT Increment Timing TCNT is incremented by input clock pulses. Internal Clock: Three different internal clock signals (o/8, o/64, or o/8192) divided from the system clock (o) can be selected, by setting bits CKS2 to CKS0 in TCR. Figure 11.2 shows the count timing. o Internal clock Clock input to TCNT TCNT N-1 N N+1 Figure 11.2 Count Timing for Internal Clock Input 11.3.2 Compare Match Timing Setting of Compare Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare match signal is not generated until the next increment clock input. Figure 11.3 shows this timing. 337 o TCNT N N+1 TCOR Compare match signal N CMF Figure 11.3 Timing of CMF Setting Timing of Compare Match Clear: The timer counter is cleared when compare match A or B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 11.4 shows the timing of this operation. o Compare match signal TCNT N H'00 Figure 11.4 Timing of Compare Match Clear 338 11.3.3 Timing of Overflow Flag (OVF) Setting The OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure 11.5 shows the timing of this operation. o TCNT H'FF H'00 Overflow signal OVF Figure 11.5 Timing of OVF Setting 11.3.4 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit timer mode) or compare matches of the 8-bit timer channel 0 could be counted by the timer of channel 1 (compare match counter mode). In this case, the timer operates as below. 16-Bit Counter Mode: When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. * Setting of compare match flags The CMF flag in TCSR0 is set to 1 when a 16-bit compare match event occurs. The CMF flag in TCSR1 is set to 1 when a lower 8-bit compare match event occurs. * Counter clear specification If the CCLR1 and CCLR0 bits in TCR0 have been set for counter clear at compare match, the 16-bit counter (TCNT0 and TCNT1 together) is cleared when a 16-bit compare match event occurs. The settings of the CCLR1 and CCLR0 bits in TCR1 are ignored. The lower 8 bits cannot be cleared independently. 339 Compare Match Counter Mode: When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts compare match A's for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, and counter clear are in accordance with the settings for each channel. Note on Usage: If the 16-bit counter mode and compare match counter mode are set simultaneously, the input clock pulses for TCNT0 and TCNT1 are not generated and thus the counters will stop operating. Software should therefore avoid using both these modes. 11.4 11.4.1 Interrupts Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in Table 11.2. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR, and independent interrupt requests are sent for each to the interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts. Table 11.2 8-Bit Timer Interrupt Sources Channel 0 Interrupt Source CMIA0 CMIB0 OVI0 1 CMIA1 CMIB1 OVI1 Description Interrupt by CMFA Interrupt by CMFB Interrupt by OVF Interrupt by CMFA Interrupt by CMFB Interrupt by OVF DTC Activation Possible Possible Not possible Possible Possible Not possible Low Priority High Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. 11.4.2 A/D Converter Activation The A/D converter can be activated only by channel 0 compare match A. If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurrence of channel 0 compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. 340 11.5 Sample Application In the example below, the 8-bit timer is used to specify the cycle for generating an interrupt, as shown in figure 11.6. The control bits are set as follows: [1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA. [2] In TCR, bits CMIEB and CMIEA are set to 1 respectively, generating interrupts at TCORA and TCORB. TCNT H'FF TCORA TCORB H'00 Interrupts generated Counter clear Figure 11.6 Example of Pulse Output 341 11.6 Usage Notes Application programmers should note that the following kinds of contention can occur in the 8-bit timer. 11.6.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 11.7 shows this operation. TCNT write cycle by CPU T1 T2 o Address TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 11.7 Contention between TCNT Write and Clear 342 11.6.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 11.8 shows this operation. TCNT write cycle by CPU T1 T2 o Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 11.8 Contention between TCNT Write and Increment 343 11.6.3 Contention between TCOR Write and Compare Match During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match signal is disabled even if a compare match event occurs. Figure 11.9 shows this operation. TCOR write cycle by CPU T1 T2 o Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare match signal Disabled Figure 11.9 Contention between TCOR Write and Compare Match 11.6.4 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 11.3 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in case 3 in table 11.3, a TCNT clock pulse is generated on the assumption that the switchover is a falling edge. This increments TCNT. 344 Table 11.3 Switching of Internal Clock and TCNT Operation Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from low to low* 1 Clock before switchover Clock after switchover TCNT clock No. 1 TCNT N CKS bit write N+1 2 Switching from low to high* 2 Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit write 3 Switching from high to low* 3 Clock before switchover Clock after switchover *4 TCNT clock TCNT N N+1 CKS bit write N+2 345 No. 4 Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from high to high Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit write Notes: *1 *2 *3 *4 Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented. 11.6.5 Interrupts and Module Stop Mode If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. 346 Section 12 Watchdog Timer (WDT) 12.1 Overview The LSI has an on-chip watchdog timer with two channels (WDT0 and WDT1). The watchdog timer can generate an internal reset signal if a system crash prevents the CPU from writing to the counter, allowing it to overflow. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer mode, an interval timer interrupt is generated each time the counter overflows. 12.1.1 Features WDT features are listed below. * Switchable between watchdog timer mode and interval timer mode * Internal reset or internal interrupt generated when watchdog timer mode WDT0 Choice of whether or not an internal power-on reset is effected when the counter overflows WDT1 Choice of internal power-on reset or NMI interrupt generation when the counter overflows * Interrupt generation in interval timer mode An interval timer interrupt is generated when the counter overflows * Choice of 8 (WDT0) or 16 (WDT1) counter input clocks Maximum WDT interval: system clock period x 131072 x 256 Subclock can be selected for the WDT1 input counter Maximum interval when the subclock is selected: subclock period x 256 x 256 * Selected clock can be output from the BUZZ output pin (WDT1) 347 12.1.2 Block Diagram Figures 12.1 (a) and (b) show block diagrams of WDT0 and WDT1. WOVI0 (interrupt request signal) Overflow Interrupt control Clock Clock select Internal reset signal* Reset control o/2 o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 Internal clock RSTCSR TCNT TCSR Module bus Bus interface WDT Legend: TCSR: Timer control/status register TCNT: Timer counter RSTCSR: Reset control/status register Note: * A register setting can be used to generate a power-on reset. Figure 12.1 (a) Block Diagram of WDT0 348 Internal bus WOVI1 (interrupt request signal) Internal NMI (interrupt request signal) Internal reset signal* Interrupt control Reset control Overflow Clock Clock select o/2 o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 Internal clock source oSUB/2 oSUB/4 oSUB/8 oSUB/16 oSUB/32 oSUB/64 oSUB/128 oSUB/256 TCNT TCSR Module bus Bus interface WDT Legend: TCSR: Timer control/status register TCNT: Timer counter Note: * A register setting can be used to generate a power-on reset. Figure 12.1 (b) Block Diagram of WDT1 12.1.3 Pin Configuration Table 12.1 describes the WDT pin. Table 12.1 WDT Pin Name Buzzer output Symbol BUZZ I/O Output Function Outputs clock selected by watchdog timer (WDT1) Internal bus BUZZ 349 12.1.4 Register Configuration Table 12.2 summarizes the WDT registers. These registers control clock selection, WDT mode switching, the reset signal, etc. Table 12.2 WDT Registers Address* 1 Channel 0 Name Timer control/status register 0 Timer counter 0 Reset control/status register 1 Timer control/status register 1 Timer counter 1 Pin function control register Notes: *1 *2 *3 *4 Abbreviation R/W TCSR0 TCNT0 RSTCSR TCSR1 TCNT1 PFCR R/(W)* R/W R/(W)* 3 3 Initial Value H'18 H'00 H'1F H'00 H'00 H'0D/H'00* 4 Write*2 H'FF74 H'FF74 H'FF76 H'FFA2 H'FFA2 H'FDEB Read H'FF74 H'FF75 H'FF77 H'FFA2 H'FFA3 H'FDEB R/(W)*3 R/W R/W Lower 16 bits of the address. For details of write operations, see section 12.2.5, Notes on Register Access. Only 0 can be written in bit 7, to clear the flag. Initialized to H'0D in modes 4 and 5, and to H'00 in modes 6 and 7. 350 12.2 12.2.1 Bit Register Descriptions Timer Counter (TCNT) : 7 6 5 4 3 2 1 0 Initial value R/W : : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), the OVF flag in TCSR is set to 1. TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared to 0. It is not initialized in software standby mode. Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on Register Access. 12.2.2 Timer Control/Status Register (TCSR) * TCSR0 Bit : 7 OVF Initial value R/W : : 0 R/(W) * 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 -- 3 -- 1 -- 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Note: * Only 0 can be written, to clear the flag. 351 * TCSR1 Bit : 7 OVF Initial value R/W : : 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 PSS 0 R/W 3 RST/NMI 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Note: * Only 0 can be written, to clear the flag. TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. TCR is initialized to H'18 (H'00) by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on Register Access. Bit 7--Overflow Flag (OVF): A status flag that indicates that TCNT has overflowed from H'FF to H'00. Bit 7 OVF 0 Description [Clearing conditions] * * 1 Write 0 in the TME bit (Only applies to WDT1) Read TCSR when OVF = 1, then write 0 in OVF* (Initial value) [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. Note: * When the OVF flag is polled with the interval timer interrupt disabled, read the OVF bit while it is 1 at least twice. 352 Bit 6--Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or interval timer. If WDT0 is used in watchdog timer mode, it can generate a reset when TCNT overflows. If WDT0 is used in interval timer mode, it generates a WOVI interrupt request to the CPU when TCNT overflows. WDT1 generates a power-on reset or NMI interrupt request if used in watchdog timer mode, and a WOVI interrupt request if used in interval timer mode. * WDT0 mode selection WDT0 TCSR WT/IT 0 1 Description Interval timer mode: Interval timer interrupt (WOVI) request is sent to CPU when TCNT overflows (Initial value) Watchdog timer mode: Internal reset can be selected when TCNT overflows* Note: * For details of the case where TCNT overflows in watchdog timer mode, see section 12.2.3, Reset Control/Status Register (RSTCSR). * WDT1 mode selection WDT1 TCSR WT/IT 0 1 Description Interval timer mode: Interval timer interrupt (WOVI) request is sent to CPU when TCNT overflows (Initial value) Watchdog timer mode: Power-on reset or NMI interrupt request is sent to CPU when TCNT overflows Bit 5--Timer Enable (TME): Selects whether TCNT runs or is halted. Bit 5 TME 0 1 Description TCNT is initialized to H'00 and count operation is halted TCNT counts (Initial value) WDT0 TCSR Bit 4--Reserved: This bit cannot be modified and is always read as 1. 353 WDT1 TCSR Bit 4--Prescaler Select (PSS): Selects the input clock source for TCNT in WDT1. For details, see the description of the CKS2 to CKS0 bits below. WDT1 TCSR Bit 4 PSS 0 1 Description TCNT counts o-based prescaler (PSM) divided clock pulses TCNT counts oSUB-based prescaler (PSS) divided clock pulses (Initial value) WDT0 TCSR Bit 3--Reserved: This bit cannot be modified and is always read as 1. WDT1 TCSR Bit 3--Power-on Reset or NMI (RST/NMI): Specifies whether a power-on reset or NMI interrupt is requested on TCNT overflow in watchdog timer mode. Bit 3 RST/NMI 0 1 Description An NMI interrupt is requested A power-on reset is requested (Initial value) Bits 2 to 0--Clock Select 2 to 0 (CKS2 to CKS0): These bits select an internal clock source, obtained by dividing the system clock (o), or subclock (oSUB) for input to TCNT. * WDT0 input clock selection Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Clock o/2 (Initial value) o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 Description Overflow Period* (when o = 10 MHz) 51.2 s 1.6 ms 3.2 ms 13.2 ms 52.4 ms 209.8 ms 838.8 ms 3.36 s Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. 354 * WDT1 input clock selection Bit 4 PSS 0 Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Description Overflow Period 1.6 ms* 1 3.2 ms* 1 13.2 ms* 1 52.4 ms* 1 209.8 ms* 1 838.8 ms* 1 3.36 s * 1 6.7 ms* 2 13.3 ms* 2 26.7 ms* 2 53.3 ms* 2 106.7 ms* 2 213.3 ms* 2 426.7 ms* 2 853.3 ms* 2 3.2 ms* 3 6.4 ms* 3 12.8 ms* 3 25.6 ms* 3 51.2 ms* 3 102.4 ms* 3 204.8 ms* 3 409.6 ms* 3 o/2 (Initial value) 51.2 s * 1 o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 oSUB/2 oSUB/4 oSUB/8 oSUB/16 oSUB/32 oSUB/64 oSUB/128 oSUB/256 Notes: *1 The time from TCNT starting to count up from H'00 until it overflows, when o = 10 MHz. *2 The time from TCNT starting to count up from H'00 until it overflows, when oSUB = 76.8 kHz. *3 The time from TCNT starting to count up from H'83 until it overflows, when oSUB = 160 kHz. 355 12.2.3 Bit Reset Control/Status Register (RSTCSR) (WDT0 Only) : 7 WOVF 6 RSTE 0 R/W 5 -- 0 R/W 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value R/W : : 0 R/(W) * Note: * Only 0 can be written, to clear the flag. RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the internal reset signal caused by a WDT overflow. Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on Register Access. Bit 7--Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (from H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode. Bit 7 WOVF 0 Description [Clearing condition] Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF 1 [Setting condition] When TCNT overflows (from H'FF to H'00) in watchdog timer mode (Initial value) Bit 6--Reset Enable (RSTE): Specifies whether or not an internal reset signal is generated if TCNT overflows in watchdog timer mode. Bit 6 RSTE 0 1 Description No internal reset when TCNT overflows* Internal reset is generated when TCNT overflows (Initial value) Note: * The chip is not reset internally, but TCNT and TCSR in WDT0 are reset. 356 Bit 5--Reserved: Only 0 may be written to this bit. Bits 4 to 0--Reserved: These bits cannot be modified and are always read as 1. 12.2.4 Bit Pin Function Control Register (PFCR) : 7 -- 6 -- 5 BUZZE 4 -- 3 AE3 2 AE2 1 AE1 0 AE0 Modes 4 and 5 Initial value Initial value R/W : : : 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 1 0 R/W 1 0 R/W 0 0 R/W 1 0 R/W Modes 6 and 7 PFCR is an 8-bit readable/writable register that performs address output control in external expanded mode. Only bit 5 is described here. For details of the other bits, see section 7.2.6, Pin Function Control Register (PFCR). Bit 5--BUZZ Output Enable (BUZZE): Enables or disables BUZZ output from the PF1 pin. The WDT1 input clock selected with bits PSS and CKS2 to CKS0 is output as the BUZZ signal. Bit 5 BUZZE 0 1 Description Functions as PF1 I/O pin Functions as BUZZ output pin (Initial value) 357 12.2.5 Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction. They cannot be written to with byte transfer instructions. Figure 12.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the same write address. For a write to TCNT, the upper byte of the written word must contain H'5A and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written word must contain H'A5 and the lower byte must contain the write data. This transfers the write data from the lower byte to TCNT or TCSR. TCNT write 15 Address: H'FF74 H'5A 87 Write data 0 TCSR write 15 Address: H'FF74 H'A5 87 Write data 0 Figure 12.2 Format of Data Written to TCNT and TCSR (Example of WDT0) Writing to RSTCSR: RSTCSR must be written to by a word transfer to address H'FF76. It cannot be written to with byte instructions. Figure 12.3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF bit differs from that for writing to the RSTE and RSTS bits. To write 0 to the WOVF bit, the upper byte of the written word must contain H'A5 and the lower byte must contain H'00. This clears the WOVF bit to 0, but has no effect on the RSTE and RSTS bits. To write to the RSTE and RSTS bits, the upper byte must contain H'5A and the lower byte must contain the write data. This writes the values in bits 6 and 5 of the lower byte into the RSTE and RSTS bits, but has no effect on the WOVF bit. 358 Writing 0 to WOVF bit 15 Address: H'FF76 H'A5 87 H'00 0 Writing to RSTE and RSTS bits 15 Address: H'FF76 H'5A 87 Write data 0 Figure 12.3 Format of Data Written to RSTCSR (Example of WDT0) Reading TCNT, TCSR, and RSTCSR (Example of WDT0): These registers are read in the same way as other registers. The read addresses are H'FF74 for TCSR, H'FF75 for TCNT, and H'FF77 for RSTCSR. 12.3 12.3.1 Operation Watchdog Timer Operation To use the WDT as a watchdog timer, set the WT/IT and TME bits in TCSR to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before overflow occurs. In this way, TCNT will not overflow while the system is operating normally, but if TCNT is not rewritten and overflows because of a system crash or other error, in the case of WDT0, if the RSTE bit in RSTCSR is set to 1 beforehand, a signal is generated that effects an internal chip reset. The internal reset signal is output for 518 states. This is illustrated in figure 12.4. If a reset caused by an input signal from the RES pin and a reset caused by WDT overflow occur simultaneously, the RES pin reset has priority, and the WOVF bit in RSTCSR is cleared to 0. In the case of WDT1, the chip is reset, or an NMI interrupt request is generated, for 516 system clock periods (516o) (515 or 516 clock periods when the clock source is osub (PSS = 1)). This is illustrated in figure 12.4. An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are handled via the same vector. Simultaneous handling of a watchdog timer NMI interrupt request and an NMI pin interrupt request must therefore be avoided. 359 TCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 H'00 written to TCNT WOVF = 1 Internal reset generated WT/IT = 1 H'00 written TME = 1 to TCNT Time Internal reset signal* 518 states (WDT0) 515/516 states (WDT1) Legend: WT/IT: Timer mode select bit TME: Timer enable bit Note: * With WDT0, the internal reset signal is generated only when the RSTE bit is set to 1. With WDT1, an internal reset or NMI interrupt is generated. Figure 12.4 Operation in Watchdog Timer Mode 12.3.2 Interval Timer Operation To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 12.5. This function can be used to generate interrupt requests at regular intervals. 360 TCNT count H'FF Overflow Overflow Overflow Overflow H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI Time Legend: WOVI: Interval timer interrupt request generation Figure 12.5 Operation in Interval Timer Mode 12.3.3 Timing of Setting of Overflow Flag (OVF) The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 12.6. If NMI request generation is selected in watchdog timer mode, when TCNT overflows the OVF bit in TCSR is set to 1 and at the same time an NMI interrupt is requested. o TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 12.6 Timing of OVF Setting 361 12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) With WDT0, the WOVF bit in RSTCSR is set to 1 if TCNT overflows in watchdog timer mode. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire chip. This timing is illustrated in figure 12.7. o TCNT H'FF H'00 Overflow signal (internal signal) WOVF Internal reset signal 518 states (WDT0) 515/516 states (WDT1) Figure 12.7 Timing of WOVF Setting 12.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. When NMI interrupt request generation is selected in watchdog timer mode, an overflow generates an NMI interrupt request. 362 12.5 12.5.1 Usage Notes Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 12.8 shows this operation. TCNT write cycle T1 T2 o Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.8 Contention between TCNT Write and Increment 12.5.2 Changing Value of PSS and CKS2 to CKS0 If bits PSS and CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits PSS and CKS2 to CKS0. 12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. 363 12.5.4 Internal Reset in Watchdog Timer Mode If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not be reset internally if TCNT overflows, but TCNT0 and TCSR0 in WDT0 will be reset. TCNT, TCSR, and RSTCR cannot be written to for a 132-state interval after overflow occurs, and a read of the WOVF flag is not recognized during this time. It is therefore necessary to wait for 132 states after overflow occurs before writing 0 to the WOVF flag to clear it. 364 Section 13 Serial Communication Interface (SCI) 13.1 Overview The LSI is equipped with a mutually independent 3-channel* serial communication interface (SCI). The SCI can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). Note: * SCI3 is dedicated for use with the FLEXTM decoder II interface, and so does not appear on an external pin. 13.1.1 Features SCI features are listed below. * Choice of asynchronous or clocked synchronous serial communication mode Asynchronous mode Serial data communication executed using asynchronous system in which synchronization is achieved character by character Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA) A multiprocessor communication function is provided that enables serial data communication with a number of processors Choice of 12 serial data transfer formats Data length : 7 or 8 bits Stop bit length : 1 or 2 bits Parity : Even, odd, or none Multiprocessor bit : 1 or 0 Receive error detection : Parity, overrun, and framing errors Break detection : Break can be detected by reading the RxD pin level directly in case of a framing error Clocked Synchronous mode Serial data communication synchronized with a clock Serial data communication can be carried out with other chips that have a synchronous communication function 365 One serial data transfer format Data length : 8 bits Receive error detection : Overrun errors detected * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data * Choice of LSB-first or MSB-first transfer Can be selected regardless of the communication mode* (except in the case of asynchronous mode 7-bit data) Note: * Descriptions in this section refer to LSB-first transfer. * On-chip baud rate generator allows any bit rate to be selected * Choice of serial clock source: internal clock from baud rate generator or external clock from SCK pin (Except SCI3. Serial clock source of SCI3 is only internal clock) * Four interrupt sources Four interrupt sources -- transmit-data-empty, transmit-end, receive-data-full, and receive error -- that can issue requests independently The transmit-data-empty interrupt and receive data full interrupts can activate the data transfer controller (DTC) to execute data transfer * Module stop mode can be set As the initial setting, SCI operation is halted. Register access is enabled by exiting module stop mode. 366 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the SCI. Bus interface Module data bus Internal data bus RDR TDR RxD RSR TSR SCMR SSR SCR SMR Transmission/ reception control BRR o Baud rate generator o/4 o/16 o/64 Clock TxD Parity generation Parity check SCK External clock TEI TXI RXI ERI Legend RSR : Receive shift register RDR : Receive data register TSR : Transmit shift register TDR : Transmit data register SMR : Serial mode register SCR : Serial control register SSR : Serial status register SCMR : Smart card mode register BRR : Bit rate register Figure 13.1 Block Diagram of SCI 367 13.1.3 Pin Configuration Table 13.1 shows the serial pins for each SCI channel. Table 13.1 SCI Pins Channel 0 Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 1 Serial clock pin 1 Receive data pin 1 Transmit data pin 1 3 (dedicated Serial clock pin 3* to the FLEXTM Receive data pin 3* decoder II Transmit data pin 3* interface) Symbol SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 SCK3 RxD3 TxD3 I/O I/O Input Output I/O Input Output Output Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI3 clock output SCI3 receive data input SCI3 transmit data output Notes: Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation. * Dedicated for the FLEXTM decoder II interface, and does not have LSI-external connection point. 368 13.1.4 Register Configuration The SCI has the internal registers shown in table 13.2. These registers are used to specify asynchronous mode or clocked synchronous mode, the data format , and the bit rate, and to control transmitter/receiver. Table 13.2 SCI Registers Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Smart card mode register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Smart card mode register 1 3 (dedicated Serial mode register 3 to the Bit rate register 3 FLEXTM Serial control register 3 decoder II Transmit data register 3 interface) Serial status register 3 Receive data register 3 Smart card mode register 3 Common Module stop control register B Module stop control register C Abbreviation SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 SMR3 BRR3 SCR3 TDR3 SSR3 RDR3 SCMR3 MSTPCRB MSTPCRC R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W 2 2 2 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'FF H'FF Address* 1 H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FDD0 H'FDD1 H'FDD2 H'FDD3 H'FDD4 H'FDD5 H'FDD6 H'FDE9 H'FDEA Notes: *1 Lower 16 bits of the address. *2 Can only be written with 0 for flag clearing. 369 13.2 13.2.1 Bit R/W : : Register Descriptions Receive Shift Register (RSR) 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU. 13.2.2 Bit Receive Data Register (RDR) : 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R Initial value : R/W : RDR is a register that stores received serial data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous receive operations to be performed. RDR is a read-only register, and cannot be written to by the CPU. RDR is initialized to H'00 by a reset, in standby mode, watch mode, subactive mode, and subsleep mode or module stop mode. 370 13.2.3 Bit R/W : : Transmit Shift Register (TSR) 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not performed if the TDRE bit in SSR is set to 1. TSR cannot be directly read or written to by the CPU. 13.2.4 Bit Transmit Data Register (TDR) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : R/W : TDR is an 8-bit register that stores data for serial transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to TDR during serial transmission of the data in TSR. TDR can be read or written to by the CPU at all times. TDR is initialized to H'FF by a reset, in standby mode, watch mode, subactive mode, and subsleep mode or module stop mode. 371 13.2.5 Bit Serial Mode Register (SMR) : 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : SMR is an 8-bit register used to set the SCI's serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode. Bit 7--Communication Mode (C/A): Selects asynchronous mode or clocked synchronous mode as the SCI operating mode. Bit 7 C/A 0 1 Description Asynchronous mode Clocked synchronous mode (Initial value) Bit 6--Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In clocked synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting. Bit 6 CHR 0 1 Description 8-bit data 7-bit data* (Initial value) Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible to choose between LSB-first or MSB-first transfer. 372 Bit 5--Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In clocked synchronous mode with a multiprocessor format, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5 PE 0 1 Description Parity bit addition and checking disabled Parity bit addition and checking enabled* (Initial value) Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Bit 4--Parity Mode (O/E): Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is invalid in clocked synchronous mode, when parity addition and checking is disabled in asynchronous mode, and when a multiprocessor format is used. Bit 4 O/E 0 1 Description Even parity* 1 Odd parity* 2 (Initial value) Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. *2 When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. 373 Bit 3--Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bits setting is only valid in asynchronous mode. If clocked synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP 0 1 Description 1 stop bit: In transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. (Initial value) 2 stop bits: In transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2--Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in clocked synchronous mode. For details of the multiprocessor communication function, see section 13.3.3, Multiprocessor Communication Function. Bit 2 MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value) Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from o, o/4, o/16, and o/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 13.2.8, Bit Rate Register. Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 Description o clock o/4 clock o/16 clock o/64 clock (Initial value) 374 13.2.6 Bit Serial Control Register (SCR) : 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value : R/W : SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCR can be read or written to by the CPU at all times. SCR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode. Bit 7--Transmit Interrupt Enable (TIE): Enables or disables transmit data empty interrupt (TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE flag in SSR is set to 1. Bit 7 TIE 0 1 Description Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled (Initial value) Note: TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. Bit 6--Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI) request and receive error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1. Bit 6 RIE 0 1 Description Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled* (Initial value) Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Note: * RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0. 375 Bit 5--Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI. Bit 5 TE 0 1 Description Transmission disabled* 1 Transmission enabled* 2 (Initial value) Notes: *1 The TDRE flag in SSR is fixed at 1. *2 In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transfer format before setting the TE bit to 1. Bit 4--Receive Enable (RE): Enables or disables the start of serial reception by the SCI. Bit 4 RE 0 1 Description Reception disabled* 1 Reception enabled* 2 (Initial value) Notes: *1 Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. *2 Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the transfer format before setting the RE bit to 1. Bit 3--Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1. The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE 0 Description Multiprocessor interrupts disabled (normal reception performed) [Clearing conditions] * * 1 When the MPIE bit is cleared to 0 When MPB= 1 data is received (Initial value) Multiprocessor interrupts enabled* Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not 376 performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. Bit 2--Transmit End Interrupt Enable (TEIE): Enables or disables transmit end interrupt (TEI) request generation when there is no valid transmit data in TDR in MSB data transmission. Bit 2 TEIE 0 1 Description Transmit end interrupt (TEI) request disabled* Transmit end interrupt (TEI) request enabled* (Initial value) Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0. Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in clocked synchronous mode, and in the case of external clock operation (CKE1 = 1). Note that the SCI's operating mode must be decided using SMR after setting the CKE1 and CKE0 bits. External clock operation (CKE1 = 1) is disabled for the SCI3 that is the internal FLEXTM decoder II interface. The CKE1 bit should always be written with 0. For details of clock source selection, see table 13.9 in section 13.3, Operation. 377 Bit 1 CKE1 0 Bit 0 CKE0 0 Description Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode Internal clock/SCK pin functions as I/O port* 1 Internal clock/SCK pin functions as serial clock output* 1 Internal clock/SCK pin functions as clock output* 2 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input* 3 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input* 3 External clock/SCK pin functions as serial clock input 1* 4 0 Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode Notes: *1 *2 *3 *4 Initial value Outputs a clock of the same frequency as the bit rate. Inputs a clock with a frequency 16 times the bit rate. The CKE1 bit of SCR (channel 3) should always be written with 0. 13.2.7 Bit Serial Status Register (SSR) : 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value : R/W : Note: * Only 0 can be written, to clear the flag. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified. SSR is initialized to H'84 by a reset, in standby mode, watch mode, subactive mode, and subsleep mode or module stop mode. 378 Bit 7--Transmit Data Register Empty (TDRE): Indicates that data has been transferred from TDR to TSR and the next serial data can be written to TDR. Bit 7 TDRE 0 Description [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] (Initial value) * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR 1 Bit 6--Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR. Bit 6 RDRF 0 Description [Clearing conditions] (Initial value) * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Bit 5--Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5 ORER 0 Description [Clearing condition] When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1*2 Notes: *1 The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. *2 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. (Initial value)*1 379 Bit 4--Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4 FER 0 Description [Clearing condition] When 0 is written to FER after reading FER = 1 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 * 2 Notes: *1 The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. *2 In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. (Initial value)*1 Bit 3--Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 3 PER 0 1 Description [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR* 2 (Initial value)*1 Notes: *1 The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. *2 If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. 380 Bit 2--Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2 TEND 0 Description [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] (Initial value) * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character 1 Bit 1--Multiprocessor Bit (MPB): When reception is performed using multiprocessor format in asynchronous mode, MPB stores the multiprocessor bit in the receive data. MPB is a read-only bit, and cannot be modified. Bit 1 MPB 0 1 Description [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received (Initial value)* Note: * Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor format. Bit 0--Multiprocessor Bit Transfer (MPBT): When transmission is performed using multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when multiprocessor format is not used, when not transmitting, and in clocked synchronous mode. Bit 0 MPBT 0 1 Description Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted (Initial value) 381 13.2.8 Bit Bit Rate Register (BRR) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : R/W : BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset and in hardware standby mode. It retains its previous state in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode. As baud rate generator control is performed independently for each channel, different values can be set for each channel. Table 13.3 shows sample BRR settings in asynchronous mode, and table 13.4 shows sample BRR settings in clocked synchronous mode. 382 Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) o = 2 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -- -- 0.00 -- o = 2.097152 MHz Error (%) o = 2.4576 MHz Error (%) o = 3 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 -- n 1 1 0 0 0 0 0 -- -- 0 -- N 141 103 207 103 51 25 12 -- -- 1 -- n 1 1 0 0 0 0 0 0 -- -- -- N 148 108 217 108 54 26 13 6 -- -- -- n N 174 127 255 127 63 31 15 7 3 -- 1 n N 212 155 77 155 77 38 19 9 4 2 -- -0.04 1 0.21 0.21 0.21 1 0 0 -0.26 1 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 1 1 0 0 0 0 0 0 0 -- -0.70 0 1.14 0 -2.48 0 -2.48 0 -- -- -- 0 -- 0 o = 3.6864 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 o = 4 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -- 0.00 -- o = 4.9152 MHz Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 o = 5 MHz Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 n 2 1 1 0 0 0 0 0 0 -- 0 N 64 191 95 191 95 47 23 11 5 -- 2 n 2 1 1 0 0 0 0 0 -- 0 -- N 70 207 103 207 103 51 25 12 -- 3 -- n 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 n 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 -1.70 0 0.00 0 383 o = 6 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) o = 6.144 MHz Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 o = 7.3728 MHz Error (%) o = 8 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -- n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 n N 108 79 159 79 159 79 39 19 9 5 4 n 2 2 1 1 0 0 0 0 0 -- 0 N 130 95 191 95 191 95 47 23 11 -- 5 n N 141 103 207 103 207 103 51 25 12 7 -- -0.44 2 0.16 0.16 0.16 0.16 0.16 0.16 2 1 1 0 0 0 -0.07 2 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 2 1 1 0 0 0 0 0 0 -- -2.34 0 -2.34 0 0.00 0 -2.34 0 o = 9.8304 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) o = 10 MHz Error (%) o = 12 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 o = 12.288 MHz Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 n N 177 129 64 129 64 129 64 32 15 9 7 n N 212 155 77 155 77 155 77 38 19 11 9 n 2 2 2 1 1 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 -0.26 2 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2 2 1 1 0 0 0 0 -0.25 2 0.16 0.16 0.16 0.16 0.16 0.16 2 2 1 1 0 0 -1.36 0 1.73 0.00 1.73 0 0 0 -2.34 0 0.00 0 -1.70 0 0.00 0 -2.34 0 384 Table 13.4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Bit Rate (bit/s) 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 5M o = 2 MHz n 3 2 1 1 0 0 0 0 0 0 0 0 N 70 124 249 124 199 99 49 19 9 4 1 0* o = 4 MHz n -- 2 2 1 1 0 0 0 0 0 0 0 0 N -- 249 124 249 99 199 99 39 19 9 3 1 0* 1 1 0 0 0 0 0 0 149 74 149 59 29 14 5 2 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* -- -- -- 1 1 0 0 0 0 0 0 -- -- -- 249 124 249 99 49 24 9 4 o = 6 MHz n N o = 8 MHz n N o = 10 MHz n N Note: As far as possible, the setting should be made so that the error is no more than 1%. Legend Blank : Cannot be set. -- : Can be set, but there will be a degree of error. * : Continuous transfer is not possible. 385 The BRR setting is found from the following formulas. Asynchronous mode: N= o 64 x 22n-1 x B x 10 6 - 1 Clocked synchronous mode: N= Where B: N: o: n: o 8x2 2n-1 xB x 10 6 - 1 Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SMR Setting n 0 1 2 3 Clock o o/4 o/16 o/64 CKS1 0 0 1 1 CKS0 0 1 0 1 The bit rate error in asynchronous mode is found from the following formula: Error (%) = { o x 106 (N + 1) x B x 64 x 22n-1 - 1} x 100 386 Table 13.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 13.6 and 13.7 show the maximum bit rates with external clock input. Table 13.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) o (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 Maximum Bit Rate (bit/s) 62500 65536 76800 93750 115200 125000 153600 156250 187500 192000 230400 250000 307200 312500 375000 384000 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 387 Table 13.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) o (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 1.2500 1.5000 1.5360 1.8432 2.0000 2.4576 2.5000 3.0000 3.0720 Maximum Bit Rate (bit/s) 31250 32768 38400 46875 57600 62500 76800 78125 93750 96000 115200 125000 153600 156250 187500 192000 Table 13.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) o (MHz) 2 4 6 8 10 12 External Input Clock (MHz) 0.3333 0.6667 1.0000 1.3333 1.6667 2.0000 Maximum Bit Rate (bit/s) 333333.3 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 388 13.2.9 Bit Smart Card Mode Register (SCMR) : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W 2 -- 0 R/W 1 -- 1 -- 0 -- 0 R/W Initial value : R/W : SCMR selects LSB-first or MSB-first by means of bit SDIR. Except in the case of asynchronous mode 7-bit data, LSB-first or MSB-first can be selected regardless of the serial communication mode. The descriptions in this chapter refer to LSB-first transfer. SCMR is initialized to H'F2 by a reset and in hardware standby mode. It retains its previous state in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode. Bits 7 to 4--Reserved: These bits cannot be modified and are always read as 1. Bit 3--Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. This bit is valid when 8-bit data is used as the transmit/receive format. Bit 3 SDIR 0 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) Bits 2 and 0--Reserved: Only 0 should be written to these bits. Bit 1--Reserved: This bit cannot be modified and is always read as 1. 389 13.2.10 Module Stop Control Registers B and C (MSTPCRB, MSTPCRC) MSTPCRB Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : R/W MSTPCRC Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W : MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : R/W : MSTPCRB and MSTPCRC are 8-bit readable/writable registers that perform module stop mode control. When one of bits MSTPB7, MSTPB6, or MSTPC7 is set to 1, SCI0, SCI1, or SCI3, respectively, stops operation at the end of the bus cycle, and enters module stop mode. For details, see section 19.5, Module Stop Mode. MSTPCRB and MSTPCRC are each initialized to H'FF by a reset and in hardware standby mode. They are not initialized in software standby mode. Module Stop Control Register B (MSTPCRB) Bit 7--Module Stop (MSTPB7): Specifies the SCI0 module stop mode. Bit 7 MSTPB7 0 1 Description SCI0 module stop mode is cleared SCI0 module stop mode is set (Initial value) Bit 6--Module Stop (MSTPB6): Specifies the SCI1 module stop mode. Bit 6 MSTPB6 0 1 390 Description SCI1 module stop mode is cleared SCI1 module stop mode is set (Initial value) Bit 5--Reserved: Only 1 should be written to this bit. Module Stop Control Register C (MSTPCRC) Bit 7--Module Stop (MSTPC7): Specifies the SCI3 module stop mode. Bit 7 MSTPC7 0 1 Description SCI3 module stop mode is cleared SCI3 module stop mode is set (Initial value) 391 13.3 13.3.1 Operation Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and clocked synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or clocked synchronous mode and the transmission format is made using SMR as shown in table 13.8. The SCI clock is determined by a combination of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 13.9. Asynchronous Mode * Data length: Choice of 7 or 8 bits * Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) * Detection of framing, parity, and overrun errors, and breaks, during reception * Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used) Clocked Synchronous Mode * Transfer format: Fixed 8-bit data * Detection of overrun errors during reception * Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a serial clock is output off-chip When external clock is selected: The on-chip baud rate generator is not used, and the SCI operates on the input serial clock 392 Table 13.8 SMR Settings and Serial Transfer Format Selection SMR Settings Bit 7 C/A 0 Bit 6 CHR 0 Bit 2 MP 0 Bit 5 PE 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 0 1 -- -- 1 -- -- 1 -- -- -- 0 1 0 1 -- Clocked 8-bit data synchronous mode No Asynchronous mode (multiprocessor format) 8-bit data Yes No Yes 7-bit data No Mode Asynchronous mode Yes SCI Transfer Format Multiprocessor Bit No Data Length 8-bit data Parity Bit No Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 7-bit data 1 bit 2 bits None Table 13.9 SMR and SCR Settings and SCI Clock Source Selection SMR Bit 7 C/A 0 SCR Setting Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 0 1 1 0 0 1 1 0 1 Clocked synInternal chronous mode External Mode Asynchronous mode Clock Source Internal SCI Transmit/Receive Clock SCK Pin Function SCI does not use SCK pin Outputs clock with same frequency as bit rate External Inputs clock with frequency of 16 times the bit rate Outputs serial clock Inputs serial clock 393 13.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 13.2 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally stop bits (high level). In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 Parity bit 1 bit, or none 1 1 1 Stop bit Transmit/receive data 7 or 8 bits 1 or 2 bits One unit of transfer data (character or frame) Figure 13.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) 394 Data Transfer Format: Table 13.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. Table 13.10 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 -- -- -- -- MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S Serial Transfer Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data STOP S STOP STOP S P STOP S P STOP STOP S S STOP STOP S P STOP S P STOP STOP S MPB STOP S MPB STOP STOP S MPB STOP S MPB STOP STOP Legend S : Start bit STOP : Stop bit P : Parity bit MPB : Multiprocessor bit 395 Clock: Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 13.9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 13.3. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 13.3 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Data Transfer Operations: * SCI initialization (asynchronous mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain. 396 Figure 13.4 shows a sample SCI initialization flowchart. Start initialization Clear TE and RE bits in SCR to 0 [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [4] Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits Figure 13.4 Sample SCI Initialization Flowchart 397 * Serial data transmission (asynchronous mode) Figure 13.5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. Initialization Start transmission [1] Read TDRE flag in SSR [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and date is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. No TDRE=1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND= 1 Yes No Break output? Yes Clear DR to 0 and set DDR to 1 [4] Clear TE bit in SCR to 0 Figure 13.5 Sample Serial Transmission Flowchart 398 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. A format in which neither a parity bit nor a multiprocessor bit is output can also be selected. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. 399 Figure 13.6 shows an example of the operation for transmission in asynchronous mode. 1 Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and request generated TDRE flag cleared to 0 in TXI interrupt service routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 13.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) 400 * Serial data reception (asynchronous mode) Figure 13.7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Initialization Start reception [1] [2] [3] Receive error processing and break detection: Read ORER, PER, and If a receive error occurs, read the [2] FER flags in SSR ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error Yes processing, ensure that the PERFERORER= 1 ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot No Error processing be resumed if any of these flags (Continued on next page) are set to 1. In the case of a framing error, a break can be detected by reading the value of [4] Read RDRF flag in SSR the input port corresponding to the RxD pin. No RDRF= 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] SCI status check and receive data read : Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] No All data received? Yes Clear RE bit in SCR to 0 [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. The RDRF flag is cleared automatically when DTC is activated by an RXI interrupt and the RDR value is read. Figure 13.7 Sample Serial Reception Data Flowchart 401 [3] Error processing No ORER= 1 Yes Overrun error processing No FER= 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 No PER= 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 13.7 Sample Serial Reception Data Flowchart (cont) 402 In serial reception, the SCI operates as described below. [1] The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. [a] Parity check: The SCI checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the O/E bit in SMR. [b] Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. [c] Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from RSR to RDR. If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error* is detected in the error check, the operation is as shown in table 13.11. Note: * Subsequent receive operations cannot be performed when a receive error has occurred. Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0. [4] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive error interrupt (ERI) request is generated. 403 Table 13.11 Receive Errors and Conditions for Occurrence Receive Error Overrun error Abbreviation ORER Occurrence Condition Data Transfer When the next data reception is Receive data is not completed while the RDRF flag transferred from RSR to in SSR is set to 1 RDR. When the stop bit is 0 Receive data is transferred from RSR to RDR. Framing error Parity error FER PER When the received data differs Receive data is transferred from the parity (even or odd) set from RSR to RDR. in SMR Figure 13.8 shows an example of the operation for reception in asynchronous mode. 1 Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ERI interrupt request generated by framing error 1 frame Figure 13.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) 404 13.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing transmission lines. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station , and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips the data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this way, data communication is carried out among a number of processors. Figure 13.9 shows an example of inter-processor communication using the multiprocessor format. Data Transfer Format: There are four data transfer formats. When the multiprocessor format is specified, the parity bit specification is invalid. For details, see table 13.10. Clock: See the section on asynchronous mode. 405 Transmitting station Serial transmission line Receiving station A (ID= 01) Serial data Receiving station B (ID= 02) Receiving station C (ID= 03) Receiving station D (ID= 04) H'01 (MPB= 1) ID transmission cycle= receiving station specification H'AA (MPB= 0) Data transmission cycle= Data transmission to receiving station specified by ID Legend MPB: Multiprocessor bit Figure 13.9 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Data Transfer Operations: * Multiprocessor serial data transmission Figure 13.10 shows a sample flowchart for multiprocessor serial data transmission. The following procedure should be used for multiprocessor serial data transmission. 406 Initialization Start transmission [1] [1] SCI initialization: Read TDRE flag in SSR [2] The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. No TDRE= 1 Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No TEND= 1 Yes No Break output? Yes [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is [3] possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to [4] 1, clear DR to 0, then clear the TE bit in SCR to 0. Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 Figure 13.10 Sample Multiprocessor Serial Transmission Flowchart 407 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Multiprocessor bit One multiprocessor bit (MPBT value) is output. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a transmission end interrupt (TEI) request is generated. 408 Figure 13.11 shows an example of SCI operation for transmission using the multiprocessor format. Multiprocessor Stop bit bit D7 0/1 1 1 Start bit 0 D0 D1 Data Start bit 0 D0 D1 Data D7 Multiproces- Stop 1 sor bit bit 0/1 1 Idle state (mark state) TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 13.11 Example of SCI Operation in Transmission (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) * Multiprocessor serial data reception Figure 13.12 shows a sample flowchart for multiprocessor serial reception. The following procedure should be used for multiprocessor serial data reception. 409 Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. Read MPIE bit in SCR Read ORER and FER flags in SSR [2] Yes FERORER= 1 No Read RDRF flag in SSR No RDRF= 1 Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR Yes FERORER= 1 No Read RDRF flag in SSR [4] No RDRF= 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error processing (Continued on next page) Figure 13.12 Sample Multiprocessor Serial Reception Flowchart 410 [5] Error processing No ORER= 1 Yes Overrun error processing No FER= 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 13.12 Sample Multiprocessor Serial Reception Flowchart (cont) 411 Figure 13.13 shows an example of SCI operation for multiprocessor format reception. Multiprocessor Stop bit bit 1 1 Multiprocessor Stop bit bit 0 1 Start bit 0 D0 D1 Data (ID1) D7 Start bit 0 D0 D1 Data (Data1) D7 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ID1 If not this station's ID, RXI interrupt request is MPIE bit is set to 1 not generated, and RDR again retains its state (a) Data does not match station's ID Multiprocessor Stop bit bit 1 1 Multiprocessor Stop bit bit 0 1 Start bit 0 D0 D1 Data (ID2) D7 Start bit 0 D0 Data (Data2) D1 D7 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ID2 Matches this station's ID, so reception continues, and data is received in RXI interrupt service routine Data2 MPIE bit set to 1 again (b) Data matches station's ID Figure 13.13 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) 412 13.3.4 Operation in Clocked Synchronous Mode In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 13.14 shows the general format for clocked synchronous serial communication. One unit of transfer data (character or frame) * Serial clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care * Figure 13.14 Data Format in Synchronous Communication In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial clock. In clocked serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the transmission line holds the MSB state. In clocked synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock. Data Transfer Format: A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock: Either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 13.9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. 413 Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When only receive operations are performed, however, the serial clock is output until an overrun error occurs or the RE bit is cleared to 0. If you want to perform receive operations in units of one character, you should select an external clock as the clock source. Data Transfer Operations: * SCI initialization (clocked synchronous mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. Figure 13.15 shows a sample SCI initialization flowchart. Start initialization [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. [2] Set the data transfer format in SMR and SCMR. Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) Set data transfer format in SMR and SCMR Set value in BRR Wait [1] [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 13.15 Sample SCI Initialization Flowchart 414 * Serial data transmission (clocked synchronous mode) Figure 13.16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. Initialization Start transmission [1] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Read TDRE flag in SSR [2] No TDRE= 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND= 1 Yes Clear TE bit in SCR to 0 Figure 13.16 Sample Serial Transmission Flowchart 415 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been specified, data is output synchronized with the input clock. The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with the MSB (bit 7). [3] The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the TxD pin maintains its state. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. [4] After completion of serial transmission, the SCK pin is fixed. Figure 13.17 shows an example of SCI operation in transmission. Transfer direction Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated TXI interrupt Data written to TDR request generated and TDRE flag cleared to 0 in TXI interrupt service routine 1 frame TEI interrupt request generated Figure 13.17 Example of SCI Operation in Transmission 416 * Serial data reception (clocked synchronous mode) Figure 13.18 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to clocked synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible. 417 Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Read ORER flag in SSR Yes ORER= 1 No [2] [3] Error processing (Continued below) [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. The RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read. Read RDRF flag in SSR [4] No RDRF= 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 Error processing Overrun error processing Clear ORER flag in SSR to 0 Figure 13.18 Sample Serial Reception Flowchart 418 In serial reception, the SCI operates as described below. [1] The SCI performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error is detected in the error check, the operation is as shown in table 13.11. Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. [3] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive error interrupt (ERI) request is generated. Figure 13.19 shows an example of SCI operation in reception. Serial clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 13.19 Example of SCI Operation in Reception * Simultaneous serial data transmission and reception (clocked synchronous mode) Figure 13.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. 419 Initialization Start transmission/reception [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR No TDRE= 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error processing: Read ORER flag in SSR Yes [3] Error processing ORER= 1 No If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Read RDRF flag in SSR No RDRF= 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read. No All data received? Yes [5] Clear TE and RE bits in SCR to 0 Figure 13.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations 420 13.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 13.12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of interrupt request is sent to the interrupt controller independently. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is performed by the DTC. The DTC cannot be activated by a TEI interrupt request. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC. The DTC cannot be activated by an ERI interrupt request. 421 Table 13.12 SCI Interrupt Sources Channel 0 Interrupt Source ERI RXI TXI TEI 1 ERI RXI TXI TEI 3 ERI RXI TXI TEI Description Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmittion end (TEND) DTC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Low Priority* High Note: * This table shows the initial state immediately after a reset. Relative priorities among channels can be changed by means of the interrupt controller. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt may have priority for acceptance, with the result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be accepted in this case. 422 13.5 Usage Notes The following points should be noted when using the SCI. Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to TDR. Operation when Multiple Receive Errors Occur Simultaneously If a number of receive errors occur at the same time, the state of the status flags in SSR is as shown in table 13.13. If there is an overrun error, data is not transferred from RSR to RDR, and the receive data is lost. Table 13.13 State of SSR Status Flags and Transfer of Receive Data SSR Status Flags RDRF 1 0 0 1 1 0 1 ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Transfer RSR to RDR X O O X X O X Receive Error Status Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error O: Receive data is transferred from RSR to RDR. X: Receive data is not transferred from RSR to RDR. Break Detection and Processing (Asynchronous Mode Only): When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 423 Sending a Break (Asynchronous Mode Only): The TxD pin has a dual function as an I/O port whose direction (input or output) is determined by DR and DDR. This can be used to send a break. Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced by the value of DR (the pin does not function as the TxD pin until the TE bit is set to 1). Consequently, DDR and DR for the port corresponding to the TxD pin are first set to 1. To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only): Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Receive Data Sampling Timing and Reception Margin in Asynchronous Mode: In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock. This is illustrated in figure 13.21. 16 clocks 8 clocks 0 Internal basic clock 7 15 0 7 15 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode 424 Thus the reception margin in asynchronous mode is given by formula (1) below. M = | (0.5 - 1 2N ) - (L - 0.5) F - | D - 0.5 | N (1 + F) | x 100% ... Formula (1) Where M N D L F : Reception margin (%) : Ratio of bit rate to clock (N = 16) : Clock duty (D = 0 to 1.0) : Frame length (L = 9 to 12) : Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by formula (2) below. When D = 0.5 and F = 0, M = (0.5 - = 46.875% 1 2 x 16 ) x 100% ... Formula (2) However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. Restrictions on Use of DTC * When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 o clock cycles after TDR is updated by the DTC. Misoperation may occur if the transmit clock is input within 4 o clocks after TDR is updated. (Figure 13.22) * When RDR is read by the DTC, be sure to set the activation source to the relevant SCI reception end interrupt (RXI). 425 SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When operating on an external clock, set t >4 clocks. Figure 13.22 Example of Clocked Synchronous Transmission by DTC Operation in Case of Mode Transition * Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. TSR, TDR, and SSR are reset. The output pin states in module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and becomes high-level output after the relevant mode is cleared. If a transition is made during transmission, the data being transmitted will be undefined. When transmitting without changing the transmit mode after the relevant mode is cleared, transmission can be started by setting TE to 1 again, and performing the following sequence: SSR read TDR write TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode, the procedure must be started again from initialization. Figure 13.23 shows a sample flowchart for mode transition during transmission. Port pin states are shown in figures 13.24 and 13.25. Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a transition from transmission by DTC transfer to module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. To perform transmission with the DTC after the relevant mode is cleared, setting TE and TIE to 1 will set the TXI flag and start DTC transmission. 426 * Reception Receive operation should be stopped (by clearing RE to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. RSR, RDR, and SSR are reset. If a transition is made without stopping operation, the data being received will be invalid. To continue receiving without changing the reception mode after the relevant mode is cleared, set RE to 1 before starting reception. To receive with a different receive mode, the procedure must be started again from initialization. Figure 13.26 shows a sample flowchart for mode transition during reception. All data transmitted? Yes Read TEND flag in SSR No [1] TEND = 1 Yes TE= 0 [2] No [1] Data being transmitted is interrupted. After exiting software standby mode, etc., normal CPU transmission is possible by setting TE to 1, reading SSR, writing TDR, and clearing TDRE to 0, but note that if the DTC has been activated, the remaining data in DTCRAM will be transmitted when TE and TIE are set to 1. [2] If TIE and TEIE are set to 1, clear them to 0 in the same way. Transition to software standby mode, etc. Exit from software standby mode, etc. Change operating mode? Yes Initialization [3] [3] Includes module stop mode, watch mode, subactive mode, and subsleep mode. No TE= 1 Figure 13.23 Sample Flowchart for Mode Transition during Transmission 427 Start of transmission End of transmission Transition to software standby Exit from software standby TE bit SCK output pin Port input/output TxD output pin Port input/output Port High output Start SCI TxD output Stop Port input/output Port High output SCI TxD output Figure 13.24 Asynchronous Transmission Using Internal Clock Transition to software standby Exit from software standby Start of transmission End of transmission TE bit SCK output pin Port input/output TxD output pin Port input/output Port Marking output SCI TxD output Last TxD bit held Port input/output Port High output* SCI TxD output Note: * Initialized by software standby. Figure 13.25 Synchronous Transmission Using Internal Clock 428 RDRF= 1 Yes Read receive data in RDR RE= 0 Transition to software standby mode, etc. Exit from software standby mode, etc. Change operating mode? Yes Initialization [2] [2] Includes module stop mode, watch mode, subactive mode, and subsleep mode. No RE= 1 Figure 13.26 Sample Flowchart for Mode Transition during Reception 429 Switching from SCK Pin Function to Port Pin Function: * Problem in Operation: When switching the SCK pin function to the output port function (highlevel output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. End of serial data transmission 2. TE bit = 0 3. C/A bit = 0 ... switchover to port output 4. Occurrence of low-level output (see figure 13.27) Half-cycle low-level output SCK/port 1. End of transmission Data TE C/A CKE1 CKE0 Bit 6 Bit 7 2.TE= 0 4. Low-level output 3.C/A= 0 Figure 13.27 Operation when Switching from SCK Pin Function to Port Pin Function 430 * Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown. 1. End of serial data transmission 2. TE bit = 0 3. CKE1 bit = 1 4. C/A bit = 0 ... switchover to port output 5. CKE1 bit = 0 High-level output SCK/port 1. End of transmission Data TE C/A 3.CKE1= 1 CKE1 CKE0 5.CKE1= 0 Bit 6 Bit 7 2.TE= 0 4.C/A= 0 Figure 13.28 Operation when Switching from SCK Pin Function to Port Pin Function (Example of Preventing Low-Level Output) SCI3: SCI3 is dedicated for the FLEXTM decoder II interface, and cannot be connected with LSIexternal equipment. * In SCI3 that is internal FLEXTM decoder II interface, set to 1 the P77DDR and P75DDR bit of P7DDR (Port 7 Data Direction Register) before set the CKE1, CKE0, and TE bit of SCR3. 431 432 Section 14 FLEXTM Roaming Decoder II The contents of this section apply to the FLEXTM Roaming Decoder. Note that underlining in the text indicates differences in specification from the FLEXTM Non-Roaming Decoder. 14.1 Overview Its primary function is to process information received and demodulated from a FLEX radio paging channel, select messages addressed to the paging device and communicate the message information to the host. The FLEXTM decoder II also operates the paging receiver in an efficient power consumption mode and enables the host to operate in a low power mode when monitoring a single channel for message information. 14.1.1 * * * * * * * * * * * * * * * * * * * Features FLEXTM paging protocol decoder 16 programmable user address words 16 fixed temporary addresses 16 operator messaging addresses 1600, 3200, and 6400 bits per second decoding Any-phase or single-phase decoding Uses standard Serial Peripheral Interface (SPI) in slave mode Allows low current STOP mode operation of host processor Highly programmable receiver control Real time clock time base FLEX fragmentation and group messaging support Real time clock over-the-air update support Compatible with synthesized receivers SSID and NID Roaming support Low Battery Indication (External detector) Backward compatible to the standard and roaming FLEXTM decoders Internal demodulator and data slicer Improved battery savings via partial correlation and intermittent receiver clock Full support for revision 1.9 of the FLEX protocol Additional Support: FLEX System Software from Motorola is a family of software components for building world-class products incorporating messaging capabilities. FLEXstackTM Software is specifically designed to support the FLEXTM Roaming Decoder II IC. FLEXstack Software runs on a product's host processor and takes care of communicating with the FLEXTM decoder II, 433 acquiring the proper FLEX channel, and fully interpreting the code words that are passed to the host from the FLEXTM decoder II. Additional Information: Additional Information on the FLEXTM protocol decoder chip set and FLEXstackTM software can be found at the following website: http://www.hitachi.co.jp/Sicd/English/Products/micom/stack/stack.html. 14.1.2 System Block Diagram Synthesizer Programming Control Receiver Receiver Control LSI S0/IFIN User Interface 38.4 or 40 kHz clock Low Battery Detector LOBAT 160 kHz Oscillator Figure 14.1 Example Block Diagram Using Internal Demodulator When configured to use the internal demodulator, the FLEXTM decoder II connects to a receiver capable of generating a limited (i.e. 1-bit digitized) 455 kHz or 140 kHz IF signal. In this mode, the FLEXTM decoder II has 7 receiver control lines used for warming up and shutting down a receiver in stages. The FLEXTM decoder II has the ability to detect a low battery signal during the receiver control sequences. It interfaces to a host MCU through a standard SPI. It has a 1 minute timer that offers low power support for a time of day function on the host. When using the internal demodulator, the oscillator frequency (or external clock) must be 160 kHz. The CLKOUT signal can be programmed to be either a 38.4 kHz signal created by fractionally dividing the oscillator clock, or a 40 kHz signal creating by dividing the oscillator clock by 4. 434 Synthesizer Programming Control Receiver Audio Receiver Control LSI EXTS1 User Interface 38.4 clock Audio to Digital Convertor EXTS0 76.8 kHz Oscillator Low Battery Detector LOBAT Figure 14.2 Example Block Diagram Using External Demodulator The FLEXTM decoder II can also be configured to connect to a receiver capable of converting a 4 level audio signal into a 2 bit digital signal. In this mode, the FLEXTM decoder II has 8 receiver control lines used for warming up and shutting down a receiver in stages. It also includes configuration settings for the two post detection filter bandwidths required to decode the two symbol rates of the FLEX signal. Also when using an external demodulator, the oscillator (or external clock) must be 76.8 kHz and the CLKOUT signal (when enabled) is 38.4 kHz clock output capable of driving other devices. 435 14.1.3 Functional Block Diagram S1-S7 7 S1-S7 S0 Receiver Control S0/IFIN IFIN Demodulator & Data Slicer Internal Control Unit EXTS0 EXTS1 SYMCLK Symbol Sync Noise Detector oDEC 76.8 kHz or 160 kHz Oscillator Sync Correlator TESTD External Control Unit RESET LOBAT CLKOUT Clock Generator De-interleaver Error Corrector Control/Status Registers Local Message Filter READY SPI Buffer SPI SPI Address Comparator/ Correlator 4 Figure 14.3 Block Diagram 436 14.2 SPI Packets All data communicated between the FLEXTM decoder II and the host MCU is transmitted on the SPI in 32-bit packets. Each packet consists of an 8-bit ID followed by 24 bits of information. The FLEXTM decoder II uses the SPI bus in full duplex mode. In other words, whenever a packet communication occurs, the data in both directions is valid packet data. The SPI interface consists of a READY pin and four SPI pins (SS, SCK, MOSI, and MISO).The SS is used as a chip select for the FLEXTM decoder II. The SCK is a clock supplied by the host MCU. The data from the host is transmitted on the MOSI line. The data from the FLEXTM decoder II is transmitted on the MISO line. Timing requirements for SPI communication are specified in 14.6.1, SPI Timing. 14.2.1 Packet Communication Initiated by the Host Refer to figure 14.4. When the host sends a packet to the FLEXTM decoder II, it performs the following steps: 1. 2. 3. 4. 5. Select the FLEXTM decoder II by driving the SS pin low. Wait for the FLEXTM decoder II to drive the READY pin low. Send the 32-bit packet. De-select the FLEXTM decoder II by driving the SS pin high. Repeat steps 1 through 4 for each additional packet. SS READY SCK MOSI MISO 1 2 3 D31 D31 4 D1 D0 D1 D0 D31 D31 D1 D0 D1 D0 D31 D31 D1 D0 D1 D0 High impedance state Figure 14.4 Typical Multiple Packet Communications Initiated by the Host When the host sends a packet, it will also receive a valid packet from the FLEXTM decoder II. If the FLEXTM decoder II is enabled (see 14.3.1, Checksum Packet for a definition of enabled) and has no other packets waiting to be sent, the FLEXTM decoder II will send a status packet. 437 The host must transition the SS pin from high to low to begin each 32-bit packet. The FLEXTM decoder II must see a negative transition on the SS pin in order for the host to initiate each packet communication. 14.2.2 Packet Communication Initiated by the FLEXTM decoder II Refer to figure 14.5.When the FLEXTM decoder II has a packet for the host to read, the following occurs: 1. The FLEXTM decoder II drives the READY pin low. 2. If the FLEXTM decoder II is not already selected, the host selects the FLEXTM decoder II by driving the SS pin low. 3. The host receives (and sends) a 32-bit packet. 4. The host de-selects the FLEXTM decoder II by driving the SS pin high (optional). SS READY SCK MOSI MISO 1 3 D31 D31 D1 D0 D1 D0 D31 D31 D1 D0 D1 D0 D31 D31 D1 D0 D1 D0 2 4 High impedance state Figure 14.5 Typical Multiple Packet Communications Initiated by the FLEXTM decoder II When the host is reading a packet from the FLEXTM decoder II, it must send a valid packet to the FLEXTM decoder II. If the host has no data to send, it is suggested that the host send a Checksum Packet with all of the data bits set to 0 in order to avoid disabling the FLEXTM decoder II. See 14.3.1, Checksum Packet for more details on enabling and disabling the FLEXTM decoder II. The following figure illustrates that it is not necessary to de-select the FLEXTM decoder II between packets when the packets are initiated by the FLEXTM decoder II. 438 SS READY SCK MOSI MISO D31 D31 D1 D0 D1 D0 D31 D31 D1 D0 D1 D0 D31 D31 D1 D0 D1 D0 High impedance state Figure 14.6 Multiple Packet Communications Initiated by the FLEXTM decoder II with No De-select 439 14.2.3 Host-to-Decoder Packet Map The upper 8 bits of a packet comprise the packet ID. The following table describes the packet ID's for all of the packets that can be sent to the FLEXTM decoder II from the host. Table 14.1 Host-to-Decoder Packet ID Map Packet ID (Hexadecimal) 00 01 02 03 04 05 06 07 - 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C - 1F 20 21 22 23 24 440 Packet Type Checksum Configuration Control All Frame Mode Operator Message Address Enables Roaming Control Packet Timing Control Packet Reserved (Host should never send) Receiver Line Control Receiver Control Configuration (Off Setting) Receiver Control Configuration (Warm Up 1 Setting) Receiver Control Configuration (Warm Up 2 Setting) Receiver Control Configuration (Warm Up 3 Setting) Receiver Control Configuration (Warm Up 4 Setting) Receiver Control Configuration (Warm Up 5 Setting) Receiver Control Configuration (3200sps Sync Setting) Receiver Control Configuration (1600sps Sync Setting) Receiver Control Configuration (3200sps Data Setting) Receiver Control Configuration (1600sps Data Setting) Receiver Control Configuration (Shut Down 1 Setting) Receiver Control Configuration (Shut Down 2 Setting) Special (Ignored by FLEXTM decoder II) Frame Assignment (Frames 112 through 127) Frame Assignment (Frames 96 through 111) Frame Assignment (Frames 80 through 95) Frame Assignment (Frames 64 through 79) Frame Assignment (Frames 48 through 63) Packet ID (Hexadecimal) 25 26 27 28 - 77 78 79 - 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 - FF Packet Type Frame Assignment (Frames 32 through 47) Frame Assignment (Frames 16 through 31) Frame Assignment (Frames 0 through 15) Reserved (Host should never send) User Address Enable Reserved (Host should never send) User Address Assignment (User address 0) User Address Assignment (User address 1) User Address Assignment (User address 2) User Address Assignment (User address 3) User Address Assignment (User address 4) User Address Assignment (User address 5) User Address Assignment (User address 6) User Address Assignment (User address 7) User Address Assignment (User address 8) User Address Assignment (User address 9) User Address Assignment (User address 10) User Address Assignment (User address 11) User Address Assignment (User address 12) User Address Assignment (User address 13) User Address Assignment (User address 14) User Address Assignment (User address 15) Reserved (Host should never send) 441 14.2.4 Decoder-to-Host Packet Map The following table describes the packet ID's for all of the packets that can be sent to the host from the FLEXTM decoder II. Table 14.2 Decoder-to-Host Packet ID Map Packet ID (Hexadecimal) 00 01 02- 57 58 - 5F 60 61 - 7D 7E 7F 80 - FE FF Packet Type Block Information Word Address Vector or Message (ID is word number in frame) Reserved Roaming Status Packet Reserved Receiver Shutdown Status Reserved Part ID 14.3 Host-to-Decoder Packet Descriptions The following sections describe the packets of information sent from the host to the FLEXTM decoder II. In all cases the packets should be sent MSB first (bit 7 of byte 3 = bit 31 of the packet = MSB). 14.3.1 Checksum Packet The Checksum Packet is used to insure proper communication between the host and the FLEXTM decoder II. The FLEXTM decoder II exclusive-or's the 24 data bits of every packet it receives (except the Checksum Packet and the special packet ID's 1C through 1F hexadecimal) with an internal checksum register. Upon reset and whenever the host writes a packet to the FLEXTM decoder II, the FLEXTM decoder II is disabled from sending any information to the host processor until the host processor sends a Checksum Packet with the proper checksum value (CV) to the FLEXTM decoder II. When the FLEXTM decoder II is disabled in this way, it prompts the host to read the Part ID Packet. Note that all other operation continues normally when the FLEXTM decoder II is "disabled". Disabled only implies that data cannot be read, all other internal operations continue to function. When the FLEXTM decoder II is reset, it is disabled and the internal checksum register is initialized to the 24 bit part ID defined in the Part ID Packet. See 14.4.8, Part ID Packet for a 442 description of the Part ID. Every time a packet other than the Checksum Packet and the special packets 1C through 1F is sent to the decoder IC, the value sent in the 24 information bits is exclusive-or'ed with the internal checksum register, the result is stored back to the checksum register, and the FLEXTM decoder II is disabled. If a Checksum Packet is sent and the CV bits match the bits in the checksum register, the FLEXTM decoder II is enabled. If a Checksum Packet is sent when the FLEXTM decoder II is already enabled, the packet is ignored by the FLEXTM decoder II. If a packet other than the Checksum Packet is sent when the FLEXTM decoder II is enabled, the decoder IC will be disabled until a Checksum Packet is sent with the correct CV bits. When the host reads a packet out of the FLEXTM decoder II but has no data to send, the Checksum Packet should be sent so the FLEXTM decoder II will not be disabled. The data in the Checksum Packet could be a null packet (32 bit stream of all zeros) since a Checksum Packet will not disable the FLEXTM decoder II. When the host re-configures the FLEXTM decoder II, the FLEXTM decoder II will be disabled from sending any packets other than the Part ID Packet until the FLEXTM decoder II is enabled with a Checksum Packet having the proper data. The ID of the Checksum Packet is 0. Table 14.3 Checksum Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 CV 23 CV 15 CV 7 Bit 6 0 CV 22 CV 14 CV 6 Bit 5 0 CV 21 CV 13 CV5 Bit 4 0 CV 20 CV 12 CV 4 Bit 3 0 CV 19 CV 11 CV 3 Bit 2 0 CV 18 CV 10 CV 2 Bit 1 0 CV 17 CV 9 CV 1 Bit 0 0 CV 16 CV 8 CV 0 CV: Checksum Value. 443 RESET Decoder disables itself Decoder initializes checksum register to Part ID value Decoder initiates Part ID Packet Decoder waits for SPI packet from host Yes Checksum Packet? No Yes Decoder disables itself Decoder enabled? No Decoder sets checksum register to the XOR of the packet data bits with the checksum register bits No Packet data matches checksum register data? Yes Decoder enables itself Figure 14.7 FLEXTM decoder II Checksum Flow Chart 444 14.3.2 Configuration Packet The Configuration Packet defines a number of different configuration options for the FLEXTM decoder II. Proper operation is not guaranteed if these settings are changed when decoding is enabled (i.e. the ON bit in the Control Packet is set). The ID of the Configuration Packet is 1. Table 14.4 Configuration Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 0 SME Bit 6 0 DFC 0 MOT Bit 5 0 0 0 COD Bit 4 0 0 0 MTE Bit 3 0 0 0 LBP Bit 2 0 IDE PCE ICO Bit 1 0 OFD1 SP1 0 Bit 0 1 OFD0 SP0 0 DFC: Disable Fractional Clock. When this bit is set and IDE is set, the CLKOUT signal will generate a 40 kHz signal (o DEC divided by 4). When this bit is cleared and IDE is set, the CLKOUT signal will generate 38.4 kHz signal (oDEC fractionally divided by 25/6 see diagram below). This bit has no effect when IDE is cleared. (value after reset=0) oDEC CLKOUT w/ DFC=1 CLKOUT w/ DFC=0 IDE: Internal Demodulator Enable. When this bit is set, the internal demodulator is enabled and the clock frequency at oDEC is expected to be 160 kHz. When this bit is cleared, the internal demodulator is disabled and the clock frequency at oDEC is expected to be 76.8 kHz. (value after reset=0) OFD: Oscillator Frequency Difference. These bits describe the maximum difference in the frequency of the 76.8 kHz oscillator crystal with respect to the frequency of the transmitter. These limits should be the worst case difference in frequency due to all conditions including but not limited to aging, temperature, and manufacturing tolerance. Using a smaller frequency difference in this packet will result in lower power consumption due to higher receiver battery save ratios. Note that this value is not the absolute error of the oscillator frequency provided to the FLEXTM decoder II. The absolute error of the clock used by the FLEX transmitter must be taken into account. (e.g. If the transmitter tolerance is +/- 25 ppm and the oscillator tolerance is +/-140 ppm, 445 the oscillator frequency difference is +/- 165 ppm and OFD should be set to 0.)(value after reset = 0) OFD1 OFD0 0 0 1 1 0 1 0 1 Frequency Difference +/- 300 ppm +/- 150 ppm +/- 75 ppm +/- 0 ppm PCE: Partial Correlation Enable. When this bit is set, partial correlation of addresses is enabled. When partial correlation is enabled, the FLEXTM decoder II will shutdown the receiver before the end of the last FLEX block which contains addresses if it can determine that none of the addresses in that FLEX block will match any enabled address in the FLEXTM decoder II. When this bit is cleared, the receiver will be controlled as it was in previous versions of the FLEXTM decoder II. (value after reset=0) SP: Signal Polarity. These bits set the polarity of EXTS1 and EXTS0 input signals. (value after reset=0) The polarity of the EXTS0 and EXTS1 bits will be determined by the receiver design. Signal Polarity SP1 SP0 0 0 1 1 0 1 0 1 EXTS1 Normal Normal Inverted Inverted EXTS0 Normal Inverted Normal Inverted FSK Modulation @ SP = 0,0 + 4800 Hz +1600 Hz - 1600 Hz - 4800 Hz EXTS1 1 1 0 0 EXTS0 0 1 1 0 SME: Synchronous Mode Enable. When this bit is set, a Status Packet will be automatically sent whenever the SMU (synchronous mode update) bit in the Status Packet is set. The host can use the SM (synchronous mode) bit in the Status Packet as an in-range/out-of-range indication. (value after reset=0) MOT: Maximum Off Time. This bit has no effect if AST in the Timing Control Packet is nonzero. When AST=0 and MOT=0, asynchronous A-word searches will time-out in 4 minutes. When 446 AST=0 and MOT=1, asynchronous A-word searches will time-out in 1 minute. (value after reset=0) COD: Clock Output Disable. When this bit is clear, a 38.4 kHz or 40 kHz (depending on the values of IDE and DFC) signal will be output on the CLKOUT pin. When this bit is set, the CLKOUT pin will be driven low. Note that setting and clearing this bit can cause pulses on the CLKOUT pin that are less than one half the clock period. Also note that when the clock output is enabled and not set for intermittent operation (see ICO in this packet), the CLKOUT pin will always output the clock signal even when the FLEXTM decoder II is in reset (as long as the FLEXTM decoder II oscillator is seeing clocks). Further note that when the FLEXTM decoder II is used in internal demodulator mode (i.e. uses a 160 kHz oscillator), the CLKOUT pin will be 80 kHz from reset until the time the IDE bit is set. This is because the FLEXTM decoder II defaults to external demodulator mode at reset. (value after reset=0) MTE: Minute Timer Enable. When this bit is set, a Status Packet will be sent at one minute intervals with the MT (minute time-out) bit in the Status Packet set. When this bit is clear, the internal one-minute timer stops counting. The internal one-minute timer is reset when this bit is changed from 0 to 1 or when the MTC (minute timer clear) bit in the Control Packet is set. Note that the minute timer will not be accurate using a 160 kHz oscillator until the IDE bit is set. (value after reset=0) LBP: Low Battery Polarity. This bit defines the polarity of the FLEXTM decoder's LOBAT pin. The LB bit in the Status Packet is initialized to the inverse value of this bit when the FLEXTM decoder II is turned on (by setting the ON bit in the Control Packet). When the FLEXTM decoder II is turned on, the first low battery update in the Status Packet will be sent to the host when a low battery condition is detected on the LOBAT pin. Setting this bit means that a high on the LOBAT pin indicates a low voltage condition. (value after reset=0) ICO: Intermittent Clock Out. When this bit is clear and COD is clear, a 38.4 kHz or 40 kHz (depending on the values of IDE and DFC) signal will be output on the CLKOUT pin. When this bit is set and COD is clear, the clock will only be output on the CLKOUT pin while the receiver is not in the Off state. The clock will be output for a few cycles before the receiver transitions from the off state and for a few cycles after the receiver transitions to the off state (this is to insure that the receiver receives enough clocks to detect and process the changes to and from the Off state). The CLKOUT pin will be driven low when it is not driving a clock. Note that when the clock is automatically enabled and disabled (i.e. when ICO is set), the CLKOUT signal transitions will be clean (i.e. no pulses less than half the clock period) when it transitions between no clock and clocked output. This bit has no effect when COD is set. (value after reset=0) 447 14.3.3 Control Packet The Control Packet defines a number of different control bits for the FLEXTM decoder II. The ID of the Control Packet is 2. Table 14.5 Control Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 FF7 0 0 Bit 6 0 FF6 SPM SBI Bit 5 0 FF5 PS1 0 Bit 4 0 FF4 PS0 MTC Bit 3 0 FF3 0 0 Bit 2 0 FF2 0 0 Bit 1 1 FF1 0 EAE Bit 0 0 FF0 0 ON FF: Force Frame 0-7. These bits enable and disable forcing the FLEXTM decoder II to look in frames 0 through 7. When an FF bit is set, the FLEXTM decoder II will decode the corresponding frame. Unlike the AF bits in the Frame Assignment Packets, the system collapse of a FLEX system will not affect frames assigned using the FF bits (e.g. Where as setting AF0 to 1 when the system collapse is 5 will cause the decoder to decode frames 0, 32, 64, and 96, setting FF0 to 1 when the system collapse is 5 will only cause the decoder to decode frame 0.). This may be useful for acquiring transmitted time information or channel attributes (e.g. Local ID). (value after reset=0) SPM: Single Phase Mode. When this bit is set, the FLEXTM decoder II will decode only one phase of the transmitted data. When this bit is clear, the FLEXTM decoder II will decode all of the phases it receives. A change to this bit while the FLEXTM decoder II is on, will not take affect until the next block 0 of the next decoded frame. (value after reset=0) PS: Phase Select. When the SPM bit is set, these bits define what phase the FLEXTM decoder II should decode according to the following table. This value is determined by the service provider. A change to these bits while the FLEXTM decoder II is on, will not take affect until the next block 0 of a frame. (value after reset=0) PS Value PS1 0 0 1 1 PS0 0 1 0 1 Phase Decoded (based on FLEX Data Rate) 1600bps a a a a 3200bps a a c c 6400bps a b c d 448 SBI: Send Block Information words 2-4. When this bit is set, any errored or time related block information words 2-4 will be sent to the host. See 14.4.1, Block Information Word Packet for a description of the words sent. (value after reset=0) MTC: Minute Timer Clear. Setting this bit will cause the one minute timer to restart from 0. EAE: End of Addresses Enable. When this bit is set, the EA bit in the Status Packet will be set immediately after the FLEXTM decoder II decodes the last address word in the frame if any of the enabled FLEXTM decoder II addresses was detected in the frame. When this bit is cleared, the EA bit will never be set. ON: Turn On Decoder. Set if the FLEXTM decoder II should be decoding FLEX signals. Clear if signal processing should be off (very low power mode). If the ON bit is changed twice and the control packets making the changes are received within 2ms of each other, the FLEXTM decoder II may ignore the double change and stay in its original state (e.g. if it is turned off then on again within 2ms it may stay on and ignore the off pulse). Therefore it is recommended that the host insures a minimum of 2ms between changes in the ON bit. (value after reset=0) Note: Turning off the FLEXTM decoder II must be done using the following sequence. This sequence is performed automatically by the FLEXstack software version 1.2 and greater. 1. Turn off the FLEXTM decoder II by sending a Control Packer with the ON bit cleared. 2. Turn on the FLEXTM decoder II by sending a Control Packer with the ON bit set. 3. Turn off the FLEXTM decoder II by sending a Control Packer with the ON bit cleared. Timing between these steps is specified below and is measured from the positive edge of the last clock of one packet to the positive edge of the last clock of the next packet: * The minimum time between steps 1 and 2 is 2ms or the programmed shut down time, whichever is greater. The programmed shut down time is the sum of all the of the times programmed in the used Receiver Shut Down Settings Packets. * There is no maximum time between steps 1 and 2. * The minimum time between steps 2 and 3 is 2ms. * The maximum time between steps 2 and 3 is the programmed warm up time minus 2ms. The programmed warm up time is the sum of all the of the times programmed in the used Receiver Warm Up Settings Packets. 14.3.4 All Frame Mode Packet The All Frame Mode Packet is used to decrement temporary address enable counters by one, decrement the all frame mode counter by one, and/or enable or disable forcing all frame mode. All frame mode is enabled if any temporary address enable counter is non-zero, the all frame mode counter is non-zero, or the force all frame mode bit is set. If all frame mode is enabled, the FLEXTM decoder II will attempt to decode every frame and send a Status Packet with the EOF (end-of-frame) bit set at the end of every frame. Both the all frame mode counter and the 449 temporary address enable counters can only be incremented internally by the FLEXTM decoder II and can only be decremented by the host. The FLEXTM decoder II will increment a temporary address enable counter whenever a short instruction vector is received assigning the corresponding temporary address. See 14.5.4, Operation of a Temporary Address for details. The FLEXTM decoder II will increment the all frame mode counter whenever an alphanumeric, HEX / binary, or secure vector is received. When the host determines that a message associated with a temporary address, or a fragmented message has ended, then the appropriate temporary address counter or all frame mode counter should be decremented by writing an All Frame Mode Packet to the FLEXTM decoder II in order to exit the all frame mode, thereby improving battery life. See 14.5.3, Building a Fragmented Message for details. Neither the temporary address enable counters nor the all frame mode counter can be incremented past the value 127 (i.e. it will not roll-over) or decremented past the value 0. The temporary address enable counters and the all frame mode counter are initialized to 0 at reset and when the decoder is turned off. The ID of the All Frame Mode Packet is 3. Table 14.6 All Frame Mode Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 DAF DTA15 DTA7 Bit 6 0 FAF DTA 14 DTA 6 Bit 5 0 0 DTA 13 DTA 5 Bit 4 0 0 DTA12 DTA 4 Bit 3 0 0 DTA11 DTA 3 Bit 2 0 0 DTA10 DTA 2 Bit 1 1 0 DTA9 DTA 1 Bit 0 1 0 DTA 8 DTA 0 DAF: Decrement All Frame counter. Setting this bit decrements the all frame mode counter by one. If a packet is sent with this bit clear, the all frame mode counter is not affected. (value after reset =0) FAF: Force All Frame mode. Setting this bit forces the FLEXTM decoder II to enter all frame mode. If this bit is clear, the FLEXTM decoder II may or may not be in all frame mode depending on the status of the all frame mode counter and the temporary address enable counters. This may be useful in acquiring transmitted time information. (value after reset=0) DTA: Decrement Temporary Address enable counter. When a bit in this word is set, the corresponding temporary address enable counter is decremented by one. When a bit is cleared, the corresponding temporary address enable counter is not affected. When a temporary address enable counter reaches zero, the temporary address is disabled.(value after reset=0) 450 14.3.5 Operator Messaging Address Enable Packet The contents of this section apply to the FLEX Roaming Decoder. They are not applicable to the FLEX Non-Roaming Decoder. The operator messaging address enable packet is used to enable and disable the built-in FLEX operator messaging addresses. Enabling and disabling operator messaging addresses does not affect what frames the decoder IC decodes. To decode the proper frames, the host must modify the FF bits in the Control Packet or the AF bits in the Frame Assignment Packets. The ID of the operator messaging address enable packet is 4. Table 14.7 System Address Enable Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 OAE15 OAE 7 Bit 6 0 0 OAE 14 OAE 6 Bit 5 0 0 OAE 13 OAE 5 Bit 4 0 0 OAE 12 OAE 4 Bit 3 0 0 OAE 11 OAE 3 Bit 2 1 0 OAE 10 OAE 2 Bit 1 0 0 OAE 9 OAE 1 Bit 0 0 0 OAE 8 OAE 0 OAE: Operator messaging Address Enable. When a bit is set, the corresponding operator messaging address is enabled. When it is cleared, the corresponding operator messaging address is disabled. OAE0 through OAE 15 corresponds to the hexadecimal operator messaging address values of 1F7810 through 1F781F respectively. (value after reset=0) 14.3.6 Roaming Control Packet The contents of this section apply to the FLEX Roaming Decoder. They are not applicable to the FLEX Non-Roaming Decoder. The roaming control packet controls the features of the FLEXTM decoder II that allow implementation of a roaming device. The ID of the roaming control packet is 5. Table 14.8 Roaming Control Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 IRS RND 0 Bit 6 0 NBC ABI 0 Bit 5 0 MCM SAS MFC1 Bit 4 0 IS1 DAS MFC0 Bit 3 0 SDF 0 0 Bit 2 1 RSP 0 0 Bit 1 0 SND 0 MCO1 Bit 0 1 CND 0 MCO0 451 IRS: Ignore Re-synchronization Signal. When this bit is set, the FLEXTM decoder II will not go asynchronous when detecting an Ar or Ar signal during searches for A-words. It will merely report that the re-synchronization signal was received by setting RSR to 1 in the Roaming Status packet. This allows the host to decide what to do when the paging device is synchronous to more than one channel and only one channel is sending the re-synchronization signal. It also prevents the FLEXTM decoder II from losing synchronization when it detects the re-synchronization signal while the paging device is checking an unknown channel. This bit is set and cleared by the host. (value after reset=0) NBC: Network Bit Check. Setting this bit will enable reporting of the received network bit value (NBU and n) in the Roaming Status Packet. Setting this bit also makes the FLEXTM decoder II abandon a frame after the Frame Info word without synchronizing to the frame if the frame information word is uncorrectable or if the n bit in the frame information word is not set. If the FLEXTM decoder II was in synchronous mode when this occurred (probably due to synchronizing to a second channel), it will maintain synchronization to the original channel. If the FLEXTM decoder II was in asynchronous mode when this occurred, it will stay in asynchronous mode and end the A-word search. This is done to avoid synchronizing to a non-roaming channel when searching for roaming channels. This bit is set and cleared by the host. (value after reset=0) MCM: Manual Collapse Mode. When this bit is set, the FLEXTM decoder II behaves as if the system collapse was 7. The FLEXTM decoder II will not apply the received system collapse to the AF bits. When this bit is set, the received system collapse is reported to the host via SCU and RSC in the Roaming Status Packet. This is so the host can modify the AF bits based on the system collapse of the channel. This bit is set and cleared by the host. (value after reset=0) IS1:Invert EXTS1. Setting this bit inverts the expected polarity of the EXTS1 pin from the way it is configured by SP 1 in the Configuration Packet (e.g. if both IS1 and SP 1 are set, the polarity of the EXTS1 pin is untouched). This bit is intended to be changed when a change in a channel changes the polarity of the received signal. This bit is set and cleared by the host. This bit has the equivalent effect when using the internal demodulator. (value after reset=0) SDF: Stop Decoding Frame. Setting this bit causes the FLEXTM decoder II to stop decoding a frame without losing frame synchronization. This bit is set by the host, and cleared by the FLEXTM decoder II once it has been processed. The packet with the SDF bit set must be sent after receiving the status packet with EA bit set. It must be sent within 40ms of the end of block in which the FLEXTM decoder II set the EA bit. (value after reset=0) RSP: Receiver Shutdown Packet enable. When this bit is set, a Receiver Shutdown Packet will be sent whenever the receiver is shut down. The receiver shutdown packet informs the host that the receiver shutdown, and how long it will be before the FLEXTM decoder II will automatically warm the receiver back up. (value after reset=0) SND: Start Noise Detect. Setting this bit while the FLEXTM decoder II is battery saving will cause it to warm-up the receiver, run a noise detect, and report the result of the noise detect via NDR in 452 the Roaming Status Packet. This bit is set by the host, and cleared by the FLEXTM decoder II once it has been processed. If the time comes for the FLEXTM decoder II to warm up automatically or the SAS bit is set while an SND is being processed, the noise detect will be abandoned and the abandoned noise detect result (NDR = 01) will be sent in the Roaming Status Packet. (value after reset=0) CND: Continuous Noise Detect. Setting this bit will cause the FLEXTM decoder II to do continuous noise detects during the decoded block data of a frame. The results of the noise detect will only be reported if noise is detected (NDR = 11). Only one noise detected result (NDR=11) will be sent per block. If the FLEXTM decoder II has not completed a noise detect when it shuts down for the frame, that noise detect will be abandoned, but no abandon result (NDR=01) will be sent. This bit is set and cleared by the host. (value after reset=0) RND: Report Noise Detects. Setting this bit will cause the FLEXTM decoder II to report the results of the noise detects it does under normal asynchronous operation (when first turned on and when asynchronous). The results of the noise detect will be reported via NDR in the Roaming Status Packet. This bit is set and cleared by the host. (value after reset=0) ABI: All Block Information words. When this bit is set, the FLEXTM decoder II will send all received Block Information words 2-4 to the host. Note: Setting the SBI bit in the Control Packet only enables errored and real time clock related block info words. (value after reset=0) SAS: Start A-word Search. Setting this bit while in asynchronous battery save mode will cause the FLEXTM decoder II to warm-up the receiver and run an A-word search. If, during the A-word search, the FLEXTM decoder II finds sufficient FLEX signal, it will enter synchronous mode and start decoding the frame. If the A-word search times-out without finding sufficient FLEX signal, it will battery save and continue doing periodic noise detects. The time-out for the A-word searches is controlled by the AST bits in the Timing Control Packet and the MOT bit in the Configuration Packet. The A-word search takes priority over noise detects. Therefore, if the FLEXTM decoder II is performing an A-word search and the time comes to do automatic noise detect, the noise detect will not be performed. This bit is set by the host, and cleared by the FLEXTM decoder II once it has been acted on. (value after reset=0) DAS: Disable A-word Search. When this bit is set, an A-word search will not automatically occur after a noise detect in asynchronous mode finds FLEX signal. This includes automatic noise detects and noise detects initiated by the host by setting SND. The FLEXTM decoder II will shut down the receiver after the noise detect completes regardless of the result. When this bit is cleared, A-word searches will occur after a noise detect finds signal in asynchronous mode. (value after reset=0) MFC: Missed Frame Control. These bits control the frames for which missing frame data (MS1, MFI, MS2, MBI, and MAW) is reported in the Roaming Status Packet. (value after reset=0) 453 MFC1 MFC0 0 0 1 1 0 1 0 1 Missing Frame Data Reported Never Only during frames 0 through 3 Only during frames 0 through 7 Always MCO: Maximum Carry On. The value of these bits sets the maximum carry on that the FLEXTM decoder II will follow. For example, if the FLEXTM decoder II receives a carry on of 3 over the air and MCO is set to 1, the FLEXTM decoder II will only carry on for one frame. (value after reset=3) 14.3.7 Timing Control Packet The contents of this section apply to the FLEX Roaming Decoder. They are not applicable to the FLEX Non-Roaming Decoder. The timing control packet gives the host control of the timing used when the FLEXTM decoder II is in asynchronous mode. The packet ID for the timing control packet is 6. Table 14.9 Timing Control Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 AST 7 ABT 7 Bit 6 0 0 AST 6 ABT 6 Bit 5 0 0 AST 5 ABT 5 Bit 4 0 0 AST 4 ABT 4 Bit 3 1 0 AST 3 ABT 3 Bit 2 1 0 AST 2 ABT 2 Bit 1 1 0 AST 1 ABT 1 Bit 0 1 0 AST 0 ABT 0 AST: A-word Search Time. The value of these bits sets the A-word search time for all asynchronous A-word searches in units of 80ms (e.g. value of 1 is 80ms, value of 2 is 160ms, etc.) If the value is 0, the FLEXTM decoder II defaults to the 1-minute (MOT=1) or 4-minute (MOT=0) A-word search time controlled by the MOT bit in the configuration packet. (Value after reset=0) ABT: Asynchronous Battery-save Time. The value of these bits sets the battery save time (time from the beginning of one automatic noise detect to the beginning of the next automatic noise detect) in asynchronous mode in units of 80ms (e.g. value of 1 is 80ms, value of 2 is 160ms, etc.) If the value is 0, the battery save time is set to the default value of 1.5 seconds. The minimum allowed ABT is 320ms, therefore values of 1, 2, 3, and 4 are invalid. (Value after reset=0) 454 14.3.8 Receiver Line Control Packet This packet gives the host control over the settings on the receiver control lines (S0-S7) in all modes except reset. In reset, the receiver control lines are in high impedance settings. The ID for the Receiver Line Control Packet is 15 (decimal). Table 14.10 Receiver Line Control Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 FRS 7 CLS 7 Bit 6 0 0 FRS 6 CLS 6 Bit 5 0 0 FRS 5 CLS 5 Bit 4 0 0 FRS 4 CLS 4 Bit 3 1 0 FRS 3 CLS 3 Bit 2 1 0 FRS 2 CLS 2 Bit 1 1 0 FRS 1 CLS 1 Bit 0 1 0 FRS 0 CLS 0 FRS: Force Receiver Setting. Setting a bit to one will cause the corresponding CLS bit in this packet to override the internal receiver control settings on the corresponding receiver control line (S0-S7). Clearing a bit gives control of the corresponding receiver control lines (S0-S7) back to the FLEXTM decoder II.(value after reset=0) CLS: Control Line Setting. If the corresponding FRS bit was set in this packet, these bits define what setting should be applied to the corresponding receiver control lines.(value after reset=0) 14.3.9 Receiver Control Configuration Packets These packets allow the host to configure what setting is applied to the receiver control lines S0S7, how long to apply the setting, and when to read the value of the LOBAT input pin. For a more detailed description of how the FLEXTM decoder II uses these settings see 14.5.1, Receiver Control. The FLEXTM decoder II defines 12 different receiver control settings. Proper operation is not guaranteed if these settings are changed when decoding is enabled (i.e. the ON bit in the Control Packet is set). The IDs for these packets range from 16 to 27 (decimal). 1. Receiver Off Setting Packet Table 14.11 Receiver Off Setting Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 CLS 7 ST 7 Bit 6 0 0 CLS 6 ST 6 Bit 5 0 0 CLS 5 ST 5 Bit 4 1 0 CLS 4 ST 4 Bit 3 0 LBC CLS 3 ST 3 Bit 2 0 0 CLS 2 ST 2 Bit 1 0 0 CLS 1 ST 1 Bit 0 0 0 CLS 0 ST 0 455 LBC: Low Battery Check. If this bit is set, the FLEXTM decoder II will check the status of the LOBAT port just before leaving this receiver state. (value after reset=0) CLS: Control Line Setting. This is the value to be output on the receiver control lines (S0-S7) for this receiver state. (value after reset=0) ST: Step Time. This is the time the FLEXTM decoder II is to keep the receiver off before applying the first warm up state's receiver control value to the receiver control lines. The setting is in steps of 625s. Valid values are 625s (ST=01) to 159.375ms (ST=FF in hexadecimal). (value after reset=625s) 2. Receiver Warm Up Setting Packets Table 14.12 Receiver Warm Up Setting Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 SE CLS 7 0 Bit 6 0 0 CLS 6 ST 6 Bit 5 0 0 CLS 5 ST 5 Bit 4 1 0 CLS 4 ST 4 Bit 3 0 LBC CLS 3 ST 3 Bit 2 s2 0 CLS 2 ST 2 Bit 1 s1 0 CLS 1 ST 1 Bit 0 s0 0 CLS 0 ST 0 s: Setting Number. Receiver control setting for which this packet's values are to be applied. The following truth table shows the names of each of the values for s that apply to this packet. s2 0 0 0 1 1 s1 0 1 1 0 0 s0 1 0 1 0 1 Setting Name Warm Up 1 Warm Up 2 Warm Up 3 Warm Up 4 Warm Up 5 SE: Step Enable. The receiver setting is enabled when the bit is set. If a step in the warm up sequence is disabled, the disabled step and all remaining steps will be skipped. (value after reset=0) LBC: Low Battery Check. If this bit is set, the FLEXTM decoder II will check the status of the LOBAT port just before leaving this receiver state. (value after reset=0) CLS: Control Line Setting. This is the value to be output on the receiver control lines (S0-S7) for this receiver state. (value after reset=0) 456 ST: Step Time. This is the time the FLEXTM decoder II is to wait before applying the next state's receiver control value to the receiver control lines. The setting is in steps of 625s. Valid values are 625s (ST=01) to 79.375ms (ST=7F in hexadecimal). (value after reset=625s) 3. 3200sps Sync Setting Packets Table 14.13 3200sps Sync Setting Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 CLS 7 0 Bit 6 0 0 CLS 6 ST 6 Bit 5 0 0 CLS 5 ST 5 Bit 4 1 0 CLS 4 ST 4 Bit 3 0 LBC CLS 3 ST 3 Bit 2 1 0 CLS 2 ST 2 Bit 1 1 0 CLS 1 ST 1 Bit 0 0 0 CLS 0 ST 0 LBC: Low Battery Check. If this bit is set, the FLEXTM decoder II will check the status of the LOBAT port just before leaving this receiver state. (value after reset=0) CLS: Control Line Setting. This is the value to be output on the receiver control lines (S0-S7) for this receiver state. (value after reset=0) ST: Step Time. This is the time the FLEXTM decoder II is to wait before expecting good signals on the EXTS1 and EXTS0 signals after warming up. The setting is in steps of 625s. Valid values are 625s (ST=01) to 79.375ms (ST=7F in hexadecimal). (value after reset=625s) 4. Receiver On Setting Packets Table 14.14 Receiver On Setting Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 CLS 7 0 Bit 6 0 0 CLS 6 0 Bit 5 0 0 CLS 5 0 Bit 4 1 0 CLS 4 0 Bit 3 s3 LBC CLS 3 0 Bit 2 s2 0 CLS 2 0 Bit 1 s1 0 CLS 1 0 Bit 0 s0 0 CLS 0 0 457 s: Setting Number. Receiver control setting for which this packet's values are to be applied. The following truth table shows the names of each of the values for s that apply to this packet. s3 s2 s1 s0 01 10 10 11 00 01 Setting Name 1600sps Sync 3200sps Data 1600sps Data LBC: Low Battery Check. If this bit is set, the FLEXTM decoder II will check the status of the LOBAT port just before leaving this receiver state. (value after reset=0) CLS: Control Line Setting. This is the value to be output on the receiver control lines (S0-S7) for this receiver state. (value after reset=0) 5. Receiver Shut Down Setting Packets Table 14.15 Receiver Shut Down Setting Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 SE CLS 7 0 Bit 6 0 0 CLS 6 0 Bit 5 0 0 CLS 5 ST 5 Bit 4 1 0 CLS 4 ST 4 Bit 3 1 LBC CLS 3 ST 3 Bit 2 0 0 CLS 2 ST 2 Bit 1 1 0 CLS 1 ST 1 Bit 0 s 0 CLS 0 ST 0 s: Setting Number. Receiver control setting for which this packet's values are to be applied. The following truth table shows the names of each of the values for s that apply to this packet. s 0 1 Setting Name Shut Down 1 Shut Down 2 SE: Step Enable. The receiver setting is enabled when the bit is set. If a step in the shut down sequence is disabled, all steps following the disabled step will be ignored. (value after reset=0) LBC: Low Battery Check. If this bit is set, the FLEXTM decoder II will check the status of the LOBAT port just before leaving this receiver state. (value after reset=0) CLS: Control Line Setting. This is the value to be output on the receiver control lines (S0-S7) for this receiver state. (value after reset=0) 458 ST: Step Time. This is the time the FLEXTM decoder II is to wait before applying the next state's receiver control value to the receiver control lines. The setting is in steps of 625s. Valid values are 625s (ST=01) to 39.375ms (ST=3F in hexadecimal). (value after reset=625s) 14.3.10 Frame Assignment Packets The FLEX protocol defines that each address of a FLEX pager is assigned a home frame and a battery cycle. The FLEXTM decoder II must be configured so that a frame that is assigned by one or more of the addresses' home frames and battery cycles has its corresponding configuration bit set. For example, if the FLEXTM decoder II has one enabled address and it is assigned to frame 3 with a battery cycle of 4, the AF bits for frames 3, 19, 35, 51, 67, 83, 99, and 115 should be set and the AF bits for all other frames should be cleared. When the FLEXTM decoder II is configured for manual collapse mode by setting the MCM bit in the Roaming Control Packet, the FLEXTM decoder II will not apply the received system collapse to the AF bits. The host should set the AF bits for all frames that should be decoded on all channels. For example, if frames 0 and 64 should be decoded on one channel and frames 4, 36, 68, and 100 should be decoded on another channel, all six of the corresponding AF bits should be set. The host can then change the receiver's carrier frequency after the FLEXTM decoder II decodes frames 0, 36, 64, and 100. There are 8 Frame Assignment Packets. The Packet IDs for these packets range from 32 to 39 (decimal). Table 14.16 Frame Assignment Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 AF 15 AF 7 Bit 6 0 0 AF 14 AF 6 Bit 5 1 0 AF 13 AF 5 Bit 4 0 0 AF 12 AF 4 Bit 3 0 0 AF 11 AF 3 Bit 2 f2 0 AF 10 AF 2 Bit 1 f1 0 AF 9 AF 1 Bit 0 f0 0 AF 8 AF 0 f: Frame range. This value determines which 16 frames correspond to the 16 AF bits in the packet according to the following table. At least one of these bits must be set when the FLEXTM decoder II is turned on by setting the ON bit in the control packet. (value after reset=0) 459 f2 f1 f0 00 00 01 01 10 10 11 11 0 1 0 1 0 1 0 1 AF15 Frame 127 Frame 111 Frame 95 Frame 79 Frame 63 Frame 47 Frame 31 Frame 15 AF0 Frame 112 Frame 96 Frame 80 Frame 64 Frame 48 Frame 32 Frame 16 Frame 0 AF: Assigned Frame. If a bit is set, the FLEXTM decoder II will consider the corresponding frame to be assigned via an address's home frame and pager collapse. (value after reset=0) 14.3.11 User Address Enable Packet The User Address Enable Packet is used to enable and disable the 16 user address words. Although the host is allowed to change the user address words while the FLEXTM decoder II is decoding FLEX signals, the host must disable a user address word before changing it. The ID of the User Address Enable Packet is 120 (decimal). Table 14.17 User Address Enable Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 UAE 15 UAE 7 Bit 6 1 0 UAE 14 UAE 6 Bit 5 1 0 UAE 13 UAE 5 Bit 4 1 0 UAE 12 UAE 4 Bit 3 1 0 UAE 11 UAE 3 Bit 2 0 0 UAE 10 UAE 2 Bit 1 0 0 UAE 9 UAE 1 Bit 0 0 0 UAE 8 UAE 0 UAE: User Address Enable. When a bit is set, the corresponding user address word is enabled. When it is cleared, the corresponding user address word is disabled. UAE0 corresponds to the user address word configured using a packet ID of 128, and UAE15 corresponds to the user address word configured using a packet ID of 143. (value after reset=0) 460 14.3.12 User Address Assignment Packets The FLEXTM decoder II has 16 user address words. Each word can be programmed to be a short address, part of a long address, or the first part of a network ID. The addresses are configured using the Address Assignment Packets. Each user address can be configured as long or short and tone-only or regular (network ID's are short and regular). Although the host is allowed to send these packets while the FLEXTM decoder II is on, the host must disable the user address word by clearing the corresponding UAE bit in the User Address Enable Packet before changing any of the bits in the corresponding User Address Assignment Packet. This method allows for easy reprogramming of user addresses without disrupting normal operation. The IDs for these packets range from 128 to 143 (decimal). Table 14.18 User Address Assignment Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 1 0 A15 A7 Bit 6 0 LA A 14 A6 Bit 5 0 TOA A13 A5 Bit 4 0 A20 A12 A4 Bit 3 a3 A19 A 11 A3 Bit 2 a2 A18 A 10 A2 Bit 1 a1 A17 A9 A1 Bit 0 a0 A16 A8 A0 a: User Address Word Number. This specifies which address word is being configured. A zero in this field corresponds to address index zero (AI = 0) in the Address Packet received from the FLEXTM decoder II when an address is detected. See 14.4.2, Address Packet for a description of the address index field. LA: Long address. When this bit is set, the address is considered a long address. Both words of a long address must have this bit set. The first word of a long address must have an even address index and the second word must be in the address index immediately following the first word. TOA: Tone-Only Address. When this bit is set, the FLEXTM decoder II will consider this address a tone-only address and will not decode a vector word when the address is received. If the TOA bit of a long address word is set, the TOA bit of the other word of the long address must also be set. A: Address word. This is the 21 bit value of the address word. Valid FLEX messaging addresses or Network ID's may be used. 461 14.4 Decoder-to-Host Packet Descriptions The following sections describe the packets of information that will be sent from the FLEXTM decoder II to the host. In all cases the packets are sent MSB first (bit 7 of byte 3 = bit 31 of the packet = MSB). The FLEXTM decoder II decides what data should be sent to the host. If the FLEXTM decoder II is disabled through the checksum feature (see 14.3.1, Checksum Packet for a description of the checksum feature) the Part ID Packet will be sent. Data Packets relating to data received over the air are buffered in the 32 packet transmit buffer. The Data packets include Block Information Word Packets, Address Packets, Vector Packets, and Message Packets. If the FLEXTM decoder II is enabled and a receiver shutdown packet is pending, the receiver shutdown packet will be sent. If there is no receiver shutdown packet pending, but there is a roaming status packet pending, the roaming status packet will be sent. If neither the receiver shutdown packet nor the roaming status packet is pending and there is data in the transmit buffer, a packet from the transmit buffer will be sent. Otherwise, the FLEXTM decoder II will send the Status Packet (which is not buffered). In the event of a buffer overflow, the FLEXTM decoder II will automatically stop decoding and clear the buffer. It is recommended that the Host be designed to empty the FIFO buffer every block with enough time left over to read a status packet. This would ensure that any applicable Status Packet would be received within 1 block of the new status being available. 32 32 32 Part ID Register Receiver Shutdown Register Roaming Status Register MUX 32 SPI Transmit Register MISO 32x32 Data Packet FIFO Transmit Buffer 32 Status Register 32 Figure 14.8 FLEXTM decoder II SPI Transmit Functional Block Diagram 462 14.4.1 Block Information Word Packet The Block Information Field is the first field following the synchronization codes of the FLEX protocol. This field contains information about the frame such as number of addresses and messages, information about current time, the channel ID, channel attributes, etc. The first block information word of each phase is used internally to the FLEXTM decoder II and is never transmitted to the host with the exception of the system collapse which is sent to the host when the FLEXTM decoder II is in manual collapse mode. Time block information words 2-4 can be optionally sent to the host by setting the SBI bit in the control packet (see 14.3.3, Control Packet). All block information words 2-4 can be optionally sent to the host by setting the ABI bit in the roaming control packet. When the SBI or ABI bit is set and any block information word 2-4 is received with an uncorrectable number of biterrors, the FLEXTM decoder II will send the block information word to the host with the e bit setregardless of the value of the f field in the block information word. The FLEXTM decoder II does not support decoding of the vector and message words associated with the Data/System Message block info word (f=101). The ID of a Block Information Word Packet is 0 (decimal). Table 14.19 Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 e x s7 Block Information Word Packet Bit Assignments Bit 6 0 p1 x s6 Bit 5 1 p0 s 13 s5 Bit 4 0 x s 12 s4 Bit 3 0 x s 11 s3 Bit 2 0 f2 s 10 s2 Bit 1 0 f1 s9 s1 Bit 0 0 f0 s8 s0 e: Set if more than 2 bit errors are detected in the word or if the check character calculation fails after error correction has been performed. p: Phase on which the block information word was found (0=a, 1=b, 2=c, 3=d) x: Unused bits. The value of these bits is not guaranteed. f: Word Format Type. The value of these bits modify the meaning of the s bits in this packet as described in the BIW word descriptions in the s bit definition below. s: These are the information bits of the block information word. The definition of these bits depend on the f bits in this packet. The following table describes the block information words. 463 f2 0 0 0 0 1 1 1 1 f1 0 0 1 1 0 0 1 1 f0 1 s13 s12 s11 s10 s9 i7 i6 i5 i4 s8 i3 d3 s7 i2 d2 s6 i1 d1 s5 i0 d0 s4 s3 s2 s1 s0 Description 0* i8 C4 C3 C2 C1 C0 Local ID, Coverage Zone Y4 Y3 Y2 Y1 Y0 Month, Day, Year 1* 2 m3 m2 m1 m0 d4 0* S2 S1 1 2 S0 M5 M4 M3 M2 M1 M0 H4 H3 H2 H1 H0 Second, Minute, Hour 1* Reserved by FLEX protocol for future use 0* 1 Reserved by FLEX protocol for future use 1* 2 z 9 1 z8 z7 z6 z5 z4 z3 z2 z1 z0 A3 A2 A1 A0 System Message 0* Reserved by FLEX protocol for future use 1* 1 c 9 c8 c7 c6 c5 c4 c3 c2 c1 c0 T3 T2 T1 T0 Country Code, Traffic Management Flags Notes: *1 Will be decoded only if the ABI bit is set. *2 Will be decoded only if the SBI or ABI bit is set. 14.4.2 Address Packet The Address Field follows the Block Information Field in the FLEX protocol. It contains all of the addresses in the frame. If less than three bit errors are detected in a received address word and it matches an enabled address assigned to the FLEXTM decoder II, an Address Packet will be sent to the host processor. The Address Packet contains assorted data about the address and its associated vector and message. The ID of an Address Packet is 1 (decimal). Table 14.20 Address Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 PA AI 7 TOA Bit 6 0 p1 AI 6 WN 6 Bit 5 0 p0 AI 5 WN 5 Bit 4 0 LA AI 4 WN 4 Bit 3 0 x AI 3 WN 3 Bit 2 0 x AI 2 WN 2 Bit 1 0 x AI 1 WN 1 Bit 0 1 x AI 0 WN 0 PA: Priority Address. Set if the address was received as a priority address. p: Phase on which the address was detected (0=a, 1=b, 2=c, 3=d) LA: Long Address type. Set if the address was programmed in the FLEXTM decoder II as a long address. AI: Address Index (valid values are 0 through 15 and 128 through 159). The index identifies which of the addresses was detected. Values 0 through 15 correspond to the 16 programmable 464 address words. Values 128 through 143 correspond to the 16 temporary addresses. Values 144 through 159 correspond to the 16 operator messaging addresses. For long addresses, the address detect packet will only be sent once and the index will refer to the second word of the address. TOA: Tone Only Address. Set if the address was programmed in the FLEXTM decoder II as a tone-only address. This bit will never be set for temporary or operator messaging addresses. No vector word will be sent for tone-only addresses. WN: Word number of vector (2 - 87). Describes the location in the frame of the vector word for the detected address. This value is invalid for this packet if the TOA bit is set. x: Unused bits. The value of these bits is not guaranteed. 14.4.3 Vector Packet The Vector Field follows the Address Field in the FLEX protocol. Each Vector Packet must be matched to its corresponding Address Packet. The ID of the vector packet is the word number where the vector word was received in the frame. This value corresponds to the WN bits sent in the associated address packet. The phase information in both the Address Packet and the Vector Packet must also match. It is important to note for long addresses, the first message word will be transmitted in the word location immediately following the associated vector. See14.5.2, Message Building for a message building example. In this case, the word number (identified by b6 to b0 ) in the Vector Packet will indicate the message start of the second message word if the message is longer than 1 word. There are several types of vectors - 3 types of Numeric Vectors, a Short Message / Tone Only Vector, a Hex / Binary Vector, an Alphanumeric Vector, a Secure Message Vector, and a Short Instruction Vector. Each is described in the following pages. Two of the modes of the Short Instruction Vector is used for assigning temporary addresses that may be associated with a group call. The Numeric, Hex / Binary, Alphanumeric, and Secure Message Vector Packets have associated Message Word Packets in the message field. The host must use the n and b bits of the vector word to calculate what message word locations are associated with the vector. The message word locations and the phase must match. Four of the vectors (Hex / Binary, Alphanumeric, Secure Message, and the temporary address assignment modes of the Short Instruction) enable the FLEXTM decoder II to begin the all frame mode. This mode is required to allow for the decoding of temporary addresses and / or fragmented messages. The host disables the All Frame Mode after the proper time by writing to the decoder via the All Frame Mode Packet. See 14.5.3, Building a Fragmented Message and 14.5.4, Operation of a Temporary Address for more information. For any Address Packet sent to the host (except tone-only addresses), a corresponding Vector Packet will always be sent. If more than two 465 bit errors are detected (via BCH calculations, parity calculations, check character calculations, or value validation) in the vector word the e bit will be set and the message words will not be sent. 1. Numeric Vector Packet Table 14.21 Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 e x n0 Numeric Vector Packet Bit Assignments Bit 6 WN6 p1 x b6 Bit 5 WN5 p0 K3 b5 Bit 4 WN4 x K2 b4 Bit 3 WN3 x K1 b3 Bit 2 WN2 V2 K0 b2 Bit 1 WN1 V1 n2 b1 Bit 0 WN0 V0 n1 b0 V: Vector type identifier. V2 V1 V0 Name 01 10 11 1 Standard NumericVector Description No special formatting of characters is specified 0 Special Format Numeric Vector Formatting of the received characters is predetermined by special rules in the host. 1 Numbered Numeric Vector The received information has been numbered by the service provider to indicate all messages have been properly received WN: Word number of vector (2 - 87 decimal). Describes the location of the vector word in the frame. e: Set if more than 2 bit errors are detected in the word, if the check character calculation fails after error correction has been performed, or if the vector value is determined to be invalid. p: Phase on which the vector was found (0=a, 1=b, 2=c, 3=d) K: Beginning check bits of the message. n: Number of message words in the message including the second vector word for long addresses (000 = 1 word message, 001 = 2 word message, etc.). For long addresses, the first message word is located in the word location that immediately follows the associated vector. b: Word number of message start in the message field (3-87 decimal). For long addresses, the word number indicates the location of the second message word. x: Unused bits. The value of these bits is not guaranteed. 466 2. Short Message / Tone Only Vector Table 14.22 Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 e x d5 Short Message / Tone Only Vector Packet Bit Assignments Bit 6 WN 6 p1 x d4 Bit 5 WN5 p0 d11 d3 Bit 4 WN4 x d10 d2 Bit 3 WN3 x d9 d1 Bit 2 WN 2 V2 d8 d0 Bit 1 WN1 V1 d7 t1 Bit 0 WN 0 V0 d6 t0 V: 010 for a Short Message / Tone Only Vector WN: Word number of vector (2 - 87 decimal). Describes the location of the vector word in the frame. e: Set if more than 2 bit errors are detected in the word or, if after error correction, the check character calculation fails. p: Phase on which the vector was found (0=a, 1=b, 2=c, 3=d) d: Data bits whose definition depend on the value of t in this packet according to the following table. Note that if this vector is received on a long address and the e bit in this packet is not set, the decoder will send a Message Packet from the word location immediately following the Vector Packet. Except for the short message on a non-network address (t=0), all message bits in the Message Packet are unused and should be ignored. t1 t0 0 0 0 1 0 0 1 0 d1 1 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Description c3 c2 c 1 c 0 b3 b2 b1 b0 a3 a2 a1 a0 Short Numeric: 3 numeric chars*1 when on a messaging address T3 T2 T1 T0 M2 M1 M0 A4 A3 A2 A1 A0 Part of NID when on a Network Address s8 s1 s7 s0 s 6 s 5 s 4 s 3 s 2 s 1 s 0 S2 S1 S0 Tone Only: 8 sources (S) and 9 unused bits (s) R0 N5 N4 N3 N2 N1 N0 S2 S1 S0 Tone Only: 8 sources (S), message number (N), message retrieval flag (R), and 2 unused bits (s) spare message type 1 1 Note: For long addresses, an extra 5 characters are sent in the Message Packet immediately following the Vector Packet. t: Message type. These bits define the meaning of the d bits in this packet. x: Unused bits. The value of these bits is not guaranteed. 467 3. HEX / Binary, Alphanumeric, and Secure Message Vector Table 14.23 HEX / Binary, Alphanumeric, and Secure Message Vector Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 e x n0 Bit 6 WN 6 p1 x b6 Bit 5 WN5 p0 n6 b5 Bit 4 WN4 x n5 b4 Bit 3 WN3 x n4 b3 Bit 2 WN 2 V2 n3 b2 Bit 1 WN1 V1 n2 b1 Bit 0 WN 0 V0 n1 b0 V: Vector type identifier. V2 V1 V0 00 10 11 0 1 0 Type Secure Alphanumeric Hex / Binary WN: Word number of vector (2 - 87 decimal). Describes the location of the vector word in the frame. e: Set if more than 2 bit errors are detected in the word, if the check character calculation fails after error correction has been performed, or if the vector value is determined to be invalid. p: Phase on which the vector was found (0=a, 1=b, 2=c, 3=d) n: Number of message words in this frame including the first Message word that immediately follows a long address vector. Valid values are 1 through 85 decimal. b: Word number of message start in the message field. Valid values are 3 through 87 decimal. x: Unused bits. The value of these bits is not guaranteed. Note: For long addresses, the first Message Packet is sent from the word location immediately following the word location of the Vector Packet. The b bits indicate the second message word in the message field if one exists. 468 4. Short Instruction Vector Short Instruction Vector Packet Bit Assignments Bit 6 WN 6 p1 x d3 Bit 5 WN5 p0 d 10 d2 Bit 4 WN4 x d9 d1 Bit 3 WN3 x d8 d0 Bit 2 WN 2 V2 d7 i2 Bit 1 WN1 V1 d6 i1 Bit 0 WN 0 V0 d5 i0 Table 14.24 Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 e x d4 V: 001 for a Short Instruction Vector WN: Word number of vector (2 - 87 decimal). Describes the location of the vector word in the frame. e: Set if more than 2 bit errors are detected in the word or, if after error correction, the check character calculation fails. p: Phase on which the vector was found (0=a, 1=b, 2=c, 3=d) d: Data bits whose definition depend on the i bits in this packet according to the following table. Note that if this vector is received on a long address and the e bit in this packet is not set, the decoder will send a Message Packet immediately following the Vector Packet. All message bits in the message packet are unused and should be ignored for all modes except the Temporary address assignment with MSN (i2 i1 i0 =010). i2 0 0 0 0 1 1 1 1 i1 0 0 1 1 0 0 1 1 I0 0 1 0 1 0 1 0 1 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Description a3 a2 a1 a0 f 6 f5 f4 f3 f2 f1 f0 Temporary address assignment* 1 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 11 Event Flags for System Event a3 a2 a1 a0 f 6 N5 N4 N3 N2 N1 N0 Temporary address assignment with MSN* 2 Reserved Reserved Reserved Reserved Reserved for test Notes: *1 Assigned temporary address (a) and assigned frame (f). See 14.5.4, Operation of a Temporary Address for a description of the use of these fields. *2 Assigned temporary address (a), MSb of assigned frame (f 6 ), and message sequence number (N). The message packet sent with this instruction on long addresses contains extra frame information, see 14.5.4, Operation of a Temporary Address for a description and for details on the use of the other fields. 469 i: Instruction type. These bits define the meaning of the d bits in this packet. x: Unused bits. The value of these bits is not guaranteed. 14.4.4 Message Packet The Message Field follows the Vector Field in the FLEX protocol. It contains the message data, checksum information, and may contain fragment numbers and message numbers. If the error bit of a vector word is not set and the vector word indicates that there are message words associated with the page, the message words are sent in Message Packets. The ID of the Message Packet is the word number where the message word was received in the frame. Table 14.25 Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 e i 15 i7 Message Packet Bit Assignments Bit 6 WN 6 p1 i 14 i6 Bit 5 WN5 p0 i 13 i5 Bit 4 WN4 i 20 i 12 i4 Bit 3 WN3 i 19 i 11 i3 Bit 2 WN 2 i 18 i 10 i2 Bit 1 WN1 i 17 i9 i1 Bit 0 WN 0 i 16 i8 i0 WN: Word number of message word (3 - 87 decimal). Describes the location of the message word in the frame. e: Set if more than 2 bit errors are detected in the word. p: Phase on which the message word was found (0=a, 1=b, 2=c, 3=d) i: These are the information bits of the message word. The definitions of these bits depend on the vector type and which word of the message is being received. 14.4.5 Roaming Status Packet The contents of this section apply to the FLEX Roaming Decoder. They are not applicable to the FLEX Non-Roaming Decoder. The FLEXTM decoder II will automatically prompt the host to read a Roaming Status Packet if RSR, MS1, MFI, MS2, MBI, MAW, NBU, NDR1 , NDR0 , or SCU is set. 470 Table 14.26 Roaming Status Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 RSR x x Bit 6 1 MS1 x x Bit 5 1 MFI x x Bit 4 0 MS2 x x Bit 3 0 MBI x SCU Bit 2 0 MAW x RSC2 Bit 1 0 NBU NDR1 RSC1 Bit 0 0 n NDR0 RSC0 RSR: Re-synchronization Signal Received. Set when the FLEXTM decoder II detected a resynchronization signal and the host configured the FLEXTM decoder II to ignore it via the IRS bit in the roaming control packet. This bit is cleared when read. MS1: Missed Synchronization 1. Set when the FLEXTM decoder II failed to detect the first synchronization pattern (A / A) of a FLEX frame and the FLEXTM decoder II was configured to report missed frame information via the MFC bit in the roaming control packet. This bit is cleared when read. MFI: Missed Frame Information word. Set when the frame information word is received with an uncorrectable number of errors and the FLEXTM decoder II was configured to report missed frame information via the MFC bit in the roaming control packet. This bit is cleared when read. MS2: Missed Synchronization 2. Set when the FLEXTM decoder II failed to detect the second synchronization pattern (C / C) of a frame and FLEXTM decoder II was configured to report missed frame information via the MFC bit in the roaming control packet. This bit is cleared when read. MBI: Missed Block Information word 1. Set when at least one of the block information word ones is received with an uncorrectable number of errors and FLEXTM decoder II was configured to report missed frame information via the MFC bit in the roaming control packet. This bit is set no more than once per frame regardless of the number of missed block information word 1's in the frame. This bit is cleared when read. MAW: Missed Address Word. Set when any address words in the address field is received with an uncorrectable number of errors and FLEXTM decoder II was configured to report missed frame information via the MFC bit in the roaming control packet. This bit is set no more than once per frame regardless of the number of missed address words in the frame. This bit is cleared when read. NBU: Network Bit Update. Set when the NBC bit in the roaming control packet is set and a frame information word is received with a correctable number of errors. This bit will not be set when the frame information word is not received due to missing the first synchronization pattern (A / A). This bit is cleared when read. 471 n: Network bit value. When NBU is set, this is the value of the n bit in the last received frame information word. NDR: Noise Detect Result. These bits indicate the result of a noise detect. The results of noise detects initiated by setting the SND bit in the roaming control packet will always be reported. The results of the automatic noise detects performed in asynchronous mode will only be reported if the RND bit is set in the roaming control packet. When continuous noise detects during block data are enabled by setting the CND bit in the roaming control packet, only the "No FLEX signal detected" result will be reported. These bits are cleared when read. NDR 00 01 10 11 Noise Detect Result No Information Noise Detect was abandoned FLEX signal detected FLEX signal not detected SCU: System Collapse Update. Set when the FLEXTM decoder II is configured for manual collapse mode by setting the MCM bit in the roaming control packet and the system collapse of a frame is received. This bit is set no more than once per frame regardless of the number of phases in the frame. This bit will not be set in frames in which no block information word ones is received properly. This bit is cleared when read. RSC: Received System Collapse. When SCU is set, this value represents the system collapse value that was received in the frame. 472 14.4.6 Receiver Shutdown Packet The contents of this section apply to the FLEX Roaming Decoder. They are not applicable to the FLEX Non-Roaming Decoder. The Shutdown Packet is sent in both synchronous and asynchronous mode. It is designed to indicate to the host that the receiver is turned off and how much time there is until the FLEXTM decoder II will automatically turn it back on. Table 14.27 Receiver Shut Down Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 FNV TNF 7 FCO Bit 6 1 CF 6 TNF 6 NAF 6 Bit 5 1 CF 5 TNF 5 NAF 5 Bit 4 1 CF 4 TNF 4 NAF 4 Bit 3 1 CF 3 TNF 3 NAF 3 Bit 2 1 CF 2 TNF 2 NAF 2 Bit 1 1 CF 1 TNF 1 NAF 1 Bit 0 1 CF0 TNF 0 NAF 0 FNV: Frame Number Valid. This bit is set if the last decoded frame info word was correctable and the frame number was the expected value. When in asynchronous mode, this value will be 0. CF: Current Frame. When in synchronous mode, this is the current frame number. This value is latched on the negative edge of the READY line when this packet is sent to the host. The value of this field is valid only if the FLEXTM decoder II is in synchronous mode and the FIV bit in the status packet is set. When in asynchronous mode, this value will be 0. TNF: Time to Next Frame. When in synchronous mode TNF indicates the time to the start of the A-word check if the FLEXTM decoder II were to warm up for the next frame. When in asynchronous mode TNF indicates the time to the start of the next automatic noise detect. See "Using the Receiver Shutdown Packet" on page 66 for an explanation on how to use this value. This value is latched on the negative edge of the READY line when this packet is sent to the host. FCO: Frame Carried On. Set if the FLEXTM decoder II is decoding the next frame due to the reception of a non-zero carry-on value in the current or a previous frame. When in asynchronous mode, this value will be 0. NAF: Next Assigned Frame. This is the frame number of the next frame the FLEXTM decoder II was scheduled to decode when the receiver shut down. The value of this field is valid only if the FLEXTM decoder II is in synchronous mode and the FIV bit in the status packet is set. When in asynchronous mode this value will be 0. 473 14.4.7 Status Packet The Status Packet contains various types of information that the host may require. The Status Packet will be sent to the host whenever the FLEXTM decoder II is polled and has no other data to send. The FLEXTM decoder II can also prompt the host to read the Status Packet due to events for which the FLEXTM decoder II was configured to send it (see 14.3.2, Configuration Packet and 14.3.3, Control Packet for a detailed description of the bits). The FLEXTM decoder II will prompt the host to read a Status Packet if the... 1. 2. 3. 4. 5. 6. ... SMU bit in the Status Packet and the SME bit in the Configuration Packet are set. ... MT bit in the Status Packet and the MTE bit in the Configuration Packet are set. ... EOF bit in the Status Packet is set. ... LBU bit in the Status Packet is set. ... EA bit in the Status Packet is set. ... BOE bit in the Status Packet is set. The ID of the Status Packet is 127 (decimal). Table 14.28 Status Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 FIV SM SMU Bit 6 1 f6 LB LBU Bit 5 1 f5 x x Bit 4 1 f4 x MT Bit 3 1 f3 c3 x Bit 2 1 f2 c2 EOF Bit 1 1 f1 c1 EA Bit 0 1 f0 c0 BOE FIV: Frame Info Valid. Set when a valid frame info word has been received since becoming synchronous to the system and the f and c fields contain valid values. If this bit is clear, no valid frame info words have been received since the FLEXTM decoder II became synchronous to the system. This value will change from 0 to 1 at the end of block 0 of the frame in which the 1st frame info word was properly received. It will be cleared when the FLEXTM decoder II goes into asynchronous mode. This bit is initialized to 0 when the FLEXTM decoder II is reset and when the FLEXTM decoder II is turned off by clearing the ON bit in the Control Packet. f: Current frame number. This value is updated every frame regardless of whether the FLEXTM decoder II needs to decode the frame. This value will change to its proper value for a frame at the end of block 0 of the frame. The value of these bits is not guaranteed when FIV is 0. SM: Synchronous Mode. This bit is set when the FLEXTM decoder II is synchronous to the system. The FLEXTM decoder II will set this bit when the first synchronization words are received. It will clear this bit when the FLEXTM decoder II has not properly received both synchronization words in any frame for 8, 16, or 32 minutes (depending on the number of assigned frames and the 474 system collapse). This bit is initialized to 0 when the FLEXTM decoder II is reset and when it is turned off by clearing the ON bit in the Control Packet. LB: Low Battery. Set to the value last read from the LOBAT pin. The host controls when the LOBAT pin is read via the Receiver Control Packets. This bit is initialized to 0 at reset. It is also initialized to the inverse of the LBP bit in the Configuration Packet when the FLEXTM decoder II is turned on by setting the ON bit in the Control Packet. c: Current system cycle number. This value is updated every frame regardless of whether the FLEXTM decoder II needs to decode the frame.This value will change to its proper value for a frame at the end of block 0 of the frame. The value of these bits is not guaranteed when FIV is 0. SMU: Synchronous Mode Update. Set if the SM bit has been updated in this packet. When the FLEXTM decoder II is turned on, this bit will be set when the first synchronization words are found (SM changes to 1) or when the first synchronization search window after the FLEXTM decoder II is turned on expires (SM stays 0). The latter condition gives the host the option of assuming the paging device is in range when it is turned on, and displaying out-of-range only after the initial A search window expires. After the initial synchronous mode update, the SMU bit will be set whenever the FLEXTM decoder II transitions from/to synchronous mode. Cleared when read. Changes in the SM bit due to turning off the FLEXTM decoder II will not cause the SMU bit to be set. This bit is initialized to 0 when the FLEXTM decoder II is reset. LBU: Low Battery Update. Set if the value on two consecutive reads of the LOBAT pin yielded different results. Cleared when read. The host controls when the LOBAT pin is read via the Receiver Control Packets. Changes in the LB bit due to turning on the FLEXTM decoder II will not cause the LBU bit to be set. This bit is initialized to 0 when the FLEXTM decoder II is reset. MT: Minute Time-out. Set if one minute has elapsed. Cleared when read. This bit is initialized to 0 when the FLEXTM decoder II is reset. EOF: End Of Frame. Set when the FLEXTM decoder II is in all frames mode and the end of frame has been reached. The FLEXTM decoder II is in all frames mode if the all frames mode enable counter is non-zero, if any temporary address enabled counter is non-zero, or if the FAF bit in the All Frame Mode Packet is set. Cleared when read. This bit is initialized to 0 when the FLEXTM decoder II is reset. EA: End of Addresses. If EAE of the control packet is set and an address is detected in a frame, EA will be set after the FLEXTM decoder II processes the last address in the frame. Since data packets take priority over the status packet, the status packet with the EA bit set is guaranteed to come after all address packets for the frame. Cleared when read. This bit is initialized to 0 when the FLEXTM decoder II is reset. BOE: Buffer Overflow Error. Set when information has been lost due to slow host response time. When the data packet FIFO transmit buffer on the FLEXTM decoder II overflows, the FLEXTM 475 decoder II clears the buffer, turns off decoding by clearing the ON bit in the Control Packet, and sets this bit. Cleared when read. This bit is initialized to 0 when the FLEXTM decoder II is reset. x: Unused bits. The value of these bits is not guaranteed. 14.4.8 Part ID Packet The Part ID Packet is sent by the FLEXTM decoder II whenever the FLEXTM decoder II is disabled due to the checksum feature. See 14.3.1, Checksum Packet for a description of the checksum feature. Since the FLEXTM decoder II is disabled after reset, this is the first packet that will be received by the host after reset. The ID of the Part ID Packet is 255 (decimal). Table 14.29 Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 1 MDL 1 CID 7 REV 7 Part ID Packet Bit Assignments Bit 6 1 MDL0 CID 6 REV 6 Bit 5 1 CID 13 CID 5 REV 5 Bit 4 1 CID 12 CID4 REV 4 Bit 3 1 CID 11 CID 3 REV 3 Bit 2 1 CID 10 CID 2 REV 2 Bit 1 1 CID 9 CID 1 REV 1 Bit 0 1 CID 8 CID 0 REV 0 MDL: Model. This identifies the FLEXTM decoder II model. Current value is 0. CID: Compatibility ID. This value describes the FLEXTM decoders to which this part is backwards compatible. See table below for meaning and current value. Bit CID0 CID1 CID2 Indicates this IC can be used in place of FLEX Alphanumeric Decoder I* FLEX Roaming Decoder I* FLEX Numeric Decoder 2 1 Value for FLEX Roaming Decoder II 1 (TRUE) 1 (TRUE) 0 (FALSE) Notes: *1 Compatibility to FLEX Alphanumeric Decoder II is indicated by MDL set to 0, CID 0 set to 1, and REV greater than or equal to 7. *2 Compatibility to FLEX Roaming Decoder II is indicated by MDL set to 0, CID 1 set to 1, and REV greater than or equal to 8. REV: Revision. This identifies the revision and manufacturer of the FLEXTM decoder II. The following table lists the currently available part ID's of the FLEXTM decoder II family. 476 Part ID Packet (Hex) 00 01 03 00 01 04 00 01 06 00 01 07 00 01 08 00 03 03 00 03 05 00 03 09 00 03 0A 00 04 01 00 01 15 00 01 16 00 03 15 00 03 16 Revision FLEX Alphanumeric Decoder I FLEX Alphanumeric Decoder I FLEX Alphanumeric Decoder I FLEX Alphanumeric Decoder II FLEX Alphanumeric Decoder II FLEX Roaming Decoder I FLEX Roaming Decoder I FLEX Roaming Decoder II FLEX Roaming Decoder II FLEX Numeric Decoder FLEX Alphanumeric Decoder II FLEX Alphanumeric Decoder II FLEX Roaming Decoder II FLEX Roaming Decoder II Manufacturer Texas Instruments Motorola Semiconductor Products Sector Philips Motorola Semiconductor Products Sector Texas Instruments Motorola Semiconductor Products Sector Texas Instruments Motorola Semiconductor Products Sector Texas Instruments Texas Instruments HITACHI H8/3937 Series HITACHI H8S/2276 Series HITACHI H8/3937 Series HITACHI H8S/2276 Series 477 14.5 14.5.1 Application Notes Receiver Control Introduction: The FLEXTM decoder II has 8 programmable receiver control lines (S0-S7). The host has control of the receiver warm up and shut down timing as well as all of the various settings on the control lines through configuration registers on the FLEXTM decoder II. The configuration registers for most settings allow the host to configure what setting is applied to the control lines, how long to apply the setting, and if the LOBAT input pin is polled before changing from the setting. With this programmability, the FLEXTM decoder II should be able to interface with many off-the-shelf receiver ICs. When using the internal demodulator (i.e. when the IDE bit of the configuration packet is set), the S0 pin becomes the input for the demodulator and the S0 register setting in the receiver control configuration packets controls the tracking mode of the peak and valley detectors for the internal data slicer. When the S0 bit is set in a receiver setting, the internal data slicer will be in fast track mode. When the S0 bit is cleared in a receiver setting, the internal data slicer will be in slow track mode. For details on the configuration of the receiver control settings, see 14.3.9, Receiver Control Configuration Packets. 1. Receiver Settings at Reset The receiver control ports are three-state outputs which are set to the high-impedance state when the FLEXTM decoder II is reset and until the corresponding FRS bit in the Receiver Line Control Packet is set or until the FLEXTM decoder II is turned on by setting the ON bit in the Control Packet. This allows the designer to force the receiver control lines to the receiver off setting with external pull-up or pull-down resistors before the host can configure these settings in the FLEXTM decoder II. When the FLEXTM decoder II is turned on, the receiver control ports are driven to the settings configured by the "14.3.9 Receiver Control Configuration Packets" until the FLEXTM decoder II is reset again. 2. Automatic Receiver Warm Up Sequence The FLEXTM decoder II allows for up to 6 steps associated with warming up the receiver. When the FLEXTM decoder II automatically turns on the receiver, it starts the warm up sequence 160 ms before it requires valid signals at the EXTS0 and EXTS1 input pins (or the equivalent internal signals when using the internal demodulator/data slicer). The first step of the warm up sequence involves leaving the receiver control lines in the "Off" state for the amount of time programmed for "Warm Up Off Time". At the end of the "Warm Up Off Time", the first warm up setting, if enabled, is applied to the receiver control lines for the amount of time programmed for that setting. Each subsequent warm up setting is applied to the receiver control lines for their corresponding time until a disabled warm up setting is found. At the end of the last used warm up setting, the "1600sps Sync Setting" or the "3200sps Sync Setting" is applied to the receiver control lines depending on the current state of the FLEXTM decoder II. The sum total of all of the used warm up times and the "Warm Up Off Time" must not exceed 160ms. If it exceeds 160ms, the FLEXTM decoder II will execute the receiver shut down sequence at the end of the 160ms warm up period. 478 The receiver warm up sequence while decoding when all warm up settings are enabled is shown in figure 14.9. 160 ms Warm Up Off Time RECEIVER CONTROL LINE SETTING Warm Up Time 1 Warm Up Setting 1 Warm Up Time 2 Warm Up Setting 2 Warm Up Time 3 Warm Up Setting 3 Warm Up Time 4 Warm Up Setting 4 Warm Up Time5 Warm Up Setting 5 1600sps or 3200sps Sync Setting Off Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check EXTS1 & EXTS0 signals are expected to be valid here. Figure 14.9 Automatic Receiver Warm Up Sequence 3. Host Initiated Receiver Warm Up Sequence The host can cause the FLEXTM decoder II to warm-up the receiver in three ways: (1) by turning on the FLEXTM decoder II by setting the ON bit in the control packet; (2) by requesting a noise detect by setting the SND bit in the roaming control packet; or (3) by requesting an A-word search by setting the SAS bit in the roaming control packet. When the FLEXTM decoder II warms up the receiver in response to a host request, the first warm up setting, if enabled, is applied to the receiver control lines for the amount of time programmed for that setting. Each subsequent warm up setting is applied to the receiver control lines for their corresponding time until a disabled warm up setting is found. Once a disabled warm up setting is found, the "3200sps Sync Setting" (for ON and SND warm ups) or the "1600sps Sync Setting" (for SAS warm ups) is applied to the receiver control lines and the decoder does not expect valid signal until after the "3200sps Sync Warm Up Time" (for ON, SND, and SAS warm ups) has expired. In figure 14.10 the receiver warm up sequence when the host initiates a warm-up sequence and when all warm up settings are enabled is shown. Warm Up Time Sync 3200sps 3200sps Sync Setting Warm Up Time 1 RECEIVER CONTROL LINE SETTING Warm Up Setting 1 Warm Up Time 2 Warm Up Setting 2 Warm Up Time 3 Warm Up Setting 3 Warm Up Time 4 Warm Up Setting 4 Warm Up Time5 Warm Up Setting 5 Off Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check EXTS1 & EXTS0 signals are expected to be valid here. Figure 14.10 Host Initiated Receiver Warm Up Sequence 479 4. Receiver Shut Down Sequence The FLEXTM decoder II allows for up to 3 steps associated with shutting down the receiver. When the FLEXTM decoder II decides to turn off the receiver, the first shut down setting, if enabled, is applied to the receiver control lines for the corresponding shut down time. At the end of the last used shut down time, the "Off" setting is applied to the receiver control lines. If the first shut down setting is not enabled, the FLEXTM decoder II will transition directly from the current on setting to the "Off" setting. The receiver turn off sequence when all shut down settings are enabled is shown in figure 14.11. If the receiver is on or being warmed up when the decoder is turned off (by clearing the ON bit in the Control Packet), the FLEXTM decoder II will execute the receiver shutdown sequence. If the FLEXTM decoder II is executing the shut down sequence when the FLEXTM decoder II is turned on (by setting the ON bit in the Control Packet), the FLEXTM decoder II will complete the shut down sequence before starting the warm up sequence. Shut Down Time 1 RECEIVER CONTROL LINE SETTING 1600sps or 3200sps Sync or Data Setting Shut Down Setting 1 Shut Down Time 2 Shut Down Setting 2 Off Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Figure 14.11 5. Miscellaneous Receiver States Receiver Shut Down Sequence In addition to the warm up and shut down states, the FLEXTM decoder II has four other receiver states. When these settings are applied to the receiver control lines, the FLEXTM decoder II will be decoding the EXTS1 and EXTS0 input signals (or the equivalent internal signals when using the internal demodulator/data slicer). The timing of these signals and their duration depends on the data the FLEXTM decoder II decodes. The four settings are as follows: * 1600sps Sync Setting:This setting is applied when the FLEXTM decoder II is searching for a 1600 symbols per second signal. * 3200sps Sync Setting:This setting is applied when the FLEXTM decoder II is searching for a 3200 symbols per second signal. * 1600sps Data Setting:This setting is applied after the FLEXTM decoder II has found the C or C sync word in a 1600 symbols per second frame. 480 * 3200sps Data Setting:This setting is applied after the FLEXTM decoder II has found the C or C sync word in a 3200 symbols per second frame. Some examples of how these settings will be used in the FLEXTM decoder II are shown in figure 14.12. Frame Info FLEX SIGNAL Block 10 Sync 1 Sync 2 Block 0 RECEIVER CONTROL LINE SETTING EXAMPLE #1 1600 sps Data or 3200 sps Data or Last Used Warm Up Setting 1600 sps Sync Setting 3200sps Sync Setting 3200sps Data Setting Possible LOBAT Check RECEIVER CONTROL LINE SETTING EXAMPLE #2 1600 sps Data or 3200 sps Data or Last Used Warm Up Setting Possible LOBAT Check 1600sps Sync Setting Possible LOBAT Check 1600 sps Data Setting Possible LOBAT Check Possible LOBAT Check Figure 14.12 6. Low Battery Detection Examples of Receiver Control Transitions The FLEXTM decoder II can be configured to poll the LOBAT input pin at the end of every receiver control setting. This check can be enabled or disabled for each receiver control setting. If the poll is enabled for a setting, the pin will be read just before the FLEXTM decoder II changes the receiver control lines from that setting to another setting. The FLEXTM decoder II will send a Status Packet whenever the value on two consecutive reads of the LOBAT pin yields different results. 14.5.2 Message Building A simple message consists of an Address Packet followed by a Vector Packet indicating the word numbers of associated Message Packets.The tables below show a more complex example of receiving three Messages and two Block Information Word Packets in the first two blocks of a 2 phase 3200 bps, FLEX frame. Note that the messages shown may be portions of fragmented or group messages. Note further that in the case of a 6400 bps FLEX signal, there would be four phases: A, B, C and D, and in the case of a 1600 bps signal there would be only a single phase A. Table 14.30 shows the block number, word number (WN) and word content of both phases A and C. Note contents of words not meant to be received by the host are left blank. Each phase begins with a block information word (WN 0), this is not sent to the host. The first message is in phase A 481 and has an address (WN 3), vector (WN 7) and three message words (WN9 - 11). The second message is also in phase A and has an address (WN 4), a vector (WN 8) and four message words (WN 12 - 15). The third message is in phase C and has a 2 word long address (WN 5 - 6) followed by a vector (WN 10) and three message words. Since the third message is sent on a long address, the first message word (WN 11) begins immediately after the vector. The vector indicates the location of the second and third message words (WN 14 - 15). Table 14.30 FLEX SIGNAL BLOCK 0 Word Number 0 1 3 4 5 6 7 1 8 9 10 11 12 13 14 15 VECTOR 1 VECTOR 2 MESSAGE 1,1 MESSAGE 1,2 MESSAGE 1,3 MESSAGE 2,1 MESSAGE 2,2 MESSAGE 2,3 MESSAGE 2,4 MESSAGE 3,2 MESSAGE 3,3 VECTOR 3 MESSAGE 3,1 ADDRESS 1 ADDRESS 2 LONG ADDRESS 3 WORD 1 LONG ADDRESS 3 WORD 2 PHASE A BIW1 PHASE C BIW1 BIW BIW Table 14.31 shows the sequence of packets received by the host. The FLEXTM decoder II processes the FLEX signal one block at a time, and one phase at a time. Thus, the address and vector information in block 0 phase A is sent to the host in packets 1-3. Then information in block 0 phase C, two block information words and one long address, is sent to the host in packets 4-6. Packets 7 - 18 correspond to information in block 1, processed in phase A first and phase C second. 482 Table 14.31 FLEXTM DECODER II PACKET SEQUENCE PHASE A A A C C C A A A A A A A A C C C C WORD NUMBER N.A. (7) N.A. (8) 7 N.A. N.A. N.A. (10) 8 9 10 11 12 13 14 15 10 11 14 15 COMMENT Address 1 has a vector located at WN 7 Address 2 has a vector located at WN 8 Vector for Address 1: Message Words located at WN = 9 to 11, phase A If BIWs enabled, then BIW packet sent If BIWs enabled, then BIW packet sent Long Address 3 has a vector beginning in word 10 of phase C Vector for Address 2: Message Words located at WN = 12 to 15, phase A Message information for Address 1 Message information for Address 1 Message information for Address 1 Message information for Address 2 Message information for Address 2 Message information for Address 2 Message information for Address 2 Vector for Long Address 3: Message Words located at WN = 14 - 15, phase C Second word of Long Vector is first message information word of Address 3 Message information for Address 3 Message information for Address 3 PACKET PACKET TYPE 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th 15th 16th 17th 18th ADDRESS ADDRESS VECTOR BIW BIW LONG ADDRESS VECTOR MESSAGE MESSAGE MESSAGE MESSAGE MESSAGE MESSAGE MESSAGE VECTOR MESSAGE MESSAGE MESSAGE The first message is built by relating packets 1, 3, and 8-10. The second message is built by relating packets 2, 7 and 11 - 14. The third message is built by relating packets 6 and 15 - 18. Additionally, the host may process block information in packets 4 and 5 for time setting information. 14.5.3 Building a Fragmented Message The longest message which will fit into a frame is 84 code words total of message data. Three alpha characters per word yields a maximum message of 252 characters in a frame assuming no other traffic. Messages longer than this value must be sent as several fragments. 483 Additional fragments can be expected when the "continue bit" in the 1st Message Word is set. This causes the pager to examine every following frame for an additional fragment until the last fragment with the continue bit reset is found. The only requirement relating to the placement in time of the remaining fragments is that no more than 32 frames (1 minute) or 128 frames (4 minutes) as indicated by the service provider may pass between fragment receptions. Each fragment contains a check sum character to detect errors in the fragment, a fragment number 0, 1, or 2 to detect missing fragments, a message number to identify which message the fragment is a part, and the continue bit which either indicates that more fragments are in queue or that the last fragment has been received. The following describes the sequence of events between the Host and the FLEXTM decoder II required to handle a fragmented message: * The host will receive a vector indicating one of the following types: V2 V1 V0 00 10 11 0 1 0 Type Secure Alphanumeric Hex / Binary * The FLEXTM decoder II will increment the all frame mode counter inside the FLEXTM decoder II and begin to decode all of the following frames. * The host will receive the Message Packet(s) contained within that frame followed by a Status Packet. The host must decide based on the Message Packet to return to normal decoding operation. If the message is indicated as fragmented by the Message Continued Flag "C" being set in the Message Packet then the host does not decrement the all frame mode counter at this time. The host decrements the counter if the Message Continued Flag "C" is clear by writing the All Frame Mode Packet to the FLEXTM decoder II with the "DAF" bit = 1. If no other fragments, temporary addresses are pending and the FAF bit is clear in the All Frame Mode Register, then the FLEXTM decoder II returns to normal operation. * The FLEXTM decoder II continues to decode all of the frames and passes any address information, vector information and message information to the host followed by a status packet indicating the end of the frame. If the message is indicated as fragmented by the Message Continued Flag "C" in the Message Packet then the host remains in the receive mode expecting more information from the FLEXTM decoder II. * After the host receives the second and subsequent fragment with the Message Continued Flag "C" = 1, it should decrement the all frame mode counter by sending an All Frame Mode Packet to the FLEXTM decoder II with the "DAF" bit = 1. Alternatively, the host may choose to decrement the counter at the end of the entire message by decrementing the counter once for each fragment received. * When the host receives a Message Packet with the Message Continued Flag "C" = 0, it will send two All Frame Mode Packets to the FLEXTM decoder II with the "DAF" bit = 1. The two 484 packets decrement the count for the first fragment and the last fragment. This dec-rements the all frame counter to zero, if no other fragmented messages, temporary addresses are pending and the FAF bit is clear in the All Frame Mode Register, the FLEXTM decoder II returns to normal operation. * The above process must be repeated for each occurrence of a fragmented message. The host must keep track of the number of fragmented messages being decoded and insure the all frame mode counter decrements after each fragment or after each fragmented message. Table 14.32 Alphanumeric Message without fragmentation PACKET 1st 2nd 3rd 4th Note: * PACKET TYPE ADDRESS 1 VECTOR 1 MESSAGE Variable* PHASE A A A All Frame Counter COMMENT 0 1 1 0 Address 1 is received Vector = Alphanumeric Type Message Word received "C" bit = 0, No more fragments are expected. Host writes All Frame Mode Packet to the FLEXTM decoder II with the "DAF" bit = 1 Host Initiated Packet. The FLEXTM decoder II returns a packet according to 14.4, Decoder-to-Host Packet Descriptions. 485 Table 14.33 Alphanumeric Message with fragmentation PACKET 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th Note: * PACKET TYPE ADDRESS 1 VECTOR 1 MESSAGE STATUS ADDRESS 1 VECTOR 1 MESSAGE Variable* STATUS ADDRESS 1 VECTOR 1 MESSAGE Variable* Variable* A A A B B B PHASE A A A All Frame Counter COMMENT 0 1 1 1 1 2 2 1 1 1 2 2 1 0 Address 1 is received Vector = Alphanumeric Type Message Word received "C" bit = 1, Message is fragmented, more expected End of Frame Indication (EOF = 1) Address 1 is received Vector = Alphanumeric Type Message Word received "C" bit = 1, Message is fragmented, more expected. Host writes All Frame Mode Packet to the FLEXTM decoder II with the "DAF" bit = 1 End of Frame Indication (EOF = 1) Address 1 is received Vector = Alphanumeric type Message Word received "C" bit = 0, No more fragments are expected. Host writes All Frame Mode Packet to the FLEXTM decoder II with the "DAF" bit = 1 Host writes All Frame Mode Packet to the FLEXTM decoder II with the "DAF" bit = 1 Host Initiated Packet. The FLEXTM decoder II returns a packet according to 14.4, Decoder-to-Host Packet Descriptions. 14.5.4 Operation of a Temporary Address 1. Group Messaging The FLEX protocol allows for a dynamic group call for the purpose of sending a common message to a group of paging devices. The dynamic group call approach assigns a "Temporary Address" using the personal address and the short instruction vector. The FLEX protocol specifies sixteen addresses for the dynamic group call which may be temporarily activated in a future frame (If the frame or one of the frames designated is equal to the present frame the host is to interpret this as the next occurrence of this frame 4 minutes in the future.) The temporary address is valid for one message starting in the specified frame(s) and remaining valid throughout the following frames to the completion of the message. If the message is not found in the specified frame(s) the host must disable the assigned temporary address. 486 The following describes the sequence of events between the Host and the FLEXTM decoder II required to handle a temporary address: * Following an Address Packet, the host will receive a Vector Packet with V2 V1 V0 = 001 and i2 i1 i0 = 000 or 010 (a Short Instruction Vector indicating a temporary address has been assigned to this pager). The system may send either and i 2 i1 i0 = 000 or and i2 i1 i0 = 010 or both when assigning a temporary address. The vector packet with and i2 i1 i0 = 000 will indicate which temporary address is assigned and the frame in which the temporary address is expected. The vector packet with and i2 i1 i0 = 010 will indicate which temporary address is assigned, the MSb of the expected frame (essentially indicating 64 frames in which to look for the temporary address), and a message sequence number. When the vector packet with and i2 i1 i0 = 010 is received on a long address, the specific assign frame is included in the mes-sage word sent after the vector. * The FLEXTM decoder II will increment the corresponding temporary address counter for each temporary address assignment vector received and begin to decode all of the follow-ing frames. Note that this implies a single dynamic group assignment that is implemented by sending two short instructions (one for each temporary address assignment mode of the short instruction vector) will cause the corresponding temporary address counter to incre-ment twice. * The FLEXTM decoder II continues to decode all of the frames and passes any address information, vector information and message information to the host followed by a status packet indicating the end of each frame and the current frame number. There are several scenarios which may occur with temporary addresses. 1. The temporary address is not found in the any of the assigned frames and therefore the host must terminate the temporary address mode by sending an All Frame Mode Packet to the FLEXTM decoder II with the "DTA" bit of the particular temporary address set (if both temporary address assignment packets were used to assign the temporary address, the "DTA" bit must be set twice to disable the temporary address). 2. The temporary address is found in the frame it was assigned and was not a fragmented message. Again, the host must terminate the temporary address mode by sending an All Frame Mode Packet to the FLEXTM decoder II with the "DTA" bit of the particular temporary address set (if both temporary address assignment packets were used to assign the temporary address, the "DTA" bit must be set twice to disable the temporary address). 3. The temporary address is found in the assigned frame and it is a fragmented message. In this case, the host must follow the rules for Operation of a Fragmented Message and determine the proper time to stop the all frame mode operation. In this case, the host must write to the "DAF" bit with a "1" and the appropriate "DTA" bit with a "1" in the All Frame Mode Register in order to terminate both the fragmented message and the temporary address (if both temporary address assignment packets were used to assign the temporary address, the "DTA" bit must be set twice to disable the temporary address). 487 * The above operation is repeated for every temporary address. 14.5.5 Using the Receiver Shutdown Packet The contents of this section apply to the FLEX Roaming Decoder. They are not applicable to the FLEX Non-Roaming Decoder. 1. Calculating Time Left The receiver shutdown packet gives timing information to the host. Two times are of particular interest when implementing a roaming algorithm. * TimeToWarmUpStart. Defined as the amount of time there is before the receiver will start to warm up (i.e. transition from the off state to the first warm up state). * TimeToTasksDisabled. Defined as the amount of time the host has to complete any host initiated tasks (e.g. by setting SND or SAS in the roaming control packet). The formula's for calculating these times depend on whether the FLEXTM decoder II is in synchronous mode or asynchronous mode. SYNCHRONOUS MODE: TimeToWarmUpStart (TNF * 80ms) + (SkippedFrames * 1874.375ms) + ReceiverOffTime -167.5ms TimeToTasksDisabled (TNF * 80ms) + (SkippedFrames * 1874.375ms) - 247.5ms ASYNCHRONOUS MODE: TimeToWarmUpStart ((TNF -2) * 80ms) + ReceiverOffTime TimeToTasksDisabled ((TNF -3) * 80 ms) Where, TNF: SkippedFrames: Time to Next Frame. Value from the receiver shutdown packet. The number of frames that won't be decoded. This can be calculated from the Current Frame (CF) and Next Needed Frame (NAF) fields in the receiver shutdown packet (e.g. If CF is 10 and NAF is 12, then SkippedFrames is 1) The time programmed in the receiver off setting packet. ReceiverOffTime: 488 2. Calculating How Long Tasks Take Since the TimeToTaskDisabled discussed in the previous section limits how much the host can do while the FLEXTM decoder II is battery saving, it is necessary for the host to know how long it can take the FLEXTM decoder II to perform a task. The formulas below calculate how long the two types of host initiated tasks take to complete as measured from the last SPI clock of the packet that initiates the task to the time the receiver shutdown sequence starts. Note that the receiver shutdown sequence must start before tasks are disabled. The following formula calculates how long it will take to complete a Noise Detect started by setting the SND bit in the roaming control packet. This formula assumes that (1) the noise detect was performed while in synchronous mode or (2) the noise detect was performed in asynchronous mode and did not find FLEX signal or (3) the noise detect found FLEX signal but the DAS bit of the roaming control packet was set. TimeToPerformNoiseDetect TotalWarmUpTime + 82ms Where, TotalWarmUpTime: The sum of the times programmed for the used warm up steps plus the time programmed for the 3200sps Sync Setting in the receiver control configuration packets. The following formula calculates how long it will take to complete an A-word search initiated by setting the SAS bit in the roaming control packet. This formula assumes that the A-word search failed to find roaming FLEX channel. TimeToPerformAwordSearch TotalWarmUpTime + AST + 47ms Where, TotalWarmUpTime: The sum of the times programmed for the used warm up steps plus the time programmed for the 3200sps Sync Setting in the receiver control configuration packets. AST: The value configured using the timing control packet. The following formula calculates how long it will take to complete a Noise Detect/A-word search combination. This can occur when the noise detect is performed while in asynchronous mode, the noise detect finds FLEX signal, and the DAS bit of the roaming control packet is not set. TimeToPerformBoth TotalWarmUpTime + AST +127ms Where, 489 TotalWarmUpTime: The sum of the times programmed for the used warm up steps plus the time programmed for the 3200sps Sync Setting in the receiver control configuration packets. AST: The value configured using the timing control packet. 490 14.6 Timing Diagrams (Reference Data) The following diagrams show the timing in a standalone FLEXTM Decoder II IC. They do not apply to this LSI, and should be used only for reference. 14.6.1 SPI Timing The following diagram and table describe the timing specifications of the SPI interface. SS READY tSSH tRDY tLEAD2 tLEAD1 SCK tCYC tR tF tLAG2 tLAG1 tRH tRS tSCKL MISO Hi-Z tSCKH D31 D0 Hi-Z tAC MOSI D31 tHI tSU tV tHO D0 tDIS Figure 14.13 SPI Timing 491 Table 14.34 SPI Timing (VCC = 2.7 V to 3.6 V, TA = -20C to 75C) Characteristic Operating Frequency Cycle Time Select Lead Time De-select Lag Time Select-to-Ready Time Select-to-Ready Time Re-select Time Ready High Time Ready Lead Time Not Ready Lag Time MOSI Data Setup Time MOSI Data Hold Time MISO Access Time MISO Disable Time MISO Data Valid Time MISO Data Hold Time SS High Time SCK High Time SCK Low Time SCK Rise Time SCK Fall Time 20% to 70% VDD 20% to 70% VDD CL =50pf CL =50pf CL =50pf previous packet did not program an address word* 2 CL =50pf Conditions Symbol f OP tCYC t LEAD1 t LAG1 t RDY Min*1 Max* 1 Unit dc 1000 200 200 80 420 30 50 200 200 200 200 0 200 300 200 0 200 300 300 1 1 1 MHz ns ns ns s s s s ns ns ns ns ns ns ns ns ns ns ns s s previous packet programmed an address t RDY word*2 CL =50pf previous packet was a checksum/special t RS packet* 3 CL =50pf t RH t LEAD2 t LAG2 t SU t HI t AC t DIS tV t HO t SSH t SCKH t SCKL tR tF Notes: *1 The specifications given in this data sheet indicate the minimum performance level of all FLEXTM decoders regardless of manufacturer. Individual manufacturers may have better performance than indicated. *2 When the host re-programs an address word with a Host-to-Decoder packet ID > 127 (decimal), there may be an added delay before the FLEXTM decoder II is ready for another packet. *3 When the host sends a checksum packet (ID is 00) or a special packet (ID is 1C through 1F hex) the t RS specification applies, otherwise the timing specifications for t LAG1 and tSSH govern the re-select timing. 492 14.6.2 Start-up Timing The following diagram and table describe the timing specifications of the FLEXTM decoder II when power is applied. VDD tSTART Oscillator RESET tRESET READY tRHRL Figure 14.14 Start-up Timing Table 14.35 Start-up Timing (VCC = 2.7 V to 3.6 V, TA = -20C to 75C) Characteristic Oscillator Start-up Time RESET Hold Time RESET High to READY Low Conditions Symbol t START t RESET t RHRL 200 76,800 76,800 Min*1 Max * 1 5 Unit sec ns T*2 Notes: *1 The specifications given in this data sheet indicate the minimum performance level of all manufacturers of the FLEXTM decoder II. Individual manufacturers may have better performance than indicated. *2 T is one period of the o DEC clock source. Note that from power-up, the oscillator start-up time can impact the availability and period of clock strobes. This can affect the actual RESET high to READY low timing. 493 14.6.3 Reset Timing The following diagram and table describe the timing specifications of the FLEXTM decoder II when it is reset. RESET tRL READY tRLRH tRHRL Figure 14.15 Reset Timing Table 14.36 Reset Timing (VCC = 2.7 V to 3.6 V, TA = -20C to 75C) Characteristic RESET Pulse Width RESET Low to READY High RESET High to READY Low Conditions Symbol t RL t RLRH t RHRL Min*1 200 - 76,800 Max* 1 - 200 76,800 Unit ns ns T*2 Notes: *1 The specifications given in this data sheet indicate the minimum performance level of all manufacturers of the FLEXTM decoder II. Individual manufacturers may have better performance than indicated. *2 T is one period of the o DEC clock source. 494 Section 15 A/D Converter 15.1 Overview The LSI incorporates a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. 15.1.1 Features A/D converter features are listed below * 10-bit resolution * Eight input channels * Settable analog conversion voltage range Conversion of analog voltages with the reference voltage pin (Vref ) as the analog reference voltage * High-speed conversion Minimum conversion time: 9.9 s per channel (at 13 MHz operation) * Choice of single mode or scan mode Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels * Four data registers Conversion results are held in a 16-bit data register for each channel * Sample and hold function * Three kinds of conversion start Choice of software or timer conversion start trigger (TPU or 8-bit timer), or ADTRG pin * A/D conversion end interrupt generation A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion * Module stop mode can be set As the initial setting, A/D converter operation is halted. Register access is enabled by exiting module stop mode. 495 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the A/D converter. Module data bus Bus interface A D D R A A D D R B A D D R C A D D R D A D C S R A D C R + Multiplexer - Comparator Sample-andhold circuit Control circuit Internal data bus AVCC Vref AVSS 10-bit D/A AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Successive approximations register o/2 o/4 o/8 o/16 ADTRG ADI interrupt Conversion start trigger from 8-bit timer or TPU ADCR : A/D control register ADCSR : A/D control/status register ADDRA : A/D data register A ADDRB : A/D data register B ADDRC : A/D data register C ADDRD : A/D data register D Figure 15.1 Block Diagram of A/D Converter 496 15.1.3 Pin Configuration Table 15.1 summarizes the input pins used by the A/D converter. The AVcc and AVss pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). Table 15.1 A/D Converter Pins Pin Name Analog power supply pin Analog ground pin Reference voltage pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Symbol AVcc AVss Vref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 I/O Input Input Input Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Group 1 analog inputs Function Analog block power supply Analog block ground and reference voltage A/D conversion reference voltage Group 0 analog inputs A/D external trigger input pin ADTRG 497 15.1.4 Register Configuration Table 15.2 summarizes the registers of the A/D converter. Table 15.2 A/D Converter Registers Name A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Module stop control register A Abbreviation ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR MSTPCRA R/W R R R R R R R R R/(W)* R/W R/W 2 Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'33 H'3F Address* 1 H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FDE8 Notes: *1 Lower 16 bits of the address. *2 Bit 7 can only be written with 0 for flag clearing. 498 15.2 15.2.1 Bit Register Descriptions A/D Data Registers A to D (ADDRA to ADDRD) : 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- Initial value : R/W : There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. Bits 5 to 0 are always read as 0. The correspondence between the analog input channels and ADDR registers is shown in table 15.3. ADDR can always be read by the CPU. The upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section 15.3, Interface to Bus Master. The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop mode. Table 15.3 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD 499 15.2.2 Bit A/D Control/Status Register (ADCSR) : 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 -- 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Initial value : R/W : Note: * Only 0 can be written to bit 7, to clear this flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations. ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode. Bit 7--A/D End Flag (ADF): Status flag that indicates the end of A/D conversion. Bit 7 ADF 0 Description [Clearing conditions] * * 1 When 0 is written to the ADF flag after reading ADF = 1 When the DTC is activated by an ADI interrupt and ADDR is read (Initial value) [Setting conditions] * * Single mode: When A/D conversion ends Scan mode: When A/D conversion ends on all specified channels Bit 6--A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests at the end of A/D conversion. Bit 6 ADIE 0 1 Description A/D conversion end interrupt (ADI) request disabled A/D conversion end interrupt (ADI) request enabled (Initial value) 500 Bit 5--A/D Start (ADST): Selects starting or stopping on A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST 0 1 Description * * * A/D conversion stopped (Initial value) Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. Bit 4--Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating mode. See section 15.4, Operation, for single mode and scan mode operation. Only set the SCAN bit while conversion is stopped. Bit 4 SCAN 0 1 Description Single mode Scan mode (Initial value) Bit 3--Reserved: 0 should be written to this bit. Bits 2 to 0--Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input channels. Only set the input channel while conversion is stopped (ADST = 0). 501 Group Selection CH2 0 Channel Selection CH1 0 CH0 0 1 1 0 1 Single Mode (SCAN = 0) AN0 (Initial value) AN1 AN2 AN3 AN4 AN5 AN6 AN7 Description Scan Mode (SCAN = 1) AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 1 0 0 1 1 0 1 15.2.3 Bit A/D Control Register (ADCR) : 7 TRGS1 0 R/W 6 TRGS0 0 R/W 5 -- 1 -- 4 -- 1 -- 3 CKS1 0 R/W 2 CKS0 0 R/W 1 -- 1 -- 0 -- 1 -- Initial value : R/W : ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations and sets the A/D conversion time. ADCR is initialized to H'33 by a reset, and in standby mode or module stop mode. Bits 7 and 6--Timer Trigger Select 1 and 0 (TRGS1, TRGS0): Select enabling or disabling of the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped (ADST = 0). Bit 7 TRGS1 0 Bit 6 TRGS0 0 1 1 0 1 Description A/D conversion start by software is enabled (Initial value) A/D conversion start by TPU conversion start trigger is enabled A/D conversion start by 8-bit timer conversion start trigger is enabled A/D conversion start by external trigger pin (ADTRG) is enabled Bits 5, 4, 1, and 0--Reserved: These bits cannot be modified and are always read as 1. 502 Bits 3 and 2--Clock Select 1 and 0 (CKS1, CKS0): These bits select the A/D conversion time. The conversion time should be changed only when ADST = 0. The conversion time setting should be less than or equal to the conversion times shown in section 20.2.4, A/D Conversion Characteristics. Bit 3 CKS1 0 Bit 2 CKS0 0 1 1 0 1 Description Conversion time = 530 states (max.) Conversion time = 260 states (max.) Conversion time = 134 states (max.) Conversion time = 68 states (max.) (Initial value) 15.2.4 Bit Module Stop Control Register A (MSTPCRA) : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : MSTPCRA is an 8-bit readable/writable register that performs module stop mode control. When the MSTPA1 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 19.5, Module Stop Mode. MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 1--Module Stop (MSTPA1): Specifies the A/D converter module stop mode. Bit 1 MSTPA1 0 1 Description A/D converter module stop mode cleared A/D converter module stop mode set (Initial value) 503 15.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading ADDR, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 15.2 shows the data flow for ADDR access. Upper byte read Bus master (H'AA) Bus interface Module data bus TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Lower byte read Bus master (H'40) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Figure 15.2 ADDR Access Operation (Reading H'AA40) 504 15.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. 15.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1, according to the software or external trigger input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 15.3 shows a timing diagram for this example. [1] Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = 0, CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). [2] When A/D conversion is completed, the result is transferred to ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. [3] Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. [4] The A/D interrupt handling routine starts. [5] The routine reads ADCSR, then writes 0 to the ADF flag. [6] The routine reads and processes the connection result (ADDRB). [7] Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps [2] to [7] are repeated. 505 Set* ADIE ADST ADF State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Idle Idle Idle Idle A/D conversion 1 A/D conversion starts Set* Clear* Set* Clear* Idle A/D conversion 2 Idle ADDRA ADDRB ADDRC ADDRD Read conversion result A/D conversion result 1 Read conversion result A/D conversion result 2 Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) 506 15.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by a software, timer or external trigger input, A/D conversion starts on the first channel in the group (AN0). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDR registers corresponding to the channels. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again from the first channel (AN0). The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described next. Figure 15.4 shows a timing diagram for this example. [1] Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). [2] When A/D conversion of the first channel (AN0) is completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. [3] Conversion proceeds in the same way through the third channel (AN2). [4] When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. [5] Steps [2] to [4] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). 507 Continuous A/D conversion execution Set*1 ADST ADF A/D conversion time State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Transfer ADDRA ADDRB ADDRC ADDRD Notes: *1 Vertical arrows ( ) indicate instructions executed by software. *2 Data currently being converted is ignored. A/D conversion result 1 A/D conversion result 4 A/D conversion result 2 A/D conversion result 3 Idle Idle Idle A/D conversion 1 Clear*1 Clear*1 Idle A/D conversion 2 A/D conversion 4 Idle A/D conversion 5 *2 Idle A/D conversion 3 Idle Idle Idle Figure 15.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) 508 15.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 15.5 shows the A/D conversion timing. Table 15.4 indicates the A/D conversion time. As indicated in figure 15.5, the A/D conversion time includes t D and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 15.4. In scan mode, the values given in table 15.4 apply to the first conversion time. The values given in table 15.5 apply to the second and subsequent conversions. (1) o Address bus (2) Write signal Input sampling timing ADF tD t SPL t CONV Legend (1) : (2) : : tD tSPL : tCONV : ADCSR write cycle ADCSR address A/D conversion start delay Input sampling time A/D conversion time Figure 15.5 A/D Conversion Timing 509 Table 15.4 A/D Conversion Time (Single Mode) CKS1 = 0 CKS0 = 0 Item CKS0 = 1 CKS1 = 1 CKS0 = 0 CKS0 = 1 Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max 18 -- -- 33 10 -- -- 63 17 -- 6 -- -- 31 9 -- 4 -- -- 15 -- 5 -- 68 A/D conversion start delay t D Input sampling time A/D conversion time t SPL t CONV 127 -- 515 -- 530 259 -- 266 131 -- 134 67 Note: Values in the table are the number of states. Table 15.5 A/D Conversion Time (Scan Mode) CKS1 0 CKS0 0 1 1 0 1 Conversion Time (State) 512 (Fixed) 256 (Fixed) 128 (Fixed) 64 (Fixed) 15.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are respectively set to 1 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit has been set to 1 by software. Figure 15.6 shows the timing. o ADTRG Internal trigger signal ADST A/D conversion Figure 15.6 External Trigger Input Timing 510 15.5 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC can be activated by an ADI interrupt. Having the converted data read by the DTC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. The A/D converter interrupt source is shown in table 15.6. Table 15.6 A/D Converter Interrupt Source Interrupt Source ADI Description Interrupt due to end of conversion DTC Activation Possible 15.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins: (1) Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss ANn Vref. (2) Relation between AVcc, AVss and Vcc, Vss As the relationship between AVcc, AVss and Vcc, Vss, set AVss = Vss. If the A/D converter is not used, the AVCC and AVSS pins must on no account be left open. (3) Vref input range The analog reference voltage input at the Vref pin set in the range Vref AVcc. If conditions (1), (2), and (3) above are not met, the reliability of the device may be adversely affected. Notes on Board Design: In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. 511 Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), analog reference power supply (Vref), and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable digital ground (Vss) on the board. Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) and analog reference power supply (Vref) should be connected between AVcc and AVss as shown in figure 15.7. Also, the bypass capacitors connected to AVcc and Vref and the filter capacitor connected to AN0 to AN7 must be connected to AVss. If a filter capacitor is connected as shown in figure 15.7, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin ), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC Vref Rin* 2 *1 *1 0.1 F 100 AN0 to AN7 AVSS Notes: Values are reference values. *1 10 F 0.01 F *2 Rin: Input impedance Figure 15.7 Example of Analog Input Protection Circuit 512 Table 15.7 Analog Pin Specifications Item Analog input capacitance Permissible signal source impedance Note: * When V CC = 2.7 V to 3.6 V Min -- -- Max 20 5* Unit pF k 10 k AN0 to AN7 To A/D converter 20 pF Note: Values are reference values. Figure 15.8 Analog Input Pin Equivalent Circuit A/D Conversion Precision Definitions: LSI A/D conversion precision definitions are given below. * Resolution The number of A/D converter digital output codes * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 15.10). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 15.10). * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 15.9). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error. * Absolute precision The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. 513 Digital output 111 110 101 100 011 010 001 000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 1024 1024 FS Analog input voltage Figure 15.9 A/D Conversion Precision Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 15.10 A/D Conversion Precision Definitions (2) 514 Permissible Signal Source Impedance: LSI analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion precision. However, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater). When converting a high-speed analog signal, a low-impedance buffer should be inserted. Influences on Absolute Precision: Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVSS. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. LSI Sensor output impedance up to 5 k Sensor input Low-pass filter C up to 0.1 F Cin = 15 pF A/D converter equivalent circuit 10 k 20 pF Note: Values are reference values. Figure 15.11 Example of Analog Input Circuit 515 516 Section 16 RAM 16.1 Overview The LSI has 16 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer. The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR). 16.1.1 Block Diagram Figure 16.1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FFB000 H'FFB002 H'FFB004 H'FFB001 H'FFB003 H'FFB005 H'FFEFBE H'FFFFC0 H'FFEFBF H'FFFFC1 H'FFFFFE H'FFFFFF Figure 16.1 Block Diagram of RAM 517 16.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 16.1 shows the address and initial value of SYSCR. Table 16.1 RAM Register Name System control register Abbreviation SYSCR R/W R/W Initial Value H'01 Address* H'FDE5 Note: * Lower 16 bits of the address. 16.2 16.2.1 Bit Register Descriptions System Control Register (SYSCR) : 7 -- 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W 3 0 R/W 2 0 R/W 1 -- 0 -- 0 RAME 1 R/W NMIEG MRESE Initial value : R/W : The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in SYSCR, see section 3.2.2, System Control Register (SYSCR). Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) Note: When the DTC is used, the RAME bit must be set to 1. 518 16.3 Operation When the RAME bit is set to 1, accesses to addresses H'FFB000 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in the LSI is directed to the on-chip RAM. When the RAME bit is cleared to 0, the offchip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or word units. Each type of access can be performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address. 16.4 Usage Note DTC register information can be located in addresses H'FFEBC0 to H'FFEFBF. When the DTC is used, the RAME bit must not be cleared to 0. 519 520 Section 17 ROM 17.1 Overview The LSI has 128 kbytes of on-chip ROM (flash memory). The ROM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in one state, making possible rapid instruction fetches and high-speed processing. The on-chip ROM is enabled or disabled by setting the mode pins (MD2, MD1, and MD0). The flash memory versions can be erased and programmed on-board as well as with a PROM programmer. 17.1.1 Block Diagram Figure 17.1 shows a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000002 H'000001 H'000003 H'01FFFE H'01FFFF Figure 17.1 Block Diagram of ROM 521 17.1.2 Register Configuration This LSI's on-chip ROM is controlled by the mode pins. The register configuration is shown in table 17.1. Table 17.1 ROM Register Name Mode control register Abbreviation MDCR R/W R/W Initial Value Undefined Address* H'FDE7 Note: * Lower 16 bits of the address. 17.2 17.2.1 Bit Register Descriptions Mode Control Register (MDCR) : 7 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 MDS2 --* R 1 MDS1 --* R 0 MDS0 --* R Initial value R/W : : 1 -- Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit read-only register that indicates the current operating mode of the LSI. Bit 7--Reserved: This bit cannot be modified and is always read as 1. Bits 6 to 3--Reserved: These bits cannot be modified and are always read as 0. Bits 2 to 0--Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to MD0. MDS2 to MDS0 are read-only bits, and cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a power-on reset. 17.3 Operation The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. Word data must start at an even address. The on-chip ROM is enabled and disabled by setting the mode pins (MD2, MD1, and MD0). These settings are shown in table 17.2. 522 Table 17.2 Operating Modes and ROM Area (F-ZTAT version) Mode Pin Operating Mode Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Mode 8 Mode 9 Mode 10 Mode 11 Mode 12 Mode 13 Mode 14 User program mode (advanced expanded mode with on-chip ROM enabled)* 1 User program mode (advanced single-chip mode)* 2 1 Boot mode (advanced expanded mode with on-chip ROM enabled)* 1 Boot mode (advanced single-chip mode)*2 -- 1 0 1 Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode -- 1 0 0 1 1 0 1 -- FWE MD2 MD1 MD0 On-Chip ROM 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Enabled (128 kbytes)* 1 Enabled (128 kbytes)* 2 Enabled (128 kbytes)* 2 -- Enabled (128 kbytes)* 1 Enabled (128 kbytes)* 1 -- Disabled -- Mode 15 1 Enabled (128 kbytes)* 1 Notes: *1 Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced expanded mode with on-chip ROM enabled. *2 Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced single-chip mode. 523 17.4 17.4.1 Overview of Flash Memory Features The LSI has 128 kbytes of on-chip flash memory. The features of the flash memory are summarized below. * Four flash memory operating modes Program mode Erase mode Program-verify mode Erase-verify mode * Programming/erase methods The flash memory is programmed 128 bytes at a time. Block erase (in single-block units) can be performed. To erase multiple blocks, each block must be erased in turn. Block erasing can be performed as required on 1 kbyte, 8 kbytes, 16 kbytes, 28 kbytes, and 32 kbytes blocks. * Programming/erase times The flash memory programming time is 10 ms (typ.) for simultaneous 128-byte programming, equivalent approximately to 80 s (typ.) per byte, and the erase time is 100 ms (typ.). * Reprogramming capability The flash memory can be reprogrammed up to 100 times. * On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: Boot mode User program mode * Automatic bit rate adjustment With data transfer in boot mode, the LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Flash memory emulation in RAM Flash memory programming can be emulated in real time by overlapping a part of RAM onto flash memory. * Protect modes There are three protect modes, hardware, software, and error protection, which allow protected status to be designated for flash memory program/erase/verify operations. * Programmer mode Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode. 524 17.4.2 Block Diagram Internal address bus Internal data bus (16 bits) Module bus FLMCR1 FLMCR2 EBR1 EBR2 RAMER FLPWCR Bus interface/controller Operating mode FWE pin Mode pin Flash memory (128 kbytes) Legend FLMCR1: FLMCR2: EBR1: EBR2: RAMER: FLPWCR: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Flash memory power control register Figure 17.2 Block Diagram of Flash Memory 525 17.4.3 Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the microcomputer enters an operating mode as shown in figure 17.3. In user mode, flash memory can be read but not programmed or erased. Transitions between user mode and user program mode should only be made when the CPU is not accessing the flash memory. The boot, user program and programmer modes are provided as modes to write and erase the flash memory. MD1 = 1, MD2 = 1, FWE = 0 *1 User mode (on-chip ROM enabled) RES = 0 Reset state RES = 0 MD1 = 1, MD2 = 1, FWE = 1 RES = 0 MD1 = 1, MD2 = 0, FWE = 1 RES = 0 Programmer mode *2 FWE = 1 FWE = 0 User program mode *1 Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. *1 RAM emulation possible *2 MD0 = 0, MD1 = 0, MD2 = 0, P14 = 0, P16 = 0, PF0 = 1, PF3 = 1 Figure 17.3 Flash Memory State Transitions 526 17.4.4 On-Board Programming Modes Boot Mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the LSI (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host " ! , Programming control program New application program New application program Host LSI LSI Boot program SCI Boot program SCI Flash memory RAM Flash memory RAM Boot program area Programming control program Application program (old version) Application program (old version) 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks. Host 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host New application program LSI LSI Boot program SCI Boot program SCI Flash memory RAM Flash memory RAM Boot program area Programming control program Boot program area Programming control program Flash memory preprogramming erase New application program Program execution state Figure 17.4 Boot Mode 527 User Program Mode 1. Initial state The FWE assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. Host Programming/ erase control program New application program 2. Programming/erase control program transfer When user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to RAM. , , Host New application program LSI LSI Boot program SCI Boot program SCI Flash memory RAM Flash memory RAM FWE assessment program FWE assessment program Transfer program Transfer program Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. Host 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host New application program LSI LSI Boot program SCI Boot program SCI Flash memory RAM Flash memory RAM FWE assessment program Transfer program FWE assessment program Transfer program Programming/ erase control program Programming/ erase control program Flash memory erase New application program Program execution state Figure 17.5 User Program Mode 528 17.4.5 Flash Memory Emulation in RAM Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. SCI Flash memory Emulation block RAM Overlap RAM (emulation is performed on data written in RAM) Application program Execution state Figure 17.6 Reading Overlap RAM Data in User Mode or User Program Mode When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten. 529 SCI Flash memory Programming data RAM Application program Overlap RAM (programming data) Programming control program execution state Figure 17.7 Writing Overlap RAM Data in User Program Mode 17.4.6 Differences between Boot Mode and User Program Mode Table 17.3 Differences between Boot Mode and User Program Mode Boot Mode Total erase Block erase Programming control program* Yes No (2) User Program Mode Yes Yes (1) (2) (3) (1) Erase/erase-verify (2) Program/program-verify (3) Emulation Note: * To be provided by the user, in accordance with the recommended algorithm. 530 17.4.7 Block Configuration The flash memory is divided into four 1 kbyte blocks, one 28 kbytes block, one 16 kbytes block, two 8 kbytes blocks, and two 32 kbytes blocks. Erasure is performed in this unit. Address H'00000 1 kbyte x 4 28 kbytes 16 kbytes 8 kbytes 128 kbytes 8 kbytes 32 kbytes 32 kbytes Address H'1FFFF Figure 17.8 Flash Memory Block Configuration 531 17.5 Pin Configuration The flash memory is controlled by means of the pins shown in table 17.4. Table 17.4 Pin Configuration Pin Name Reset Flash write enable Mode 2 Mode 1 Mode 0 Port F3 Port F0 Port 16 Port 14 Transmit data Receive data Abbreviation I/O RES FWE MD2 MD1 MD0 PF3 PF0 P16 P14 TxD0 RxD0 Input Input Input Input Input Input Input Input Input Output Input Function Reset Flash memory program/erase protection by hardware Sets LSI operating mode Sets LSI operating mode Sets LSI operating mode Sets LSI operating mode when MD2 = MD1 = MD0 =0 Sets LSI operating mode when MD2 = MD1 = MD0 =0 Sets LSI operating mode when MD2 = MD1 = MD0 =0 Sets LSI operating mode when MD2 = MD1 = MD0 =0 Serial transmit data output Serial receive data input 532 17.6 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 17.5. In order to access these registers, the FLSHE bit in SCRX must be set to 1 (except for RAMER, SCRX). Table 17.5 Register Configuration Register Name Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Abbreviation FLMCR1* 5 FLMCR2* 5 EBR1 * 5 EBR2 * 5 RAMER*5 R/W R/W*2 R*2 R/W*2 R/W*2 R/W R/W R/W Initial Value H'00* 3 H'00 H'00* 4 H'00* 4 H'00 H'00 H'00 Address* 1 H'FFA8 H'FFA9 H'FFAA H'FFAB H'FEDB H'FFAC H'FDB4 Flash memory power control register FLPWCR* 5 Serial control register X SCRX Notes: *1 Lower 16 bits of the address. *2 To access these registers, set the FLSHE bit to 1 in serial control register X. Even if FLSHE is set to 1, if the chip is in a mode in which the on-chip flash memory is disabled, a read will return H'00 and writes are invalid. Writes are also invalid when the FWE bit in FLMCR1 is not set to 1. *3 When a high level is input to the FWE pin, the initial value is H'80. *4 When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in FLMCR1 is not set, these registers are initialized to H'00. *5 FLMCR1, FLMCR2, EBR1, EBR2, RAMER, and FLPWCR are 8-bit registers. Only byte access can be used on these registers, with the access requiring two states. 533 17.7 17.7.1 Bit Register Descriptions Flash Memory Control Register 1 (FLMCR1) : 7 FWE 6 SWE1 0 R/W 5 ESU1 0 R/W 4 PSU1 0 R/W 3 EV1 0 R/W 2 PV1 0 R/W 1 E1 0 R/W 0 P1 0 R/W Initial value R/W : : --* R Note: * Determined by the state of the FWE pin. FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'00000 to H'1FFFF is entered by setting SWE1 bit to 1 when FWE = 1, then setting the PV1 or EV1 bit. Program mode for addresses H'00000 to H'1FFFF is entered by setting SWE1 bit to 1 when FWE = 1, then setting the PSU1 bit, and finally setting the P1 bit. Erase mode for addresses H'00000 to H'1FFFF is entered by setting SWE1 bit to 1 when FWE = 1, then setting the ESU1 bit, and finally setting the E1 bit. FLMCR1 is initialized by a power-on reset, and in hardware standby mode and software standby mode. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes are enabled only in the following cases: Writes to bit SWE1 of FLMCR1 enabled when FWE = 1, to bits ESU1, PSU1, EV1, and PV1 when FWE = 1 and SWE1 = 1, to bit E1 when FWE = 1, SWE1 = 1 and ESU1 = 1, and to bit P1 when FWE = 1, SWE1 = 1, and PSU1 = 1. Bit 7--Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing. Bit 7 FWE 0 1 Description When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin 534 Bit 6--Software Write Enable Bit 1 (SWE1): Enables or disables flash memory programming and erasing. Set this bit when setting bits 5 to 0, bits 7 to 0 of EBR1, and bits 3 to 0 of EBR2. Bit 6 SWE1 0 1 Description Writes disabled Writes enabled [Setting condition] When FWE = 1 (Initial value) Bit 5--Erase Setup Bit 1 (ESU1): Prepares for a transition to erase mode. Set this bit to 1 before setting the E1 bit in FLMCR1 to 1. Do not set the SWE1, PSU1, EV1, PV1, E1, or P1 bit at the same time. Bit 5 ESU1 0 1 Description Erase setup cleared Erase setup [Setting condition] When FWE = 1 and SWE1 = 1 (Initial value) Bit 4--Program Setup Bit 1 (PSU1): Prepares for a transition to program mode. Set this bit to 1 before setting the P1 bit in FLMCR1 to 1. Do not set the SWE1, ESU1, EV1, PV1, E1, or P1 bit at the same time. Bit 4 PSU1 0 1 Description Program setup cleared Program setup [Setting condition] When FWE = 1 and SWE1 = 1 (Initial value) 535 Bit 3--Erase-Verify 1 (EV1): Selects erase-verify mode transition or clearing. Do not set the SWE1, ESU1, PSU1, PV1, E1, or P1 bit at the same time. Bit 3 EV1 0 1 Description Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE1 = 1 (Initial value) Bit 2--Program-Verify 1 (PV1): Selects program-verify mode transition or clearing. Do not set the SWE1, ESU1, PSU1, EV1, E1, or P1 bit at the same time. Bit 2 PV1 0 1 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] When FWE = 1 and SWE1 = 1 (Initial value) Bit 1--Erase 1 (E1): Selects erase mode transition or clearing. Do not set the SWE1, ESU1, PSU1, EV1, PV1, or P1 bit at the same time. Bit 1 E1 0 1 Description Erase mode cleared Transition to erase mode [Setting condition] When FWE = 1, SWE1 = 1, and ESU1 = 1 (Initial value) 536 Bit 0--Program 1 (P1): Selects program mode transition or clearing. Do not set the SWE1, PSU1, ESU1, EV1, PV1, or E1 bit at the same time. Bit 0 P1 0 1 Description Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE1 = 1, and PSU1 = 1 (Initial value) 17.7.2 Bit Flash Memory Control Register 2 (FLMCR2) : 7 FLER 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R Initial value R/W : : 0 R Note: FLMCR2 is a read-only register, and should not be written to. FLMCR2 is an 8-bit register used for flash memory operating mode control. FLMCR2 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00. Bit 7--Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state. Bit 7 FLER 0 Description Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Power-on reset or hardware standby mode 1 An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See 17.10.3 Error Protection (Initial value) Bits 6 to 0--Reserved: These bits always read 0. 537 17.7.3 Bit Erase Block Register 1 (EBR1) : : : 7 EB7 0 R/W 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W 0 EB0 0 R/W Initial value R/W EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE1 bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically cleared to 0. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 17.6. 17.7.4 Bit Erase Block Register 2 (EBR2) : 7 -- 6 -- 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 -- 0 R/W 2 -- 0 R/W 1 EB9 0 R/W 0 EB8 0 R/W Initial value R/W : : 0 R/W EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE1 bit in FLMCR1 is not set. When a bit in EBR2 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically cleared to 0. Bits 7 to 2 are reserved and must only be written with 0. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. 538 The flash memory block configuration is shown in table 17.6. Table 17.6 Flash Memory Erase Blocks Block (Size) EB0 (1 kbyte) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbyte) EB4 (28 kbytes) EB5 (16 kbytes) EB6 (8 kbytes) EB7 (8 kbytes) EB8 (32 kbytes) EB9 (32 kbytes) Addresses H'000000-H'0003FF H'000400-H'0007FF H'000800-H'000BFF H'000C00-H'000FFF H'001000-H'007FFF H'008000-H'00BFFF H'00C000-H'00DFFF H'00E000-H'00FFFF H'010000-H'017FFF H'018000-H'01FFFF 17.7.5 Bit RAM Emulation Register (RAMER) : 7 -- 6 -- 0 R 5 -- 0 R 4 -- 0 R/W 3 RAMS 0 R/W 2 -- 0 R/W 1 RAM1 0 R/W 0 RAM0 0 R/W Initial value R/W : : 0 R RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized in software standby mode. RAMER settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 17.7. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bits 7 to 5--Reserved: These bits always read 0. Bits 4 and 2--Reserved: Only 0 may be written to these bits. 539 Bit 3--RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory block are program/erase-protected. Bit 3 RAMS 0 Description Emulation not selected Program/erase-protection of all flash memory blocks is disabled 1 Emulation selected Program/erase-protection of all flash memory blocks is enabled (Initial value) Bits 1 and 0--Flash Memory Area Selection: These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM. (See table 17.7.) Table 17.7 Flash Memory Area Divisions Addresses H'FFD000-H'FFD3FF H'000000-H'0003FF H'000400-H'0007FF H'000800-H'000BFF H'000C00-H'000FFF Block Name RAM area 1 kbyte EB0 (1 kbyte) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbyte) RAMS 0 1 1 1 1 RAM1 * 0 0 1 1 RAM0 * 0 1 0 1 *: Don't care 17.7.6 Flash Memory Power Control Register (FLPWCR) Bit: 7 PDWND Initial value: R/W: 0 R/W 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. FLPWCR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. 540 Bit 7--Power-Down Disable (PDWND): Enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. Bit 7 PDWND 0 1 Description Transition to flash memory power-down mode enabled Transition to flash memory power-down mode disabled (Initial value) Note: PDWND is valid only when the LSI is in subactive mode or subsleep mode, and is invalid in other modes. Bits 6 to 0--Reserved: These bits always read 0. 17.7.7 Bit Serial Control Register X (SCRX) : 7 -- 6 -- 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 FLSHE 0 R/W 2 -- 0 R/W 1 -- 0 R/W 0 -- 0 R/W Initial value R/W : : 0 R/W SCRX is an 8-bit readable/writable register that performs on-chip flash memory control. SCRX is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 4, 2 to 0--Reserved: Only 0 may be written to these bits. Bit 3--Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Setting the FLSHE bit to 1 enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash memory control register contents are retained. Bit 3 FLSHE 0 1 Description Flash control registers deselected in area H'FFFFA8 to H'FFFFAC Flash control registers selected in area H'FFFFA8 to H'FFFFAC (Initial value) 541 17.8 On-Board Programming Modes When pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 17.8. For a diagram of the transitions to the various flash memory modes, see figure 17.3. Table 17.8 Setting On-Board Programming Modes Mode Boot mode Expanded mode Single-chip mode User program mode Expanded mode Single-chip mode 1 FWE 1 MD2 0 0 1 1 MD1 1 1 1 1 MD0 0 1 0 1 17.8.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The SCI channel to be used is set to asynchronous mode. When a reset-start is executed after the LSI's pins have been set to boot mode, the boot program built into the LSI is started and the programming control program prepared in the host is serially transmitted to the LSI via the SCI. In the LSI, the programming control program received via the SCI is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 17.9, and the boot mode execution procedure in figure 17.10. 542 LSI Flash memory Host Write data reception Verify data transmission RxD0 SCI0 TxD0 On-chip RAM Figure 17.9 System Configuration in Boot Mode If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error indication, and the erase operation and subsequent operations are halted. When a transition is made to boot mode, or from boot mode to another mode, mode switching must be carried out by means of RES input. The states of ports with multiplexed address functions and bus control output signals (AS, RD, WR) change during the switchover period (while a low level is being input at the RES pin), and therefore these pins should not be used for output signals during this period. 543 Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate LSI measures low period of H'00 data transmitted by host LSI calculates bit rate and sets value in bit rate register After bit rate adjustment, LSI transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, LSI transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte LSI transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units LSI transmits received programming control program to host as verify data (echo-back) Transfer received programming control program to on-chip RAM No Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, LSI transmits one H'AA data byte to host Execute programming control program transferred to on-chip RAM n+1n n = N? Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Figure 17.10 Boot Mode Execution Procedure 544 Automatic SCI Bit Rate Adjustment Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 17.11 Automatic SCI Bit Rate Adjustment When boot mode is initiated, the LSI measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The LSI calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the LSI. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host's transmission bit rate and the LSI's system clock frequency, there will be a discrepancy between the bit rates of the host and the LSI. Set the host transfer bit rate at 4,800, 9,600, or 19,200 bps to operate the SCI properly. Table 17.9 shows host transfer bit rates and system clock frequencies for which automatic adjustment of the LSI bit rate is possible. The boot program should be executed within this system clock range. Table 17.9 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate 4,800 bps 9,600 bps 19,200 bps System Clock Frequency for Which Automatic Adjustment of LSI Bit Rate is Possible 2 MHz to 13.5 MHz 4 MHz to 13.5 MHz 8 MHz to 13.5 MHz 545 On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the programming control program is transferred via the SCI, as shown in figure 17.12. The boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host. H'FFC000 Programming control program area (8 kbytes) H'FFDFFF H'FFE000 Boot program area (4 kbytes) H'FFEFBF Note: The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note also that the boot program remains in this area of the on-chip RAM even after control branches to the programming control program. Figure 17.12 RAM Areas in Boot Mode Notes on Use of Boot Mode: * When the chip comes out of reset in boot mode, it measures the low-level period of the input at the SCI's RxD0 pin. The reset should end with RxD0 high. After the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period of the RxD0 pin. * In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. * Interrupts cannot be used while the flash memory is being programmed or erased. * The RxD0 and TxD0 pins should be pulled up on the board. * Before branching to the programming control program (RAM area H'FFC000), the chip terminates transmit and receive operations by the on-chip SCI (channel 0) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD0, goes to the high-level output state (P30DDR = 1, P30DR = 1). 546 The contents of the CPU's internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. Initial settings must also be made for all other on-chip registers. * Boot mode can be entered by making the pin settings shown in table 17.8 and executing a reset-start. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the FWE pin and mode pins, and executing reset release*1. Boot mode can also be cleared by a WDT overflow reset. Do not change the mode pin input levels in boot mode, and do not drive the FWE pin low while the boot program is being executed or while flash memory is being programmed or erased* 2. * If the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR) will change according to the change in the microcomputer's operating mode*3. Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. Notes: *1 Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS = 200 ns) with respect to the reset release timing. *2 For further information on FWE application and disconnection, see section 17.15, Flash Memory Programming and Erasing Precautions. *3 See appendix D, Pin States. 17.8.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary. To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7), and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7. The flash memory itself cannot be read while the SWE1 bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM or external memory. 547 Figure 17.13 shows the procedure for executing the program/erase control program when transferred to on-chip RAM. Write the FWE assessment program and transfer program (and the program/erase control program if necessary) beforehand MD2, MD1, MD0 = 110, 111 Reset-start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area FWE = high* Execute program/erase control program (flash memory rewriting) Clear FWE* Branch to flash memory application program Notes: Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only when the flash memory is programmed or erased. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * For further information on FWE application and disconnection, see section 17.15, Flash Memory Programming and Erasing Precautions. Figure 17.13 User Program Mode Execution Procedure 548 17.9 Programming/Erasing Flash Memory A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes are made by setting the PSU1, ESU1, P1, E1, PV1, and EV1 bits in FLMCR1 for addresses H'000000 to H'01FFFF. The flash memory cannot be read while it is being written or erased. Install the program to control flash memory programming and erasing (programming control program) in the on-chip RAM, in external memory, and execute the program from there. Notes: 1. Operation is not guaranteed if bits SWE1, ESU1, PSU1, EV1, PV1, E1, and P1 of FLMCR1 are set/reset by a program in flash memory in the corresponding address areas. 2. When programming or erasing, set FWE to 1 (programming/erasing will not be executed if FWE = 0). 3. Programming should be performed in the erased state. Do not perform additional programming on previously programmed addresses. 17.9.1 Program Mode Follow the procedure shown in the program/program-verify flowchart in figure 17.14 to write data or programs to flash memory. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a time. For the wait times (tsswe, tspsu , tsp10, tsp30, tsp200, tcp , tcpsu, tspv, tspvr, tcpv , tcswe) after bits are set or cleared in flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N), see 20.2.5, Flash Memory Characteristics. Following the elapse of (tsswe ) s or more after the SWE1 bit is set to 1 in flash memory control register 1 (FLMCR1), 128-byte data is stored in the program data area and reprogram data area, and the 128-byte data in the program data area in RAM is written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00 or H'80. 128 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than (tspsu + tsp200 + tcp + tcpsu) s as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU1 bit in FLMCR1, and after the elapse of (tspsu) s or more, the operating mode is switched to program mode by 549 setting the P1 bit in FLMCR1. The time during which the P1 bit is set is the flash memory programming time. Set the programming time according to the table in the programming flowchart. 17.9.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of a given programming time, the programming mode is exited (the P1 bit in FLMCR1 is cleared, then the PSU1 bit is cleared at least (tcp ) s later). The watchdog timer is cleared after the elapse of (tcpsu) s or more, and the operating mode is switched to program-verify mode by setting the PV1 bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (tspv) s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (tspvr) s after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 17.14) and transferred to the reprogram data area. After 128 bytes of data have been verified, exit program-verify mode, wait for at least (tcpv) s, then clear the SWE1 bit in FLMCR1 to 0. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits. 550 Subroutine: Write Pulse Start of subroutine Enable WDT Set PSU1 bit in FLMCR1 tspsu: Wait 50 s Set P1 bit in FLMCR1 n=1 Wait: tsp10, tsp30, or tsp200 Clear P1 bit in FLMCR1 tcp: Wait 5 s Clear PSU1 bit in FLMCR1 tcpsu: Wait 5 s Disable WDT tspv: Wait 4 s Return Perform H'FF dummy-write to verify address Note: *6 Write Pulse Width Write Pulse (tsp30 or tsp200) Set PV1 bit in FLMCR1 *5 m=0 Successively write 128-byte data from reprogram data area in RAM to flash memory *1 Subroutine call See Note *6 for pulse width Start Set SWE1 bit in FLMCR1 tsswe: Wait 1 s Store 128 bytes program data in program data area and reprogram data area *4 Data writes must be performed in the memory-erased state. Do not write additional data to an address to which data is already written. Number of Writes n 1 2 3 4 5 6 7 8 9 10 11 12 13 . . . 998 999 1000 Write Time (tsp30/tsp200)s tsp30 tsp30 tsp30 tsp30 tsp30 tsp30 tsp200 tsp200 tsp200 tsp200 tsp200 tsp200 tsp200 . . . tsp200 tsp200 tsp200 Increment address tspvr: Wait 2 s Read verify data Write data = verify data? Yes 6 n? Yes Compute additional-programming data Transfer additional-programming data to additional-programming data area Compute reprogram data Transfer reprogram data to reprogram data area No 128 byte data verify complete? Yes Clear PV1 bit in FLMCR1 tcpv: Wait 2 s 6 n? Yes No *4 No No m=1 *2 nn+1 *3 *4 Note: Use a tsp10 write pulse for additional programming. RAM Program data storage area (128 bytes) Reprogram data storage area (128 bytes) Additional program data storage area (128 bytes) Notes: *1 Transfer data in byte units. The lower eight bits of the start address to which data is written must be H'00 or H'80. Transfer 128-byte data even when writing fewer than 128 bytes. In this case, Set H'FF in unused addresses. *2 Read verify data in word form (16 bits). *3 Even for bits to which data is already written, an additional write should be performed if their verify result is NG. *4 A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional program data must be provided in RAM. The reprogram and additional program data contents are modified as programming proceeds. *5 A write pulse of tsp30 or tsp200 is applied according to the progress of the programming operation. See Note 6 for the pulse widths. When writing of the additional program data is executed, a tsp10 write pulse should be applied. Reprogram data X' means reprogram data when the pulse is applied. Successively write 128-byte data from additional-programming data area in RAM to flash memory Subroutine call Write Pulse (tsp10) No *1 m = 0? Yes Clear SWE1 bit in FLMCR1 tcswe: Wait 100 s Programming end n 1000? Yes Clear SWE1 bit in FLMCR1 tcswe Wait 100 s Programming failure No Reprogram Data Computation Table Original Data Verify Data Reprogram Data Comments (V) (D) (X) 0 0 1 Programming complete. Programming is incomplete; 0 1 0 reprogramming should be performed. 1 0 1 -- 1 1 1 Left in the erased state. Additional-Programming Data Computation Table Reprogram Data Verify Data Additional-Programming Comments (X') (V) Data (Y) Additional programming executed 0 0 0 Additional programming not executed 0 1 1 Additional programming not executed 1 0 1 Additional programming not executed 1 1 1 Figure 17.14 Program/Program-Verify Flowchart 551 17.9.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 17.15. For the wait times (tsswe, tsesu, tse, tce, tcesu , tsev, tsevr, tcev, tcswe) after bits are set or cleared in flash memory control register 1 (FLMCR1) and the maximum number of erase operations (N), see 20.2.5, Flash Memory Characteristics. To perform data or program erasure, make a 1-bit setting for the flash memory area to be erased in erase block register 1 or 2 (EBR1 or EBR2) at least (tsswe) s after setting the SWE1 bit to 1 in flash memory control register 1 (FLMCR1). Next, set up the watchdog timer to prevent overerasing in the event of program runaway, etc. Set a value greater than (t sesu + tse + tce + tcesu) ms as the WDT overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the ESU1 bit in FLMCR1, and after the elapse of (tsesu) s or more, the operating mode is switched to erase mode by setting the E1 bit in FLMCR1. The time during which the E1 bit is set is the flash memory erase time. Ensure that the erase time does not exceed (tse) ms. Note: With flash memory erasing, prewriting (setting all data in the memory to be erased to 0) is not necessary before starting the erase procedure. 17.9.4 Erase-Verify Mode In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the erase time, erase mode is exited (the E1 bit in FLMCR1 is cleared to 0, then the ESU1 bit is cleared to 0 at least (tce) s later), the watchdog timer is cleared after the elapse of (tcesu) s or more, and the operating mode is switched to erase-verify mode by setting the EV1 bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (tsev) s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (tsevr) s after the dummy write before performing this read operation. If the read data has been erased (all 1), execute a dummy write to the next address, and perform an erase-verify. If the read data has not been erased, set erase mode again and repeat the erase/erase-verify sequence as before. However, ensure that the erase/erase-verify sequence is not repeated more than (N) times. When verification is completed, exit erase-verify mode, and wait for at least (tcev) s. If erasure has been completed on all the erase blocks, clear the SWE1 bit in FLMCR1. If there are any unerased blocks, make a 1-bit setting for the flash memory block to be erased, and repeat the erase/erase-verify sequence as before. 552 Start *1 Set SWE1 bit in FLMCR1 tsswe: Wait 1 s n=1 Set EBR1 (2) Enable WDT Set ESU1 bit in FLMCR1 tsesu: Wait 100 s Set E1 bit in FLMCR1 tse: Wait 10 ms Clear E1 bit in FLMCR1 tce: Wait 10 s Clear ESU1 bit in FLMCR1 tcesu: Wait 10 s Disable WDT Set EV1 bit in FLMCR1 tsev: Wait 20 s Set block start address to verify address *3 Erasing must be performed in block units. Start erase Halt erase nn+1 H'FF dummy write to verify address tsevr: Wait 2 s Increment address Read verify data Verify data = all "1"? Yes No Last address of block? Yes Clear EV1 bit in FLMCR1 tcev: Wait 4 s No *4 *2 No Clear EV1bit in FLMCR1 tcev: Wait 4 s No End of erasing of all erase blocks? n 100? Yes Clear SWE1 bit in FLMCR1 tcswe: Wait 100 s Erase failure Yes Clear SWE1 bit in FLMCR1 tcswe: Wait 100 s End of erasing Notes: *1 *2 *3 *4 Preprogramming (setting erase block data to all "0") is not necessary. Verify data is read in 16-bit (word) units. Set only one bit in EBR1 (2). More than one bit cannot be set. Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn. Figure 17.15 Erase/Erase-Verify Flowchart 553 17.10 Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 17.10.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2). The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained in the error-protected state. (See table 17.10.) Table 17.10 Hardware Protection Functions Item FWE pin protection Description * When a low level is input to the FWE pin, FLMCR1, FLMCR2, (except bit FLER) EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. In a power-on reset (including a WDT power-on reset) and in standby mode, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/eraseprotected state is entered. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. Program Yes Erase Yes Reset/standby protection * Yes Yes * 554 17.10.2 Software Protection Software protection can be implemented by setting the SWE1 bit in FLMCR1, erase block register 1 (EBR1), erase block register 2 (EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), does not cause a transition to program mode or erase mode. (See table 17.11.) Table 17.11 Software Protection Functions Item SWE bit protection Description * Setting bit SWE1 in FLMCR1 to 0 will place area H'000000 to H'01FFFF in the program/erase-protected state. (Execute the program in the on-chip RAM, external memory) Erase protection can be set for individual blocks by settings in erase block register 1 (EBR1) and erase block register 2 (EBR2). Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state. Setting the RAMS bit to 1 in the RAM emulation register (RAMER) places all blocks in the program/erase-protected state. Program Yes Erase Yes Block specification protection * -- Yes * Emulation protection * Yes Yes 555 17.10.3 Error Protection In error protection, an error is detected when LSI runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the LSI malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P1 or E1 bit. However, PV1 and EV1 bit setting is enabled, and a transition can be made to verify mode. FLER bit setting conditions are as follows: 1. When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) 2. Immediately after exception handling (excluding a reset) during programming/erasing 3. When a SLEEP instruction (including software standby) is executed during programming/erasing 4. When the CPU releases the bus to the DTC during programming/erasing. Error protection is released only by a power-on reset and in hardware standby mode. 556 Figure 17.16 shows the flash memory state transition diagram. Program mode Erase mode RD VF PR ER FLER = 0 RES = 0 or HSTBY = 0 Reset or standby (hardware protection) RD VF PR ER FLER = 0 Error occurrence (software standby) Error occurrence RES = 0 or HSTBY = 0 RES = 0 or HSTBY = 0 FLMCR1, FLMCR2, EBR1, EBR2 initialization state Error protection mode RD VF PR ER FLER = 1 Software standby mode Software standby mode release Error protection mode (software standby) RD VF PR ER FLER = 1 FLMCR1, FLMCR2, (except bit FLER) EBR1, EBR2 initialization state Legend RD: Memory read possible VF: Verify-read possible PR: Programming possible ER: Erasing possible RD: VF: PR: ER: Memory read not possible Verify-read not possible Programming not possible Erasing not possible Figure 17.16 Flash Memory State Transitions 557 17.11 Flash Memory Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses can be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 17.17 shows an example of emulation of real-time flash memory programming. Start of emulation program Set RAMER Write tuning data to overlap RAM Execute application program No Tuning OK? Yes Clear RAMER Write to flash memory emulation block End of emulation program Figure 17.17 Flowchart for Flash Memory Emulation in RAM 558 This area can be accessed from both the RAM area and flash memory area H'000000 EB0 H'000400 EB1 H'000800 EB2 H'000C00 EB3 H'001000 Flash memory EB4 to EB9 H'FFD000 H'FFD3FF On-chip RAM H'01FFFF Figure 17.18 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB0 is Overlapped 1. Set bits RAMS, RAM1, and RAM0 in RAMER to 1, 0, 0, to overlap part of RAM onto the area (EB0) for which real-time programming is required. 2. Real-time programming is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB0). Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of RAM1 and RAM0 (emulation protection). In this state, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), will not cause a transition to program mode or erase mode. When actually programming or erasing a flash memory area, the RAMS bit should be cleared to 0. 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 contains the vector table. When performing RAM emulation, the vector table is needed in the overlap RAM. 559 17.12 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI interrupt is disabled when flash memory is being programmed or erased (when the P1 or E1 bit is set in FLMCR1), and while the boot program is executing in boot mode*1, to give priority to the program or erase operation. There are three reasons for this: 1. Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly*2, possibly resulting in MCU runaway. 3. If interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, in on-board programming mode alone there are conditions for disabling interrupt, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All requests, including NMI interrupt, must therefore be restricted inside and outside the MCU when programming or erasing flash memory. NMI interrupt is also disabled in the error-protection state while the P1 or E1 bit remains set in FLMCR1. Notes: *1 Interrupt requests must be disabled inside and outside the MCU until the programming control program has completed programming. *2 The vector may not be read correctly in this case for the following two reasons: * If flash memory is read while being programmed or erased (while the P1 or E1 bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned). * If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. 17.13 Flash Memory Programmer Mode Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, flash memory read mode, auto-program mode, autoerase mode, and status read mode are supported. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. In programmer mode, set the mode pins to programmer mode (see table 17.12) and input a 12 MHz input clock. Table 17.12 shows the pin settings for programmer mode. For the pin names in programmer mode, see section 1.3.2, Pin Functions in Each Operating Mode. 560 Table 17.12 Programmer Mode Pin Settings Pin Names Mode pins: MD2, MD1, MD0 Mode setting pins: PF3, PF0, P16, P14 FWE pin RES pin XTAL, EXTAL pins Settings Low level input to MD2, MD1, and MD0. High level input to PF3 and PF0, low level input to P16 and P14 High level input (in auto-program and auto-erase modes) Power-on reset circuit Oscillator circuit 17.13.1 Socket Adapter Pin Correspondence Diagram Connect the socket adapter to the chip as shown in figure 17.20. This will enable conversion to a 40-pin arrangement. The on-chip ROM memory map is shown in figure 17.19, and the socket adapter pin correspondence diagram in figure 17.20. Addresses in MCU mode H'000000 Addresses in programmer mode H'00000 On-chip ROM space 128 kbytes H'01FFFF H'1FFFF Figure 17.19 On-Chip ROM Memory Map 561 LSI Pin No. TFP-100B, TFP-100G 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 4 5 6 7 8 9 10 11 3 1 2 66 12, 53, 54, 58, 60, 61, 62, 72, 75, 99 14, 38, 40, 42, 55, 56, 64, 67, 100 HN27C4096HG (40 Pins) Pin Name Socket Adapter (Conversion to 40-Pin Arrangement) Pin No. Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CE OE WE FWE VCC VSS NC A20 A19 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 D0 D1 D2 D3 D4 D5 D6 D7 CE OE WE FWE VCC 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 10 19 18 17 16 15 14 13 12 2 20 3 4 1,40 11,30 VSS RES XTAL EXTAL NC (OPEN) Oscillator circuit Power-on reset circuit 5,6,7 8 9 Legend FWE: I/O7-I/O0: A18-A0: CE: OE: WE: 59 63 65 Other than the above Flash write enable Data input/output Address input Chip enable Output enable Write enable Figure 17.20 Socket Adapter Pin Correspondence Diagram 562 17.13.2 Programmer Mode Operation Table 17.13 shows how the different operating modes are set when using programmer mode, and table 17.14 lists the commands used in programmer mode. Details of each mode are given below. * Memory Read Mode Memory read mode supports byte reads. * Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. * Auto-Erase Mode Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-programming. * Status Read Mode Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the I/O6 signal. In status read mode, error information is output if an error occurs. Table 17.13 Settings for Various Operating Modes In Programmer Mode Pin Names Mode Read Output disable Command write Chip disable FWE H or L H or L H or L H or L CE L L L H OE L H H X WE H H L X I/O7- I/O0 Data output Hi-z Data input Hi-z A18-A0 Ain X *Ain X Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. *Ain indicates that there is also address input in auto-program mode. 3. For command writes in auto-program and auto-erase modes, input a high level to the FWE pin. 563 Table 17.14 Programmer Mode Commands Number of Cycles 1+n 129 2 2 1st Cycle Mode Write Write Write Write Address Data X X X X H'00 H'40 H'20 H'71 Mode Read Write Write Write 2nd Cycle Address Data RA WA X X Dout Din H'20 H'71 Command Name Memory read mode Auto-program mode Auto-erase mode Status read mode Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n). 17.13.3 Memory Read Mode 1. After completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. When reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. 2. In memory read mode, command writes can be performed in the same way as in the command wait state. 3. Once memory read mode has been entered, consecutive reads can be performed. 4. After powering on, memory read mode is entered. Table 17.15 AC Characteristics in Transition to Memory Read Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol t nxtc t ceh t ces t dh t ds t wep tr tf Min 20 0 0 50 50 70 -- -- Max -- -- -- -- -- -- 30 30 Unit s ns ns ns ns ns ns ns 564 Command write A18-A0 tces CE tceh tnxtc Memory read mode Address stable OE tf WE twep tr tds I/O7-I/O0 tdh Note: Data is latched on the rising edge of WE. Figure 17.21 Timing Waveforms for Memory Read after Memory Write Table 17.16 AC Characteristics in Transition from Memory Read Mode to Another Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol t nxtc t ceh t ces t dh t ds t wep tr tf Min 20 0 0 50 50 70 -- -- Max -- -- -- -- -- -- 30 30 Unit s ns ns ns ns ns ns ns 565 Memory read mode A18-A0 Address stable tnxtc CE Other mode command write tces tceh OE tf WE twep tr tds I/O7-I/O0 Note: Do not enable WE and OE at the same time. tdh Figure 17.22 Timing Waveforms in Transition from Memory Read Mode to Another Mode Table 17.17 AC Characteristics in Memory Read Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Access time CE output delay time OE output delay time Output disable delay time Data output hold time Symbol t acc t ce t oe t df t oh Min -- -- -- -- 5 Max 20 150 150 100 -- Unit s ns ns ns ns A18-A0 Address stable Address stable CE OE WE VIL VIL VIH tacc toh tacc toh I/O7-I/O0 Figure 17.23 CE and OE Enable State Read Timing Waveforms 566 A18-A0 CE Address stable tce toe Address stable tce toe OE WE tacc toh I/O7-I/O0 tdf tacc toh VIH tdf Figure 17.24 CE and OE Clock System Read Timing Waveforms 17.13.4 Auto-Program Mode 1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. 2. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. The lower 7 bits of the transfer address must be low. If a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 4. Memory address transfer is performed in the second cycle (figure 17.25). Do not perform transfer after the third cycle. 5. Do not perform a command write during a programming operation. 6. Perform one auto-program operation for a 128-byte block for each address. Two or more additional programming operations cannot be performed on a previously programmed address block. 7. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-program operation end decision pin). 8. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. 567 Table 17.18 AC Characteristics in Auto-Program Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Address setup time Address hold time Memory write time Write setup time Write end setup time WE rise time WE fall time Symbol t nxtc t ceh t ces t dh t ds t wep t wsts t spa t as t ah t write t pns t pnh tr tf Min 20 0 0 50 50 70 1 -- 0 60 1 100 100 -- -- Max -- -- -- -- -- -- -- 150 -- -- 3000 -- -- 30 30 Unit s ns ns ns ns ns ms ns ns ns ms ns ns ns ns FWE tpnh Address stable tpns tces tceh tnxtc tnxtc A18-A0 CE OE tf twep tr tas tah Data transfer 1 to 128 bytes twsts tspa WE tds tdh twrite Write operation end decision signal I/O7 I/O6 I/O5-I/O0 Write normal end decision signal H'40 H'00 Figure 17.25 Auto-Program Mode Timing Waveforms 568 17.13.5 Auto-Erase Mode 1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin). 4. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. Table 17.19 AC Characteristics in Auto-Erase Mode (Conditions: V CC = 3.3 V 3.0 V, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Memory erase time Erase setup time Erase end setup time WE rise time WE fall time Symbol t nxtc t ceh t ces t dh t ds t wep t ests t spa t erase t ens t enh tr tf Min 20 0 0 50 50 70 1 -- 100 100 100 -- -- Max -- -- -- -- -- -- -- 150 40000 -- -- 30 30 Unit s ns ns ns ns ns ms ns ms ns ns ns ns 569 FWE A18-A0 CE OE WE I/O7 ,,,, tpnh tens tces tceh tnxtc tnxtc tf twep tr tests tspa tds tdh terase Erase end decision signal Erase normal end decision signal I/O6 I/O5-I/O0 H'20 H'20 H'00 Figure 17.26 Auto-Erase Mode Timing Waveforms 570 17.13.6 Status Read Mode 1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. The return code is retained until a command write other than a status read mode command write is executed. Table 17.20 AC Characteristics in Status Read Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Read time after command write CE hold time CE setup time Data hold time Data setup time Symbol t nxtc t ceh t ces t dh t ds Min 20 0 0 50 50 70 -- -- -- -- -- Max -- -- -- -- -- -- Unit s ns ns ns ns ns ns ns ns ns ns Write pulse width OE output delay time Disable delay time WE rise time WE fall time CE output delay time A18-A0 I/O7-I/O0 ,,,, t wep t oe t df 150 100 150 30 30 t ce tr tf tces tceh tnxtc tces tceh tnxtc tnxtc CE tce OE tf twep tr tf twep tr toe WE tds tdh tds tdh tdf H'71 H'71 Note: I/O2 and I/O3 are undefined. Figure 17.27 Status Read Mode Timing Waveforms 571 Table 17.21 Status Read Mode Return Commands Pin Name I/O7 Attribute Normal end decision I/O6 Command error I/O5 Programming error I/O4 Erase error I/O3 -- I/O2 -- I/O1 I/O0 ProgramEffective ming or address error erase count exceeded 0 0 Initial value 0 Indications Normal end: 0 Abnormal end: 1 0 Command error: 1 0 0 0 0 -- ProgramErasing -- ming error: 1 Otherwise: 0 error: 1 Otherwise: 0 Otherwise: 0 Count Effective exceeded: 1 address Otherwise: 0 error: 1 Otherwise: 0 Note: I/O2 and I/O3 are undefined. 17.13.7 Status Polling 1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode. 2. The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase mode. Table 17.22 Status Polling Output Truth Table Pin Name I/O7 I/O6 I/O0-I/O5 During Internal Operation 0 0 0 Abnormal End 1 0 0 -- 0 1 0 Normal End 1 1 0 17.13.8 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 17.23 Stipulated Transition Times to Command Wait State Item Standby release (oscillation stabilization time) Programmer mode setup time VCC hold time Symbol t osc1 t bmv t dwn Min 30 10 0 Max -- -- -- Unit ms ms ms 572 tosc1 VCC tbmv Memory read mode Command Auto-program mode wait state Auto-erase mode Command wait state Normal/abnormal end decision tdwn RES FWE Note: Except in auto-erase or auto-program mode, the FWE input pin should be driven low. Figure 17.28 Oscillation Stabilization Time, Boot Program Transfer Time, and Power-Down Sequence 17.13.9 Notes on Memory Programming 1. When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. 2. When performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Hitachi. For other chips for which the erasure history is unknown, it is recommended that autoerasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. Additional programming cannot be performed on previously programmed address blocks. 573 17.14 Flash Memory and Power-Down States In addition to its normal operating state, the flash memory has power-down states in which power consumption is reduced by halting part or all of the internal power supply circuitry. There are three flash memory operating states: (1) Normal operating mode: The flash memory can be read and written to. (2) Power-down mode: Part of the power supply circuitry is halted, and the flash memory can be read only when the LSI is operating on the subclock. (3) Standby mode: All flash memory circuits are halted, and the flash memory cannot be read or written to. States (2) and (3) are flash memory power-down states. Table 17.24 shows the correspondence between the operating states of the LSI and the flash memory. Table 17.24 Flash Memory Operating States LSI Operating State High-speed mode Medium-speed mode Sleep mode Subactive mode Subsleep mode Watch mode Software standby mode Hardware standby mode Note: PDWND is valid only when the LSI is in subactive mode or subsleep mode, and is invalid in other modes. When PDWND = 0: Power-down mode (read-only) When PDWND = 1: Normal mode (read-only) Standby mode Flash Memory Operating State Normal mode (read/write) 17.14.1 Note on Power-Down States When the flash memory is in a power-down state, part or all of the internal power supply circuitry is halted. Therefore, a power supply circuit stabilization period must be provided when returning to normal operation. When the flash memory returns to its normal operating state from a powerdown state, bits STS2 to STS0 in SBYCR must be set to provide a wait time of at least 100 s (power supply stabilization time), even if an oscillation stabilization period is not necessary. 574 17.15 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode, the RAM emulation function, and PROM mode are summarized below. Use the specified voltages and timing for programming and erasing Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Hitachi microcomputer device type with 128-kbyte on-chip flash memory (FZTAT128V3A). Do not select the HN27C101 or the HN28F101 setting for the PROM programmer, and only use the specified socket adapter. Failure to observe these points may result in damage to the device. Powering on and off (See figures 17.29 to 17.31) Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low before turning off VCC. When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. FWE application/disconnection (See figures 17.29 to 17.31) FWE application should be carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection state. The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: * Apply FWE when the VCC voltage has stabilized within its rated voltage range. * In boot mode, apply and disconnect FWE during a reset. * In user program mode, FWE can be switched between high and low level regardless of the reset state. FWE input can also be switched during execution of a program in flash memory. * Do not apply FWE if program runaway has occurred. * Disconnect FWE only when the SWE1, ESU1, PSU1, EV1, PV1, P1, and E1 bits in FLMCR1 are cleared. Make sure that the SWE1, ESU1, PSU1, EV1, PV1, P1, and E1 bits are not set by mistake when applying or disconnecting FWE. 575 Do not apply a constant high level to the FWE pin Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. Use the recommended algorithm when programming and erasing flash memory The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P1 or E1 bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. Do not set or clear the SWE1 bit during execution of a program in flash memory Wait for at least 100 s after clearing the SWE1 bit before executing a program or reading data in flash memory. When the SWE1 bit is set, data in flash memory can be rewritten, but access flash memory only for verify operations (verification during programming/erasing). Also, do not clear the SWE1 bit during programming, erasing, or verifying. Similarly, when using emulation by RAM with a high level applied to the FWE pin, the SWE1 bit should be cleared before executing a program or reading data in flash memory. However, read/write accesses can be performed in the RAM area overlapping the flash memory space regardless of whether the SWE1 bit is set or cleared. Do not use interrupts while flash memory is being programmed or erased All interrupt requests, including NMI, should be disabled during FWE application to give priority to program/erase operations. Do not perform additional programming. Erase the memory before reprogramming In on-board programming, perform only one programming operation on a 128-byte programming unit block. In programmer mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. Before programming, check that the chip is correctly mounted in the PROM programmer Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. Do not touch the socket adapter or chip during programming Touching either of these can cause contact faults and write errors. 576 The reset state must be entered after powering on Apply the reset signal for at least 100 s during the oscillation setting period. When a reset is applied during operation, this should be done while the SWE1 pin is low. Wait at least 100 s after clearing the SWE1 bit before applying the reset. Programming/ erasing possible Wait time: 100 s Wait time: tsswe o tOSC1 VCC Min. 0 s FWE tMDS*3 Min. 0 s MD2 to MD0*1 tMDS*3 RES SWE set SWE1 bit SWE cleared Period during which flash memory access is prohibited (tsswe: Wait time after setting SWE1 bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: *1 Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off by pulling the pins up or down. *2 See Flash Memory Characteristics (section 20.2.5). *3 Mode programming setup time tMDS (min) = 200 ns Figure 17.29 Power-On/Off Timing (Boot Mode) 577 Wait time: tsswe Programming/ erasing possible Wait time: 100 s o tOSC1 VCC Min. 0 s FWE MD2 to MD0*1 tMDS*3 RES SWE set SWE1 bit SWE cleared Period during which flash memory access is prohibited (tsswe: Wait time after setting SWE1 bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: *1 Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off by pulling the pins up or down. *2 See Flash Memory Characteristics (section 20.2.5). *3 Mode programming setup time tMDS (min) = 200 ns Figure 17.30 Power-On/Off Timing (User Program Mode) 578 Programming/erasing possible Programming/erasing possible Programming/erasing possible Programming/erasing possible Wait time: 100 s Wait time: 100 s Wait time: 100 s Wait time: tsswe Wait time: tsswe Wait time: tsswe *4 *4 *4 Wait time:tsswe Wait time: 100 s *4 o tOSC1 VCC Min. 0 s FWE tMDS tMDS*2 MD2 to MD0 tMDS tRESW RES SWE set Mode change*1 Boot mode SWE1 bit SWE cleared Mode User change*1 mode User program mode User mode User program mode Period during which flash memory access is prohibited (tsswe: Wait time after setting SWE1 bit)*3 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: *1 When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of RES input. The state of ports with multiplexed address functions and bus control output pins (AS, RD, WR) will change during this switchover interval (the interval during which the RES pin input is low), and therefore these pins should not be used as output signals during this time. *2 When making a transition from boot mode to another mode, a mode programming setup time tMDS (min) of 200 ns is necessary with respect to RES clearance timing. *3 See Flash Memory Characteristics (section 20.2.5). *4 Wait time: 100 s Figure 17.31 Mode Transition Timing (Example: Boot Mode User Mode User Program Mode) 579 580 Section 18 Clock Pulse Generator 18.1 Overview The LSI has a built-in clock pulse generator (CPG) that generates the system clock (o), the bus master clock, and internal clocks. The clock pulse generator consists of a system clock oscillator, duty adjustment circuit, clock selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock oscillator, and waveform shaping circuit. 18.1.1 Block Diagram Figure 18.1 shows a block diagram of the clock pulse generator. LPWRCR RFCUT SCKCR SCK2 to SCK0 EXTAL XTAL System clock oscillator Duty adjustment circuit Clock selection circuit oSUB Mediumspeed clock divider o/2 to o/32 Bus master clock selection circuit o OSC1 Subclock oscillator OSC2 Waveform shaping circuit 1/2 System clock to o pin Internal clock to supporting modules Bus master clock to CPU and DTC FLEXTM decoder II clock Legend: LPWRCR: Low-power control register SCKCR: System clock control register WDT1 count clock Figure 18.1 Block Diagram of Clock Pulse Generator 581 18.1.2 Register Configuration The clock pulse generator is controlled by SCKCR and LPWRCR. Table 18.1 shows the register configuration. Table 18.1 Clock Pulse Generator Register Name System clock control register Low-power control register Abbreviation SCKCR LPWRCR R/W R/W R/W Initial Value H'00 H'00 Address* H'FDE6 H'FDEC Note:* Lower 16 bits of the address. 18.2 18.2.1 Bit Register Descriptions System Clock Control Register (SCKCR) : 7 PSTOP 0 R/W 6 -- 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 -- 0 R/W 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W Initial value: R/W : SCKCR is an 8-bit readable/writable register that performs o clock output control and mediumspeed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--o Clock Output Disable (PSTOP): Controls o output. Bit 7 High-Speed Mode, Medium-Speed Mode, Subactive Mode o output (initial value) Fixed high Description Sleep Mode Subsleep Mode o output Fixed high Software Standby Mode, Watch Mode, Direct Transition Fixed high Fixed high Hardware Standby Mode High impedance High impedance PSTOP 0 1 Bits 6 to 3--Reserved: Only 0 should be written to these bits. 582 Bits 2 to 0--System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master clock used in high-speed mode and medium-speed mode. In the case of transition to subactive mode or watch mode, bits SCK2 to SCK0 should all be cleared to 0. Bit 2 SCK2 0 Bit 1 SCK1 0 Bit 0 SCK0 0 1 1 0 1 1 0 0 1 1 -- Description Bus master is in high-speed mode Medium-speed clock is o/2 Medium-speed clock is o/4 Medium-speed clock is o/8 Medium-speed clock is o/16 Medium-speed clock is o/32 -- (Initial value) 18.2.2 Bit Low-Power Control Register (LPWRCR) : 7 DTON 0 R/W 6 LSON 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 -- 0 R/W 1 STC1 0 R/W 0 STC0 0 R/W NESEL SUBSTP RFCUT Initial value : R/W : LPWRCR is an 8-bit readable/writable register that performs power-down mode control. LPWRCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Direct-Transfer On Flag (DTON): Specifies whether a direct transition is made between high-speed mode or medium-speed mode and subactive mode when making a power-down transition by executing a SLEEP instruction. The operating mode to which the transition is made after SLEEP instruction execution is determined by a combination of other control bits. 583 Bit 7 DTON 0 Description * * * When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode (Initial value) When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made directly to subactive mode*, or a transition is made to sleep mode or sofware standby mode When a SLEEP instruction is executed in subactive mode, a transition is made directly to high-speed mode, or a transition is made to subsleep mode 1 * Note: * In the case of a transition to watch mode or subactive mode, high-speed mode must be set. Bit 6--Low-Speed On Flag (LSON): Determines the operating mode in combination with other control bits when making a power-down transition by executing a SLEEP instruction. Also controls whether a transition is made to high-speed mode or medium-speed mode, or to subactive mode, when watch mode is cleared. Bit 6 LSON 0 Description * * * * * * When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode*, or directly to high-speed mode After watch mode is cleared, a transition is made to high-speed mode (Initial value) When a SLEEP instruction is executed in high-speed mode, a transition is made to watch mode or subactive mode When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode After watch mode is cleared, a transition is made to subactive mode 1 Note: * In the case of a transition to watch mode or subactive mode, high-speed mode must be set. 584 Bit 5--Noise Elimination Sampling Frequency Select (NESEL): Selects the frequency at which the subclock (oSUB) generated by the subclock oscillator is sampled with the clock (o) generated by the system clock oscillator. When o = 5 MHz or higher, this bit should be cleared to 0. Bit 5 NESEL 0 1 Description Sampling at o divided by 8 Sampling at o divided by 4 (Initial value) Bit 4--Subclock Oscillator Control (SUBSTP): Controls operation and stopping of the subclock oscillator. Bit 4 SUBSTP 0 1 Description Subclock oscillator operates Subclock oscillator is stopped (Initial value) Note: When the subclock is not used, this bit should be set to 1. Bit 3--Built-in Feedback Resistor Control (RFCUT): Selects whether the oscillator's built-in feedback resistor and duty adjustment circuit are used with external clock input. Do not access this bit when a crystal oscillator is used. After this bit is set when using external clock input, a transition should intially be made to software standby mode, watch mode, or subactive mode. Switching between use and non-use of the oscillator's built-in feedback resistor and duty adjustment circuit is performed when the transition is made to software standby mode, watch mode, or subactive mode. Bit 3 RFCUT 0 1 Description System clock oscillator's built-in feedback resistor and duty adjustment circuit are used (Initial value) System clock oscillator's built-in feedback resistor and duty adjustment circuit are not used Bit 2--Reserved: This bit can be read or written to, but should only be written with 0. 585 Bits 1 and 0--Frequency Multiplication Factor (STC1, STC0): The STC bits specify the frequency multiplication factor of the PLL circuit incorporated into the evaluation chip. The specified frequency multiplication factor is valid after a transition to software standby mode, watch mode, or subactive mode. With the LSI, STC1 and STC0 must both be set to 1. After a reset, STC1 and STC0 are both cleared to 0, and so must be set to 1. Bit 1 STC1 0 Bit 0 STC0 0 1 1 0 1 Description x1 x2 (Setting prohibited) x4 (Setting prohibited) PLL is bypassed (Initial value) 586 18.3 System Clock Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 18.3.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 18.2. Select the damping resistance Rd according to table 18.2. An AT-cut parallel-resonance crystal should be used. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF Figure 18.2 Connection of Crystal Resonator (Example) Table 18.2 Damping Resistance Value Frequency (MHz) Rd () 2 1k 4 500 6 300 8 200 10 100 12 0 Crystal Resonator: Figure 18.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 18.3 and the same resonance frequency as the system clock (o). CL L XTAL Rs EXTAL AT-cut parallel-resonance type C0 Figure 18.3 Crystal Resonator Equivalent Circuit Table 18.3 Crystal Resonator Parameters Frequency (MHz) RS max () C0 max (pF) 2 500 7 4 120 7 6 100 7 8 80 7 10 60 7 12 60 7 587 Note on Board Design: When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 18.4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Avoid CL2 Signal A Signal B LSI XTAL EXTAL CL1 Figure 18.4 Example of Incorrect Board Design 18.3.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 18.5. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode, subactive mode, subsleep mode, and watch mode. EXTAL XTAL Open External clock input (a) XTAL pin left open EXTAL XTAL External clock input (b) Complementary clock input at XTAL pin Figure 18.5 External Clock Input (Examples) 588 External Clock: The external clock signal should have the same frequency as the system clock (o). Table 18.4 and figure 18.6 show the input conditions for the external clock. Table 18.4 External Clock Input Conditions F-ZTAT Version VCC = 2.7 V to 3.6 V Item External clock input low pulse width External clock input high pulse width External clock rise time External clock fall time Clock low pulse width level Symbol t EXL t EXH t EXr t EXf t CL Min 30 30 -- -- 0.4 80 Clock high pulse width level t CH 0.4 80 Max -- -- 7 7 0.6 -- 0.6 -- Unit ns ns ns ns t cyc ns t cyc ns o 5 MHz Figure 20.3 o < 5 MHz o 5 MHz o < 5 MHz Conditions Figure 18.6 The external clock input conditions when the duty adjustment circuit is not used are shown in table 18.5 and figure 18.6. When the duty adjustment circuit is not used, the o output waveform depends on the external clock input waveform, and so no restrictions apply. Table 18.5 External Clock Input Conditions when the Duty Adjustment Circuit is not Used F-ZTAT Version VCC = 2.7 V to 3.6 V Item External clock input low pulse width External clock input high pulse width External clock rise time External clock fall time Symbol t EXL t EXH t EXr t EXf Min 37 37 -- -- Max -- -- 7 7 Unit ns ns ns ns Conditions Figure 18.6 Note: When duty adjustment circuit is not used, the maximum frequency decreases according to the input waveform. (Example: When t EXL = tEXH = 50 ns, and tEXr = tEXf = 10 ns, clock cycle time = 120 ns; therefore, maximum operating frequency = 8.3 MHz) 589 tEXH VCC x 0.8 tEXL EXTAL VCC x 0.2 tEXr tEXf Figure 18.6 External Clock Input Timing (3) Note on Switchover of External Clock When two or more external clocks (e.g. 10 MHz and 2 MHz) are used as the system clock, switchover of the input clock should be carried out in software standby mode. An example of an external clock switching circuit is shown in figure 18.7, and an example of the external clock switchover timing in figure 18.8. LSI Port output External interrupt External clock switchover request Control circuit External interrupt signal External clock switchover signal External clock 1 External clock 2 Selector EXTAL Figure 18.7 Example of External Clock Switching Circuit 590 External clock 1 External clock 2 Operation Clock switchover request SLEEP instruction execution Interrupt exception handling (5) (1) Port output (2) (3) External clock switchover signal EXTAL Internal clock o Wait time External interrupt Active (external clock 2) (1) Port output (clock switchover) (2) Software standby mode transition (3) External clock switchover (4) External interrupt generation (Input interrupt at least 200 ns after transition to software standby mode.) (5) Interrupt exception handling 200 ns or more (4) Software standby mode Active (external clock 1) Figure 18.8 Example of External Clock Switchover Timing 591 18.4 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (o). 18.5 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate o/2, o/4, o/8, o/16, and o/32. 18.6 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock (o) or one of the medium-speed clocks (o/2, o/4, or o/8, o/16, and o/32) to be supplied to the bus master, according to the settings of the SCK2 to SCK0 bits in SCKCR. 18.7 Subclock Oscillator (1) Method of Connecting 76.8 kHz/160 kHz Crystal Resonator To supply a clock to the subclock oscillator, a 76.8 kHz/160 kHz crystal resonator should be connected as shown in figure 18.9. Cautions concerning the connection are as noted in section 18.3 (3), Notes on Board Design. C1 OSC1 C2 OSC2 C1, C2: refer to table 18.6 Figure 18.9 Example of Connection of 76.8 kHz/160 kHz Crystal Resonator 592 Figure 18.10 shows an equivalent circuit for the 76.8 kHz/160 kHz crystal resonator. LS CS Rs OSC1 C0 OSC2 C0, RS: refer to table 18.6 fw = 76.8 kHz/160 kHz Figure 18.10 76.8 kHz/160 kHz Crystal Resonator Equivalent Circuit Table 18.6 Reference of Subclock Oscillator Equivalent Circuit Oscillation Frequency [kHz] 76.8 160.0 Load Capacitance C1, C2 [pF] 11 11 Shunt Capacitance [pF] 0.8 1.0 Series Resistance [k] 12 20 Type Code T26-76.8 TF26-160 Manufacturer MEC ILSI (2) Pin Handling When Subclock Is Not Needed When the subclock is not needed, connect the OSC1 pin to GND (Vss) and leave the OSC2 pin open as shown in figure 18.11, and the SUBSTP bit of LPWRCR should be set to 1. OSC1 OSC2 Open Figure 18.11 Pin Handling When Subclock Is Not Needed 593 18.8 Subclock Waveform Shaping Circuit To eliminate noise in the subclock input from the OSC1 pin, the signal is sampled using a clock scaled from the o clock. The sampling frequency is set with the NESEL bit in LPWRCR. For details, see section 18.2.2, Low-Power Control Register (LPWRCR). Sampling is not performed in subactive mode, subsleep mode, or watch mode. 18.9 Note on Crystal Resonator Since various characteristics related to the crystal resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a guide. As the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. 594 Section 19 Power-Down Modes 19.1 Overview In addition to the normal program execution state, the LSI has power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. The LSI operating modes are as follows: (1) High-speed mode (2) Medium-speed mode (3) Subactive mode (4) Sleep mode (5) Subsleep mode (6) Watch mode (7) Module stop mode (8) Software standby mode (9) Hardware standby mode Of these, (2) to (9) are power-down modes. Sleep mode and subsleep mode are CPU modes, medium-speed mode is a CPU and bus master mode, subactive mode is a CPU, bus master, and on-chip supporting module mode, and module stop mode is an on-chip supporting module mode (including bus masters other than the CPU). Certain combinations of these modes can be set. After a reset, the MCU is in high-speed mode. Table 19.1 shows the internal chip states in each mode, and table 19.2 shows the conditions for transition to the various modes. Figure 19.1 shows a mode transition diagram. 595 Table 19.1 H8S/2276 Series Internal States in Each Mode Function System clock oscillator Subclock oscillator CPU operation Instructions Registers RAM I/O External interrupts On-chip PBC supporting module operation DTC WDT1 WDT0 TMR TPU SCI A/D Function- Halted ing/halted (reset) (reset) Functioing/halted (retained) Functioning Functioning Functioning Functioning HighSpeed Functioning MediumSpeed Sleep Module Stop Subactive Watch Halted Software Hardware Subsleep Standby Standby Halted Halted Halted Function- Functioning ing Function- Halted ing Function- Function- Function- Function- Functioning/Halted ing/Halted ing/Halted ing/Halted ing Functioning Mediumspeed Halted Retained Function- Halted ing Retained Function- Functioning ing Subclock Halted operation Retained Function- Retained ing Function- Retained ing Function- Functioning ing Subclock Halted operation (retained) Halted (retained) Function- Halted ing/Halted Halted Retained Retained Retained Halted Undefined Retained High impedance Function- Function- Function- Retained ing ing (DTC) ing Function- Functioning ing Function- Functioning ing Mediumspeed Functioning Function- Retained ing Function- Functioning ing Function- Halted ing/halted (retained) (retained) Function- Halted ing Halted Halted (retained) (reset) Functioning Function- Subclock ing operation Halted (retained) Subclock Subclock operation operation Halted Halted (retained) (retained) Halted (reset) Halted (reset) Halted (reset) Note: "Halted (retained)" means that internal register values are retained. The internal state is operation suspended. "Halted (reset)" means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). Subclock oscillation is halted when the SUBSTP bit is set to 1 and a stop setting is made. : Operating state 596 Program-halted state Reset state Power-on reset state STBY pin = low Hardware standby mode STBY pin = high RES pin = low RES pin = high Program execution state High-speed mode (main clock) SCK2 to SCK0 = 0 SCK2 to SCK0 0 SLEEP instruction All interrupt*3 SLEEP instruction External interrupt*4 SLEEP instruction SSBY = 1 PSS = 1, DTON = 0 Watch mode (subclock) SSBY = 1 PSS = 0, LSON = 0 Software standby mode SSBY = 0, LSON = 0 Sleep mode (main clock) Medium-speed mode (main clock) SLEEP instruction SSBY = 1, PSS = 1, DTON = 1, LSON = 0 Clock switching exception handling after oscillation stabilization time (STS2 to STS0) Interrupt*1, SLEEP instruction SSBY = 1, PSS = 1, LSON bit = 0 DTON = 1, LSON = 1 Clock switching SLEEP exception handling instruction Interrupt*1, LSON bit = 1 SLEEP instruction Interrupt*2 SSBY = 0 PSS = 1, LSON = 1 Subsleep mode (subclock) Subactive mode (subclock) : Transition after exception handling Notes: *1 *2 *3 *4 : Power-down mode NMI, IRQ0 to IRQ7, and WDT1 interrupts NMI, IRQ0 to IRQ7, WDT0 interrupts, WDT1 interrupt, TMR0 and TMR1 interrupt All interrupts NMI, IRQ0 to IRQ7 * When a transition is made between modes by means of an interrupt, transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. * From any state except hardware standby mode, a transition to the power-on reset state occurs whenever RES goes low. * From any state, a transition to hardware standby mode occurs when STBY goes low. * When a transition is made to watch mode or subactive mode, high-speed mode must be set. Figure 19.1 Mode Transitions 597 Table 19.2 Power-Down Mode Transition Conditions Control Bit States at Time of Transition State before Transition SSBY PSS * * 0 0 1 1 1 1 0 1 1 0 1 1 1 1 LSON 0 1 0 1 0 1 0 1 * 0 1 * 0 1 0 1 DTON * * * * 0 0 1 1 * * * * 0 0 1 1 State after Transition State after Return by SLEEP Instruction by Interrupt Sleep -- Software standby -- Watch Watch -- Subactive -- -- Subsleep -- Watch Watch High-speed -- High-speed/ medium-speed -- High-speed/ medium-speed -- High-speed Subactive -- -- -- -- Subactive -- High-speed Subactive -- -- High-speed/ 0 medium-speed 0 1 1 1 1 1 1 Subactive 0 0 0 1 1 1 1 1 *: Don't care --: Don't set. 598 19.1.1 Register Configuration The power-down modes are controlled by the SBYCR, SCKCR, LPWRCR, TCSR (WDT1), and MSTPCR registers. Table 19.3 summarizes these registers. Table 19.3 Power-Down Mode Registers Name Standby control register System clock control register Low-power control register Timer control/status register (WDT1) Module stop control register Abbreviation SBYCR SCKCR LPWRCR TCSR MSTPCRA MSTPCRB MSTPCRC Note: * Lower 16 bits of the address. R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'08 H'00 H'00 H'00 H'3F H'FF H'FF Address* H'FDE4 H'FDE6 H'FDEC H'FFA2 H'FDE8 H'FDE9 H'FDEA 19.2 19.2.1 Bit Register Descriptions Standby Control Register (SBYCR) : 7 SSBY 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 OPE 1 R/W 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- Initial value R/W : : 0 R/W SBYCR is an 8-bit readable/writable register that performs power-down mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Software Standby (SSBY): Determines the operating mode, in combination with other control bits, when a power-down mode transition is made by executing a SLEEP instruction. The SSBY setting is not changed by a mode transition due to an interrupt, etc. 599 Bit 7 SSBY 0 Description Transition to sleep mode after execution of SLEEP instruction in high-speed mode or medium-speed mode Transition to subsleep mode after execution of SLEEP instruction in subactive mode 1 Transition to software standby mode, subactive mode, or watch mode after execution of SLEEP instruction in high-speed mode or medium-speed mode Transition to watch mode or high-speed mode after execution of SLEEP instruction in subactive mode (Initial value) Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the time the MCU waits for the clock to stabilize when software standby mode, watch mode, or subactive mode is cleared and a transition is made to high-speed mode or medium-speed mode by means of a specific interrupt or instruction. With crystal oscillation, refer to table 19.5 and make a selection according to the operating frequency so that the standby time is at least 8 ms (the oscillation stabilization time). With an external clock, any selection* can be made. Note: * In the F-ZTAT version, a 16-state wait time cannot be used with an external clock. Use 8192 states or more. Bit 6 STS2 0 Bit 5 STS1 0 Bit 4 STS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states* (Initial value) Note: * Not used on the F-ZTAT version. Bit 2 to 0--Reserved: These bits cannot be modified and is always read as 0. Bit 3--Output Port Enable (OPE): Specifies whether the address bus and bus control signals (CS0 to CS3, AS, RD, HWR, and LWR) retain their output state or go to the high-impedance state in software standby mode and watch mode, and in a direct transition. 600 Bit 3 OPE 0 1 Description In software standby mode, watch mode, and in a direct transition, address bus and bus control signals are high-impedance In software standby mode, watch mode, and in a direct transition, address bus and bus control signals retain their output state (Initial value) 19.2.2 Bit System Clock Control Register (SCKCR) : 7 PSTOP 6 -- 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 -- 0 R/W 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W Initial value R/W : : 0 R/W SCKCR is an 8-bit readable/writable register that performs o clock output control and mediumspeed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--o Clock Output Disable (PSTOP): Controls o output. Bit 7 Description High-Speed Mode, Medium-Speed Mode, Sleep Mode, Subactive Mode Subsleep Mode o output (Initial value) Fixed high o output Fixed high Software Standby Mode, Watch Mode, Direct Transition Fixed high Fixed high Hardware Standby Mode High impedance High impedance PSTOP 0 1 Bits 6 to 3--Reserved: These bits should always be written with 0, and are always read as 0. 601 Bits 2 to 0--System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the clock for the bus master in high-speed mode and medium-speed mode. When operating the device after a transition to subactive mode or watch mode, bits SCK2 to SCK0 should all be cleared to 0. Bit 2 SCK2 0 Bit 1 SCK1 0 Bit 0 SCK0 0 1 1 0 1 1 0 0 1 1 -- Description Bus master is in high-speed mode Medium-speed clock is o/2 Medium-speed clock is o/4 Medium-speed clock is o/8 Medium-speed clock is o/16 Medium-speed clock is o/32 -- (Initial value) 19.2.3 Bit Low-Power Control Register (LPWRCR) : 7 DTON 6 LSON 0 R/W 5 NESEL 0 R/W 4 3 2 -- 0 R/W 1 STC1 0 R/W 0 STC0 0 R/W SUBSTP RFCUT 0 R/W 0 R/W Initial value R/W : : 0 R/W LPWRCR is an 8-bit readable/writable register that performs power-down mode control. LPWRCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized in software standby mode. Only bits 7 to 4 are described here; for details of the other bits, see section 18.2.2, Low-Power Control Register (LPWRCR). Bit 7--Direct-Transfer On Flag (DTON): Specifies whether a direct transition is made between high-speed mode, medium-speed mode, and subactive mode when making a power-down transition by executing a SLEEP instruction. The operating mode to which the transition is made after SLEEP instruction execution is determined by a combination of other control bits. 602 Bit 7 DTON 0 Description When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode* When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode (Initial value) 1 When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made directly to subactive mode*, or a transition is made to sleep mode or software standby mode When a SLEEP instruction is executed in subactive mode, a transition is made directly to high-speed mode, or a transition is made to subsleep mode Note: * When a transition is made to watch mode or subactive mode, high-speed mode must be set. Bit 6--Low-Speed On Flag (LSON): Determines the operating mode in combination with other control bits when making a power-down transition by executing a SLEEP instruction. Also controls whether a transition is made to high-speed mode or medium-speed mode, or to subactive mode when watch mode is cleared. Bit 6 LSON 0 Description When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode* When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode, or directly to high-speed mode After watch mode is cleared, a transition is made to high-speed mode 1 (Initial value) When a SLEEP instruction is executed in high-speed mode a transition is made to watch mode or subactive mode* When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode After watch mode is cleared, a transition is made to subactive mode Note: * When a transition is made to watch mode or subactive mode, high-speed mode must be set. 603 Bit 5--Noise Elimination Sampling Frequency Select (NESEL): Selects the frequency at which the subclock (oSUB) generated by the subclock oscillator is sampled with the clock (o) generated by the system clock oscillator. When o = 5 MHz or higher, clear this bit to 0. Bit 5 NESEL 0 1 Description Sampling at o divided by 8 Sampling at o divided by 4 (Initial value) Bit 4--Subclock Oscillator Control (SUBSTP): Controls operation and stopping of the subclock oscillator. Bit 4 SUBSTP 0 1 Description Subclock oscillator operates Subclock oscillator is stopped (Initial value) Note: When the subclock is not used, this bit should be set to 1. 19.2.4 Timer Control/Status Register (TCSR) WDT1 TCSR Bit : 7 OVF Initial value R/W : : 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 PSS 0 R/W 3 RST/NMI 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Note: * Only 0 can be written in bit 7, to clear the flag. TCSR is an 8-bit readable/writable register that performs selection of the WDT1 TCNT input clock, mode, etc. Only bit 4 is described here. For details of the other bits, see section 12.2.2, Timer Control/Status Register (TCSR). TCSR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 4--Prescaler Select (PSS): Selects the WDT1 TCNT input clock. This bit also controls the operation in a power-down mode transition. The operating mode to which a transition is made after execution of a SLEEP instruction is determined in combination 604 with other control bits. For details, see the description of Clock Select 2 to 0 in section 12.2.2, Timer Control/Status Register (TCSR). Bit 4 PSS 0 Description TCNT counts o-based prescaler (PSM) divided clock pulses When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode or software standby mode (Initial value) 1 TCNT counts oSUB-based prescaler (PSS) divided clock pulses When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, watch mode*, or subactive mode* When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode, watch mode, or high-speed mode Note: * When a transition is made to watch mode or subactive mode, high-speed mode must be set. 19.2.5 Module Stop Control Register (MSTPCR) MSTPCRA Bit : 7 6 5 4 3 2 1 0 MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value R/W MSTPCRB Bit : 7 6 5 4 3 2 1 0 : : 0 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W R/W MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value R/W MSTPCRC Bit : 7 6 5 4 3 2 1 0 : : 1 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W R/W MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value R/W : : 1 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W R/W MSTPCRA, MSTPCRB, and MSTPCRC are 8-bit readable/writable registers that perform module 605 stop mode control. MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. MSTPCRB and MSTPCRC are initialized to H'FF. They are not initialized in software standby mode. MSTPCRA, MSTPCRB, and MSTPCRC Bits 7 to 0--Module Stop (MSTPA7 to MSTPA0, MSTPB7 to MSTPB0, and MSTPC7 to MSTPC0): These bits specify module stop mode. See table 19.4 for the method of selecting on-chip supporting modules. MSTPCRA, MSTPCRB, and MSTPCRC Bits 7 to 0 MSTPA7 to MSTPA0, MSTPB7 to MSTPB0, and MSTPC7 to MSTPC0 0 1 Description Module stop mode is cleared (Initial value of MSTPA7, MSTPA6) Module stop mode is set (Initial value of except MSTPA7 to MSTPA6) 19.3 Medium-Speed Mode When the SCK2 to SCK0 bits in SCKCR are set to 1 in high-speed mode, the operating mode changes to medium-speed mode at the end of the bus cycle. In medium-speed mode, the CPU operates on the operating clock (o/2, o/4, o/8, o/16, or o/32) specified by the SCK2 to SCK0 bits. The bus master other than the CPU (the DTC) also operates in medium-speed mode. On-chip supporting modules other than the bus masters always operate on the high-speed clock (o). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if o/4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR are cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, and the LSON bit in LPWRCR and the PSS bit in TCSR (WDT1) are both cleared to 0, a transition is made to software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is driven low, a transition is made to the reset state, and medium-speed mode is cleared. The same applies in the case of a reset caused by overflow of the watchdog timer. 606 When the STBY pin is driven low, a transition is made to hardware standby mode. Figure 19.2 shows the timing for transition to and clearance of medium-speed mode. Medium-speed mode o, supporting module clock Bus master clock Internal address bus SBYCR SBYCR Internal write signal Figure 19.2 Medium-Speed Mode Transition and Clearance Timing 19.4 19.4.1 Sleep Mode Sleep Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR are both cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained. Other supporting modules do not stop. 19.4.2 Clearing Sleep Mode Sleep mode is cleared by all interrupts, or with the RES pin or STBY pin. Clearing with an Interrupt: When an interrupt request signal is input, sleep mode is cleared and interrupt exception handling is started. Sleep mode will not be cleared if interrupts are disabled, or if interrupts other than NMI have been masked by the CPU. Clearing with the RES Pin: When the RES pin is driven low, the reset state is entered. When the RES pin is driven high after the prescribed reset input period, the CPU begins reset exception handling. Clearing with the STBY Pin: When the STBY pin is driven low, a transition is made to hardware standby mode. 607 19.5 19.5.1 Module Stop Mode Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 19.4 shows MSTP bits and the corresponding on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating again at the end of the bus cycle. In module stop mode, the internal states of modules other than the A/D converter are retained. After reset release, all modules other than the DTC are in module stop mode. When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. When a transition is made to sleep mode with all modules stopped (MSTPCR = H'FFFFFF), the bus controller and I/O ports also stop operating, enabling current dissipation to be further reduced. 608 Table 19.4 MSTP Bits and Corresponding On-Chip Supporting Modules Register MSTPCRA Bit MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 MSTPCRB MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 MSTPCRC MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Note: * Reserved. Module --* Data transfer controller (DTC) 16-bit timer pulse unit (TPU) 8-bit timers (TMR0, TMR1) --* --* A/D converter --* Serial communication interface 0 (SCI0) Serial communication interface 1 (SCI1) --* --* --* --* --* --* Serial communication interface 3 (SCI3) --* --* PC break controller (PBC) --* --* --* --* 19.5.2 Usage Note DTC Module Stop Mode: Depending on the operating status of the DTC, the MSTPA6 bit may not be set to 1. Setting of the DTC module stop mode should be carried out only when the DTC is not activated. For details, see section 8, Data Transfer Controller (DTC). On-Chip Supporting Module Interrupts: Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been 609 requested, it will not be possible to clear the CPU interrupt source or DTC activation source. Interrupts should therefore be disabled before setting module stop mode. Writing to MSTPCR: MSTPCR should be written to only by the CPU. 19.6 19.6.1 Software Standby Mode Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT1) is cleared to 0, software standby mode is entered. In this mode, the CPU, on-chip supporting modules, and system clock oscillator all stop. However, the contents of the CPU's internal registers, RAM data, and the states of onchip supporting module other than the A/D converter, and of the I/O ports, are retained. The address bus and bus control signals are placed in the high-impedance state. In this mode the oscillator stops, and therefore power dissipation is significantly reduced. 19.6.2 Clearing Software Standby Mode Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ7), or by means of the RES pin or STBY pin. Clearing with an Interrupt: When an NMI or IRQ0 to IRQ7 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. When software standby mode is cleared with an IRQ0 to IRQ7 interrupt, set the corresponding enable bit to 1 and ensure that an interrupt of higher priority than interrupts IRQ0 to IRQ7 is not generated. Software standby mode cannot be cleared if the interrupt has been masked by the CPU side or has been designated as a DTC activation source. Clearing with the RES Pin: When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling. Clearing with the STBY Pin: When the STBY pin is driven low, a transition is made to hardware standby mode. 610 19.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time). Table 19.5 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 19.5 Oscillation Stabilization Time Settings STS2 STS1 STS0 Standby Time 0 0 0 1 1 0 1 1 0 0 1 1 0 1 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved 16 states 13 MHz 0.6 1.3 2.5 5.0 10.1 20.2 -- 1.2 10 MHz 0.8 1.6 3.3 6.6 13.1 26.2 -- 1.6 8 MHz 1.0 2.0 4.1 8.2 16.4 32.8 -- 2.0 6 MHz 1.3 2.7 5.5 10.9 21.8 43.6 -- 1.7 4 MHz 2.0 4.1 8.2 16.4 32.8 65.6 -- 4.0 2 MHz 4.1 8.2 16.4 32.8 65.5 131.2 -- 8.0 -- s Unit ms : Recommended time setting Using an External Clock: Any value can be set. Normally, use of the minimum time is recommended. Note: A 16-state standby time cannot be used in the F-ZTAT version; a standby time of 8192 states or longer should be used. 19.6.4 Software Standby Mode Application Example Figure 19.3 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin. 611 Oscillator o NMI NMIEG SSBY NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down mode) Oscillation stabilization time tOSC2 NMI exception handling SLEEP instruction Figure 19.3 Software Standby Mode Application Example 19.6.5 Usage Notes I/O Port States: In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus and bus control signal output is also retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. Current Dissipation During the Oscillation Stabilization Wait Period: Current dissipation increases during the oscillation stabilization wait period. 19.7 19.7.1 Hardware Standby Mode Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. 612 In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while the LSI is in hardware standby mode. Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillation stabilizes (at least tOSC1--the oscillation stabilization time--when using a crystal oscillator). When the RES pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 19.7.2 Hardware Standby Mode Timing Figure 19.4 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation stabilization time, then changing the RES pin from low to high. Oscillator RES STBY Oscillation stabilization time tOSC1 Reset exception handling Figure 19.4 Hardware Standby Mode Timing (Example) 613 19.8 19.8.1 Watch Mode Watch Mode If a SLEEP instruction is executed in high-speed mode or subactive mode when the SSBY in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT1) is set to 1, the CPU makes a transition to watch mode. In this mode, the CPU, all on-chip supporting modules except WDT1 and system clock oscillator stop. The contents of CPU internal registers and on-chip RAM, and the states of the on-chip supporting functions (except the A/D converter) and I/O ports, are retained. The address bus and bus control signals go to the high-impedance state. When a transition is made to watch mode, bits SCK2 to SCK0 in SCKCR must all be cleared to 0. 19.8.2 Clearing Watch Mode Watch mode is cleared by an interrupt (WOVI1 interrupt, NMI pin, or pins IRQ0 to IRQ7), or by means of the RES pin or STBY pin. Clearing with an Interrupt: When an interrupt request signal is input, watch mode is cleared and a transition is made to high-speed mode or medium-speed mode if the LSON bit in LPWRCR is cleared to 0, or to subactive mode if the LSON bit is set to 1. When making a transition to highspeed mode, after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are supplied to the entire chip, and interrupt exception handling is started. Watch mode cannot be cleared with an IRQ0 to IRQ7 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip supporting module interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable register or masked by the CPU. See section 19.6.3, Setting Oscillation Stabilization Time after Clearing Software Standby Mode, for the oscillation stabilization time setting when making a transition from watch mode to highspeed mode. Clearing with the RES Pin: See "Clearing with the RES Pin" in section 19.6.2, Clearing Software Standby Mode. Clearing with the STBY Pin: When the STBY pin is driven low, a transition is made to hardware standby mode. 614 19.8.3 Usage Notes I/O Port States: In watch mode, I/O port states are retained. If the OPE bit is set to 1, address bus and bus control signal output is also retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. Current Dissipation during the Oscillation Stabilization Wait Period: Current dissipation increases during the oscillation stabilization wait period. 19.9 19.9.1 Subsleep Mode Subsleep Mode If a SLEEP instruction is executed in subactive mode when the SSBY in SBYCR is cleared to 0, the LSON bit in LPWRCR is set to 1, and the PSS bit in TCSR (WDT1) is set to 1, the CPU makes a transition to subsleep mode. In this mode, the CPU, all on-chip supporting modules except TMR0, TMR1, WDT0, and WDT1 and system clock oscillator stop. The contents of CPU internal registers and on-chip RAM, and the states of the on-chip supporting functions (except the A/D converter) and I/O ports, are retained. 19.9.2 Clearing Subsleep Mode Subsleep mode is cleared by an interrupt (on-chip supporting module interrupt, NMI pin, or pin IRQ0 to IRQ7), or by means of the RES pin or STBY pin. Clearing with an Interrupt: When an interrupt request signal is input, subsleep mode is cleared and interrupt exception handling is started. Subsleep mode cannot be cleared with an IRQ0 to IRQ7 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip supporting module interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable register or masked by the CPU. Clearing with the RES Pin: See "Clearing with the RES Pin" in section 19.6.2, Clearing Software Standby Mode. Clearing with the STBY Pin: When the STBY pin is driven low, a transition is made to hardware standby mode. 615 19.10 19.10.1 Subactive Mode Subactive Mode If a SLEEP instruction is executed in high-speed mode when the SSBY bit in SBYCR, the DTON bit in LPWRCR, and the PSS bit in TCSR (WDT1) are all set to 1, the CPU makes a transition to subactive mode. When an interrupt is generated in watch mode, if the LSON bit in LPWRCR is set to 1, a transition is made to subactive mode. When an interrupt is generated in subsleep mode, a transition is made to subactive mode. In subactive mode, the CPU performs sequential program execution at low speed on the subclock. In this mode, all on-chip supporting modules except PBC, TMR0, TMR1, WDT0, and WDT1, and system clock oscillator stop. When operating the device in subactive mode, bits SCK2 to SCK0 in SBYCR must all be cleared to 0. 19.10.2 Clearing Subactive Mode Subactive mode is cleared by a SLEEP instruction, or by means of the RES pin or STBY pin. Clearing with a SLEEP Instruction: When a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT1) is set to 1, subactive mode is cleared and a transition is made to watch mode. When a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the LSON bit in LPWRCR is set to 1, and the PSS bit in TCSR (WDT1) is set to 1, a transition is made to subsleep mode. When a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the DTON bit is set to 1 and the LSON bit is cleared to 0 in LPWRCR, and the PSS bit in TCSR (WDT1) is set to 1, a transition is made directly to high-speed mode (SCK0 to SCK2 all 0). Fort details of direct transition, see section 19.11, Direct Transition. Clearing with the RES Pin: See "Clearing with the RES Pin" in section 19.6.2, Clearing Software Standby Mode. Clearing with the STBY Pin: When the STBY pin is driven low, a transition is made to hardware standby mode 616 19.11 19.11.1 Direct Transition Overview of Direct Transition There are three operating modes in which the CPU executes programs: high-speed mode, mediumspeed mode, and subactive mode. A transition between high-speed mode and subactive mode without halting the program is called a direct transition. A direct transition can be carried out by setting the DTON bit in LPWRCR to 1 and executing a SLEEP instruction. After the transition, direct transition interrupt exception handling is started. Direct Transition from High-Speed Mode to Subactive Mode: If a SLEEP instruction is executed in high-speed mode while the SSBY bit in SBYCR, the LSON bit and DTON bit in LPWRCR, and the PSS bit in TSCR (WDT1) are all set to 1, a transition is made to subactive mode. Direct Transition from Subactive Mode to High-Speed Mode: If a SLEEP instruction is executed in subactive mode while the SSBY bit in SBYCR is set to 1, the LSON bit is cleared to 0 and the DTON bit is set to 1 in LPWRCR, and the PSS bit in TSCR (WDT1) is set to 1, after the elapse of the time set in bits STS2 to STS0 in SBYCR, a transition is made to directly to highspeed mode. 19.12 o Clock Output Disabling Function Output of the o clock can be controlled by means of the PSTOP bit in SCKCR and the corresponding DDR bit. When the PSTOP bit is set to 1, the o clock is stopped at the end of the bus cycle, and o output goes high. o clock output is enabled when PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, o clock output is disabled and input port mode is set. Table 19.6 shows the state of the o pin in each processing mode. Table 19.6 o Pin State in Each Processing Mode DDR PSTOP Hardware standby mode Software standby mode, watch mode, direct transition Sleep mode, subsleep mode High-speed mode, medium-speed mode, subactive mode 0 -- 1 0 1 1 High Impedance High Impedance High Impedance High Impedance Fixed high High Impedance o output High Impedance o output Fixed high Fixed high Fixed high 617 19.13 19.13.1 Usage Notes I/O Port Status In software standby mode and watch mode, I/O port states are retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. 19.13.2 Current Dissipation during Oscillation Stabilization Wait Period Current dissipation increases during the oscillation stabilization wait period. 19.13.3 DTC Module Stop Depending on the operating status of the DTC, the MSTPA6 bit may not be set to 1. Setting of the DTC module stop mode should be carried out only when the respective module is not activated. For details, refer to section 8, Data Transfer Controller (DTC). 19.13.4 On-Chip Supporting Module Interrupt * Module stop mode Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled before entering module stop mode. * Subactive mode/Watch mode On-chip peripheral modules (DTC, TPU) that stop operation in subactive mode cannot clear interrupts in subactive mode. Therefore, if subactive mode is entered when an interrupt is requested, CPU interrupt factors cannot be cleared. Interrupts should therefore be disabled before executing the SLEEP instruction and entering subactive or watch mode. 19.13.5 Writing to MSTPCR MSTPCR should only be written to by the CPU. 618 19.13.6 Entering Subactive/Watch Mode and DTC Module Stop To enter subactive or watch mode, set DTC to module stop (write 1 to the MSTPA6 bit) and reading the MSTPA6 bit as 1 before transiting mode. After transiting from subactive mode to active mode, clear module stop. When DTC activation factor occurs in subactive mode, DTC is activated when module stop is cleared after active mode is entered. 619 620 Section 20 Electrical Characteristics 20.1 Power Supply Voltage and Operating Frequency Range Power supply voltage and operating frequency ranges (shaded areas) are shown in figure 20.1. -- Preliminary -- (1) Power Supply Voltage and Oscillation Frequency Range (F-ZTAT version) f (MHz) 13.5 System clock f (kHz) 160 Subclock 76.8 2.0 0 2.7 3.6 AVcc (V) * Active (high-speed/medium-speed) mode * Sleep mode 0 2.7 3.6 * All operating modes Vcc (V) (2) Power Supply Voltage and Instruction Execution Time Range (F-ZTAT version) t (ns) 74 System clock t (s) 13.0 Subclock 6.25 500 0 2.7 3.6 Vcc (V) * Active (high-speed/medium-speed) mode 0 2.7 * Subactive mode 3.6 Vcc (V) Figure 20.1 Power Supply Voltage and Operating Ranges 621 20.2 20.2.1 Electrical Characteristics Absolute Maximum Ratings Table 20.1 lists the absolute maximum ratings. Table 20.1 Absolute Maximum Ratings Item Power supply voltage Input voltage (except port 4, TESTD, LOBAT) Input voltage (port 4, TESTD, LOBAT) Reference power supply voltage Analog power supply voltage Analog input voltage Operating temperature Storage temperature Symbol VCC Vin Vin Vr ef AVCC VAN Topr Tstg Value -0.3 to +4.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to AVCC +0.3 -0.3 to +4.3 -0.3 to AVCC +0.3 -20 to +75 -55 to +125 -- Preliminary -- Unit V V V V V V C C Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. 622 20.2.2 DC Characteristics DC characteristics are shown in table 20.2 and permissible output currents in table 20.3. Table 20.2 DC Characteristics (1) Conditions (F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C* Item Schmitt trigger input voltage Input high voltage IRQ0 to IRQ7 Symbol VT - VT + + - -- Preliminary -- Min VCC x 0.2 -- VCC x 0.9 Typ -- -- Max -- VCC x 0.8 -- VCC + 0.3 Test Unit Conditions V V V V VT - VT VCC x 0.05 -- RES, STBY, NMI, VIH MD2 to MD0, FWE, IFIN EXTAL, ports 1, 3, A to G, EXTS0, EXTS1 Port 4, TESTD, LOBAT -- VCC x 0.8 -- VCC + 0.3 V VCC x 0.8 -0.3 -- -- AVCC + 0.3 V VCC x 0.1 V Input low voltage RES, STBY, VIL MD2 to MD0, FWE, IFIN NMI, EXTAL, ports 1, 3, 4, A to G, EXTS0, EXTS1, TESTD, LOBAT -0.3 -- VCC x 0.2 V Output high voltage Output low voltage Input leakage current All output pins VOH VOL | Iin | VCC - 0.5 VCC - 1.0 -- -- -- -- -- -- -- -- -- -- 0.4 0.4 1.0 1.0 V V V V A A I OH = -200 A I OH = -1 mA I OL = 0.4 mA I OL = 0.8 mA Vin = 0.2 to VCC - 0.2 V All output pins RES STBY, NMI, MD2 to MD0, FWE, IFIN, EXTS0, EXTS1 Port 4, TESTD, LOBAT -- -- -- -- 1.0 A Vin = 0.2 to AVCC - 0.2 V 623 Item Three-state Ports 1, 3, A to G leakage current (off state) Input pull-up MOS current Ports A to E Symbol | ITSI | Min -- Typ -- Max 1.0 Test Unit Conditions A Vin = 0.2 to VCC - 0.2 V Vin = 0 V -IP 10 -- 300 A Note: * If the A/D converter is not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage between 2.0 V and 3.6 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC. 624 Table 20.2 DC Characteristics (2) Conditions (F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C*1 Item Input RES capacitance NMI All input pins except the above Current Normal dissipation* 2 operation Sleep mode All modules stopped Medium-speed mode (o/32) Subactive mode I CC* 4 Symbol Min Cin -- -- -- Typ -- -- -- Max 30 30 15 Unit pF pF pF -- Preliminary -- Test Conditions Vin = 0 V f = 1 MHz Ta = 25C -- -- -- 13 26 mA VCC = 3.0 V VCC = 3.6 V 9 20 mA VCC = 3.0 V VCC = 3.6 V 12 -- mA f = 13.5 MHz f = 13.5 MHz f = 13.5 MHz, VCC = 3.0 V (reference values) f = 13.5 MHz, VCC = 3.0 V (reference values) Using 160 kHz crystal resonator VCC = 3.0 V Using 160 kHz crystal resonator VCC = 3.0 V Using 160 kHz crystal resonator VCC = 3.0 V Ta 50C not using subclock 50C < Ta not using subclock -- 9 -- mA -- 150 280 A Subsleep mode -- 120 230 A Watch mode -- 50 90 A Standby mode* 3 -- -- 0.01 10 A VCC = 3.0 V VCC = 3.6 V -- 50 VCC = 3.6 V 625 Item Analog power supply current Reference power supply current During A/D conversion Idle During A/D conversion Idle Symbol Min AI CC -- -- AI CC -- -- VRAM 2.0 Typ 0.2 0.01 0.2 0.01 -- Max 1.0 5.0 1.0 5.0 -- Unit mA A mA A V Test Conditions AVCC = 3.0 V Vref = 3.0 V RAM standby voltage Notes: *1 If the A/D converters is not used, do not leave the AVCC, Vref, and AVSS pins open. Apply a voltage between 2.0 V and 3.6 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC. *2 Current dissipation values are for V IH min = VCC - 0.2 V and VIL max = 0.2 V with all output pins unloaded and all MOS input pull-ups in the off state. *3 The values are for VRAM V CC < 2.7 V, VIH min = VCC - 0.2, and VIL max = 0.2 V. *4 I CC depends on VCC and f as follows: I CC max = 1.0 (mA) + 0.51 (mA/(MHz * V)) x V CC x f (normal operation) I CC max = 1.0 (mA) + 0.39 (mA/(MHz * V)) x V CC x f (sleep mode) 626 Table 20.3 Permissible Output Currents Conditions (F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C Item Permissible output low current (per pin) Permissible output low current (total) Permissible outputhigh current (per pin) Permissible outputhigh current (total) All output pins Total of all output pins All output pins Total of all output pins Symbol I OL IOL -I OH -IOH Min -- -- -- -- -- Preliminary -- Typ -- -- -- -- Max 1.0 60 1.0 30 Unit mA mA mA mA Note: To protect chip reliability, do not exceed the output current values in table 20.3. 20.2.3 AC Characteristics Figure 20.2 shows the AC test conditions. 3V RL Chip output pin C RH C = 30 pF: RL: 2.4 k RH: 12 k Input/output timing measurement level: Low: 0.8 V High: 2.0 V Figure 20.2 Output Load Circuit 627 Clock Timing Table 20.4 shows the clock timing. Table 20.4 Clock Timing -- Preliminary -- Conditions (F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 160 kHz, 76.8 kHz, 2 MHz to 13.5 MHz, Ta = -20C to +75C Item Clock cycle time Clock pulse high width Clock pulse low width Clock rise time Clock fall time Reset oscillation stabilization time (crystal) Software standby oscillation stabilization time (crystal) External clock output stabilization delay time Subclock oscillation stabilization time Subclock oscillator frequency Subclock (o SUB) cycle time Symbol t cyc t CH t CL t Cr t Cf t OSC1 t OSC2 t DEXT t OSC3 f SUB t SUB Min 74 25 25 -- -- 20 8 500 -- -- -- Typ -- -- -- -- -- -- -- -- -- 160, 76.8 6.25, 13.0 Max 500 -- -- 10 10 -- -- -- 2 -- -- Unit ns ns ns ns ns ms ms s s kHz s Figure 20.4 Figure 19.3 Figure 20.4 Test Conditions Figure 20.3 628 Control Signal Timing Table 20.5 shows the control signal timing. Table 20.5 Control Signal Timing --Preliminary-- Conditions (F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 160 kHz, 76.8 kHz, 2 MHz to 13.5 MHz, Ta = -20C to +75C Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (in recovery from software standby mode) IRQ setup time IRQ hold time IRQ pulse width (in recovery from software standby mode) Symbol t RESS t RESW t NMIS t NMIH t NMIW t IRQS t IRQH t IRQW Min 250 20 250 10 200 250 10 200 Max -- -- -- -- -- -- -- -- ns Unit ns t cyc ns Figure 20.6 Test Conditions Figure 20.5 629 Bus Timing Table 20.6 shows the bus timing. Table 20.6 Bus Timing -- Preliminary -- Conditions (F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 13.5 MHz, Ta = -20C to +75C Item Address delay time Address setup time Address hold time CS delay time AS delay time RD delay time 1 RD delay time 2 Read data setup time Read data hold time Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Read data access time 5 WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time Write data hold time WAIT setup time WAIT hold time BREQ setup time BACK delay time Bus floating time Symbol t AD t AS t AH t CSD t ASD t RSD1 t RSD2 t RDS t RDH t ACC1 t ACC2 t ACC3 t ACC4 t ACC5 t WRD1 t WRD2 t WSW1 t WSW2 t WDD t WDS t WDH t WTS t WTH t BRQS t BACD t BZD Min -- 0.5 x tcyc - 30 0.5 x tcyc - 15 -- -- -- -- 30 0 -- -- -- -- -- -- -- 1.0 x tcyc - 30 1.5 x tcyc - 30 -- 0.5 x tcyc - 37 0.5 x tcyc - 15 50 10 50 -- -- Max 50 -- -- 50 50 50 50 -- -- 1.0 x tcyc - 65 1.5 x tcyc - 65 2.0 x tcyc - 65 2.5 x tcyc - 65 3.0 x tcyc - 65 50 50 -- -- 70 -- -- -- -- -- 50 80 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 20.12 Figure 20.9 Figure 20.7 Figure 20.8 Test Conditions Figure 20.7 to Figure 20.11 630 Timing of On-Chip Supporting Modules Table 20.7 shows the timing of the on-chip supporting modules. Table 20.7 Timing of On-Chip Supporting Modules -- Preliminary -- Conditions (F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 160 kHz, 76.8 kHz, 2 MHz to 13.5 MHz, Ta = -20C to +75C Item I/O ports Output data delay time Input data setup time Input data hold time TPU Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width WDT1 SCI Single-edge Both-edge Symbol t PWD t PRS t PRH t TOCD t TICS t TCKS t TCKWH t TCKWL t BUZD t Scyc Min -- 50 50 -- 40 40 1.5 2.5 -- 4 6 t SCKW t SCKr t SCKf t TXD t RXS t RXH t TRGS 0.4 -- -- -- 75 75 40 Max 100 -- -- 100 -- -- -- -- 100 -- -- 0.6 1.5 1.5 100 -- -- -- ns ns ns ns Figure 20.19 Figure 20.18 t scyc t cyc ns t cyc Figure 20.16 Figure 20.17 ns t cyc Figure 20.15 ns Figure 20.14 Unit ns Test Conditions Figure 20.13 BUZZ output delay time Input clock cycle Asynchronous Synchronous Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) A/D converter Trigger input setup time 631 20.2.4 A/D Conversion Characteristics Table 20.8 shows the A/D conversion characteristics. Table 20.8 A/D Conversion Characteristics -- Preliminary -- Conditions (F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 13.5 MHz, Ta = -20C to +75C Item Resolution Conversion time Analog input capacitance Permissible signal source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min 10 9.9 -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- Max 10 -- 20 5 6.0 4.0 4.0 0.5 8.0 Unit Bit s pF k LSB LSB LSB LSB LSB 632 20.2.5 Flash Memory Characteristics Table 20.9 shows the flash memory characteristics. Table 20.9 Flash Memory Characteristics -- Preliminary -- Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, VCC = 3.0 V to 3.6 V (program/erase operating voltage range), Ta = -20C to +75C (program/erase operating temperature range) Item Programming time*1, *2, *4 Erase time*1, *3, *5 Rewrite times Programming Wait time after SWE1 bit setting* 1, 4 1 Symbol tP tE NWEC tsswe tspsu tsp10 tsp30 tsp200 Wait time after P1 bit clearing*1 Wait time after PSU1 bit clearing*1 Wait time after PV1 bit setting*1 Wait time after H'FF dummy write* Wait time after PV1 bit clearing*1 Wait time after SWE1 bit clearing* 1, 4 1 1 Min -- -- -- 1 50 8 28 198 5 5 4 2 2 100 -- -- 1 100 10 10 10 20 2 4 100 -- Typ 10 100 -- 1 50 10 30 200 5 5 4 2 2 100 -- -- 1 100 10 10 10 20 2 4 100 -- Max 200 1200 100 -- -- 12 32 202 -- -- -- -- -- -- 6*4 994* -- -- 100 -- -- -- -- -- -- 100 4 Unit ms/ 128 bytes ms/block Times s s s s s s s s s s s Times s s ms s s s s s s Times Test Conditions Wait time after PSU1 bit setting*1 Wait time after P1 bit setting* * 1n6 7 n 1000 tcp tcpsu tspv tspvr tcpv tcswe N1 N2 tsswe tsesu tse tce tcesu tsev tsevr tcev tcswe N 1 1 Maximum number of programming operations * * Erasing Wait time after SWE1 bit setting*1 Wait time after ESU1 bit setting* Wait time after E1 bit clearing*1 Wait time after ESU1 bit clearing*1 Wait time after EV1 bit setting* 1 Wait time after E1 bit setting*1, *5 Wait time after H'FF dummy write*1 Wait time after EV1 bit clearing* 1, Wait time after SWE1 bit clearing Maximum number of erases* * 5 Notes: *1 Follow the program/erase algorithms when making the time settings. *2 Programming time per 128 bytes. (Indicates the total time during which the P1 bit is set in flash memory control register 1 (FLMCR1). Does not include the program-verify time.) 633 *3 Time to erase one block. (Indicates the time during which the E1 bit is set in FLMCR1. Does not include the erase-verify time.) *4 Maximum programming time (tP(max) = Wait time after P1 bit setting (tsp) x maximum number of writes (N)) (tsp30 + tsp10) x 6 + (tsp200) x 994 *5 For the maximum erase time (tE(max)), the following relationship applies between the wait time after E1 bit setting (t se) and the maximum number of erases (N): t E(max) = Wait time after E1 bit setting (tse) x maximum number of erases (N) 634 20.3 Operational Timing This section shows timing diagrams. 20.3.1 Clock Timing Clock timing diagrams are shown below. System Clock Timing Figure 20.3 shows the system clock timing. tcyc tCH o tCL tCr tCf Figure 20.3 System Clock Timing Oscillation Stabilization Timing Figure 20.4 shows the oscillation stabilization timing. EXTAL tDEXT VCC tDEXT STBY tOSC1 RES tOSC1 o Figure 20.4 Oscillation Stabilization Timing 635 20.3.2 Control Signal Timing Control signal timing diagrams are shown below. Reset Input Timing Figure 20.5 shows the reset input timing. o tRESS RES tRESW tRESS Figure 20.5 Reset Input Timing Interrupt Input Timing Figure 20.6 shows the timing of NMI and IRQ interrupt input. o tNMIS NMI tNMIW tNMIH IRQ tIRQW tIRQS IRQ Edge input tIRQS IRQ Level input tIRQH Figure 20.6 Interrupt Input Timing 636 20.3.3 Bus Timing The following bus timing diagrams are shown here. Basic Bus Timing: Two-State Access Figure 20.7 shows the timing of external two-state access. T1 T2 o tAD A23 to A0 tAS tAH tCSD CS3 to CS0 tASD AS tASD tRSD1 RD (read) tAS tACC2 tRSD2 tACC3 D15 to D0 (read) tRDS tRDH tWRD2 HWR, LWR (write) tWRD2 tAH tAS tWDD tWSW1 tWDH D15 to D0 (write) Figure 20.7 Basic Bus Timing (Two-State Access) 637 Basic Bus Timing: Three-State Access Figure 20.8 shows the timing of external three-state access. T1 T2 T3 o tAD A23 to A0 tAS tAH tCSD CS3 to CS0 tASD AS tASD tRSD1 RD (read) tAS tACC4 tRSD2 tACC5 D15 to D0 (read) tRDS tRDH tWRD1 HWR, LWR (write) tWDD tWDS D15 to D0 (write) tWSW2 tWRD2 tAH tWDH Figure 20.8 Basic Bus Timing (Three-State Access) 638 Basic Bus Timing: Three-State Access with One Wait Figure 20.9 shows the timing of external three-state access with one wait inserted. T1 T2 TW T3 o A23 to A0 CS3 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH WAIT tWTS tWTH Figure 20.9 Basic Bus Timing (Three-State Access with One Wait State) 639 Burst ROM Access Timing: Two-State Figure 20.10 shows the timing of burst ROM two-state access. T1 T2 or T3 T1 T2 o tAD A23 to A0 tAS tAH CS0 tASD tASD AS tRSD2 RD (read) tACC3 D15 to D0 (read) tRDS tRDH Figure 20.10 Burst ROM Access Timing (Two-State Access) 640 Burst ROM Access Timing: One-State Figure 20.11 shows the timing of burst ROM one-state access. T1 o T2 or T3 T1 tAD A23 to A0 CS0 AS tRSD2 RD (read) tACC1 D15 to D0 (read) tRDS tRDH Figure 20.11 Burst ROM Access Timing (One-State Access) 641 External Bus Release Timing Figure 20.12 shows the timing of external bus release. o tBRQS tBRQS BREQ tBACD BACK tBZD A23 to A0, CS3 to CS0, AS, RD, HWR, LWR tBACD tBZD Figure 20.12 External Bus Release Timing 20.3.4 Timing of On-Chip Supporting Modules Figures 20.13 to 20.19 show the timing of the on-chip supporting modules. T1 o T2 tPRS Port 1, 3, 4, A to G (read) tPRH tPWD Port 1, 3, A to G (write) Figure 20.13 I/O Port Input/Output Timing 642 o tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA2, TIOCB0, TIOCC0, TIOCD0 Figure 20.14 TPU Input/Output Timing o tTCKS TCLKA to TCLKB tTCKWL tTCKWH tTCKS Figure 20.15 TPU Clock Input Timing o tBUZD BUZZ tBUZD Figure 20.16 WDT1 Output Timing tSCKW SCK0, SCK1 tScyc tSCKr tSCKf Figure 20.17 SCK Clock Input Timing 643 SCK0, SCK1 tTXD TxD0, TxD1 (transit data) tRXS RxD0, RxD1 (receive data) tRXH Figure 20.18 SCI Input/Output Timing (Clock Synchronous Mode) o tTRGS ADTRG Figure 20.19 A/D Converter External Trigger Input Timing 644 Appendix A Instruction Set A.1 Instruction List Operand Notation Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / ( ) <> :8/:16/:24/:32 General register (destination)*1 General register (source)*1 General register*1 General register (32-bit register) Multiply-and-accumulate register (32-bit register)*2 Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Add Subtract Multiply Divide Logical AND Logical OR Logical exclusive OR Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Logical NOT (logical complement) Contents of operand 8-, 16-, 24-, or 32-bit length Notes: *1 General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). *2 The MAC register cannot be used in the LSI. 645 Condition Code Notation Symbol Changes according to the result of instruction * 0 1 -- Undetermined (no guaranteed value) Always cleared to 0 Always set to 1 Not affected by execution of the instruction 646 Table A-1 Instruction Set (1) Data Transfer Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code Operation #xx:8Rd8 IHNZVC ---- ---- ---- ---- ---- ---- ---- ---- @aa:32Rd8 Rs8@ERd ---- ---- Rs8@(d:16,ERd) Rs8@(d:32,ERd) ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- No. of States*1 Advanced 1 1 2 3 5 3 2 3 4 2 3 5 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) Mnemonic MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd B W4 W W 2 2 B B B B 8 2 2 4 6 B 4 B 2 B 6 B 4 B 2 B 2 B 8 B 4 B 2 @ERsRd8 @(d:16,ERs)Rd8 @(d:32,ERs)Rd8 B 2 Rs8Rd8 B2 MOV @@aa -- @ERsRd8,ERs32+1ERs32 @aa:8Rd8 @aa:16Rd8 ERd32-1ERd32,Rs8@ERd Rs8@aa:8 Rs8@aa:16 Rs8@aa:32 #xx:16Rd16 Rs16Rd16 @ERsRd16 ---- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 3 2 3 4 2 1 2 647 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa -- MOV.L @aa:32,ERd L 8 @aa:32ERd32 ---- 648 Addressing Mode/ Instruction Length (Bytes) Condition Code Operation @(d:16,ERs)Rd16 @(d:32,ERs)Rd16 2 4 6 2 4 8 2 4 6 Rs16@ERd Rs16@(d:16,ERd) Rs16@(d:32,ERd) @aa:32Rd16 @aa:16Rd16 ---- ---- IHNZVC 0-- 0-- 0-- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- ---- ---- #xx:32ERd32 2 4 6 10 4 6 ERs32ERd32 @ERsERd32 @(d:16,ERs)ERd32 @(d:32,ERs)ERd32 @ERsERd32,ERs32+4ERs32 @aa:16ERd32 ---- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- Mnemonic MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd L L L L L L L6 W W W W W W W W W W 8 @ERsRd16,ERs32+2ERs32 -- -- W 4 3 5 3 3 4 2 3 5 3 3 4 3 1 4 5 7 5 5 6 ERd32-2ERd32,Rs16@ERd -- -- Rs16@aa:16 Rs16@aa:32 No. of States*1 Advanced MOV Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 0-- 0-- 4 5 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa -- Mnemonic MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) L MOV.L ERs,@(d:32,ERd) L MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn LDM @SP+,(ERm-ERn) L 4 L 4 W 2 L 4 W 2 L 8 ERs32@aa:32 @SPRn16,SP+2SP @SPERn32,SP+4SP SP-2SP,Rn16@SP SP-4SP,ERn32@SP (@SPERn32,SP+4SP) Repeated for each register restored STM (ERm-ERn),@-SP L 4 (SP-4SP,ERn32@SP) Repeated for each register saved MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 Cannot be used in the LSI Cannot be used in the LSI L 6 ERs32@aa:16 L 4 10 ERs32@(d:32,ERd) 6 ERs32@(d:16,ERd) L 4 ERs32@ERd ---- ---- ---- Operation IHNZVC MOV 0-- 0-- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- ------------ 7 5 5 6 3 5 3 5 7/9/11 [1] ERd32-4ERd32,ERs32@ERd -- -- POP LDM STM ------------ PUSH 7/9/11 [1] MOVFPE [2] [2] MOVTPE 649 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa -- ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDX #xx:8,Rd ADDX Rs,Rd ADDS #1,ERd ADDS #2,ERd ADDS #4,ERd INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd DAA Rd SUB.B Rs,Rd SUB.W #xx:16,Rd B W4 B 2 2 L 2 L 2 W 2 W 2 B 2 L 2 L 2 L 2 B 2 B2 L 2 L6 W 2 Rd16+Rs16Rd16 ERd32+#xx:32ERd32 ERd32+ERs32ERd32 Rd8+#xx:8+CRd8 Rd8+Rs8+CRd8 ERd32+1ERd32 ERd32+2ERd32 ERd32+4ERd32 Rd8+1Rd8 Rd16+1Rd16 Rd16+2Rd16 ERd32+1ERd32 ERd32+2ERd32 Rd8 decimal adjustRd8 Rd8-Rs8Rd8 Rd16-#xx:16Rd16 W4 Rd16+#xx:16Rd16 B 2 Rd8+Rs8Rd8 -- -- [5] -- -- [3] SUB -- 650 Addressing Mode/ Instruction Length (Bytes) Condition Code Operation Rd8+#xx:8Rd8 IHNZVC Mnemonic ADD.B #xx:8,Rd B2 1 1 -- [3] -- [3] -- [4] -- [4] -- 2 1 3 1 [5] 1 1 ---- -- ---- -- ---- -- ---- -- ---- -- ---- -- ---- ---- ---- ---- ---- --* -- -- -- -- -- * 1 1 1 1 1 1 1 1 1 1 2 (2) Arithmetic Instructions No. of States*1 Advanced ADD ADDX ADDS INC DAA Addressing Mode/ Instruction Length (Bytes) Condition Code Operation Rd16-Rs16Rd16 ERd32-#xx:32ERd32 -- [3] IHNZVC No. of States*1 Advanced 1 3 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) Mnemonic SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBX #xx:8,Rd SUBX Rs,Rd SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DAS Rd MULXU.B Rs,Rd MULXU.W Rs,ERd W 2 B 2 B 2 L 2 L 2 W 2 W 2 B 2 L 2 Rd8-1Rd8 Rd16-1Rd16 Rd16-2Rd16 ERd32-1ERd32 ERd32-2ERd32 Rd8 decimal adjustRd8 L 2 ERd32-2ERd32 ERd32-4ERd32 L 2 ERd32-1ERd32 B 2 Rd8-Rs8-CRd8 B2 Rd8-#xx:8-CRd8 L 2 ERd32-ERs32ERd32 L6 W 2 SUB @@aa -- -- [4] -- -- -- [4] 1 [5] [5] 1 1 ------------ ------------ ------------ ---- ---- ---- ---- ---- --* -- -- -- -- -- *-- 1 1 1 1 1 1 1 1 1 SUBS DEC DAS MULXU Rd8xRs8Rd16 (unsigned multiplication) -- -- -- -- -- -- Rd16xRs16ERd32 (unsigned multiplication) SUBX 12 ------------ 20 MULXS MULXS.W Rs,ERd W MULXS.B Rs,Rd B 4 4 Rd8xRs8Rd16 (signed multiplication) Rd16xRs16ERd32 (signed multiplication) ---- ---- ---- ---- 13 21 651 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa -- NEG.L ERd EXTU.W Rd EXTU.L ERd L W 2 2 L 2 0-ERd32ERd32 0( -- ---- 0 652 Addressing Mode/ Instruction Length (Bytes) Condition Code Operation IHNZVC Mnemonic DIVXU.B Rs,Rd RdL: quotient) (unsigned division) DIVXU.W Rs,ERd W 2 ERd32/Rs16ERd32 (Ed: remainder, -- -- [6] [7] -- -- Rd: quotient) (unsigned division) DIVXS.B Rs,Rd B 4 Rd16/Rs8Rd16 (RdH: remainder, -- -- [8] [7] -- -- RdL: quotient) (signed division) DIVXS.W Rs,ERd Rd8-#xx:8 2 Rd8-Rs8 Rd16-#xx:16 2 Rd16-Rs16 ERd32-#xx:32 2 2 2 ERd32-ERs32 0-Rd8Rd8 0-Rd16Rd16 W 4 ERd32/Rs16ERd32 (Ed: remainder, -- -- [8] [7] -- -- Rd: quotient) (signed division) CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd NEG.B Rd NEG.W Rd W B L L6 W W4 B B2 -- -- 1 1 -- [3] 2 -- [3] 1 -- [4] 3 -- [4] -- -- 1 1 1 1 ---- 0 0-- 0-- 1 1 21 13 20 B 2 Rd16/Rs8Rd16 (RdH: remainder, -- -- [6] [7] -- -- 12 No. of States*1 Advanced DIVXU DIVXS CMP NEG EXTU Addressing Mode/ Instruction Length (Bytes) Condition Code Operation ( No. of States*1 Advanced Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa -- Mnemonic EXTS.W Rd W 2 ---- IHNZVC EXTS 0-- 1 EXTS.L ERd ( L 2 ---- 0-- 1 MAC TAS @ERd-0CCR set, (1) ---- 0-- 4 [2] CLRMAC LDMAC STMAC 653 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa -- NOT.L ERd L 2 ERd32ERd32 ---- 654 Addressing Mode/ Instruction Length (Bytes) Condition Code Operation Rd8#xx:8Rd8 2 Rd16#xx:16Rd16 2 Rd16Rs16Rd16 ERd32#xx:32ERd32 4 ERd32ERs32ERd32 Rd8#xx:8Rd8 2 Rd8Rs8Rd8 Rd16#xx:16Rd16 2 Rd16Rs16Rd16 ERd32#xx:32ERd32 4 ERd32ERs32ERd32 Rd8#xx:8Rd8 2 Rd8Rs8Rd8 Rd16#xx:16Rd16 2 Rd16Rs16Rd16 ERd32#xx:32ERd32 4 B W 2 2 ERd32ERs32ERd32 L Rd8Rd8 Rd16Rd16 Rd8Rs8Rd8 IHNZVC ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- Mnemonic AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd NOT.B Rd NOT.W Rd L6 W W4 B B2 L L6 W W4 B B2 L L6 W W4 B B2 1 1 2 1 3 2 1 1 2 1 3 2 1 1 2 1 3 2 1 1 1 (3) Logical Instructions No. of States*1 Advanced AND OR XOR NOT (4) Shift Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code Operation IHNZVC ---- ---- 0 C MSB LSB ---- ---- ---- ---- ---- ---- ---- MSB LSB C ---- ---- ---- ---- ---- 0 ---- C MSB LSB No. of States*1 Advanced 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) B B W W L L B B W W L L B B W W L L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Mnemonic SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHAL SHAR SHLL @@aa -- ---- ---- ---- 0 1 0 1 0 1 655 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa -- ROTXR.L #2,ERd L 2 -- ---- 0 -- -- -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- MSB -- LSB C C MSB LSB MSB LSB C ---- 0 ---- 0 ---- 0 ---- 0 ---- 0 ---- 0 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 656 Addressing Mode/ Instruction Length (Bytes) Condition Code Operation IHNZVC Mnemonic SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd L 2 W 2 W 2 B 2 B 2 L 2 L 2 W 2 W 2 B 2 B 2 L 2 L 2 W 2 W 2 B 2 B 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 No. of States*1 Advanced SHLR ROTXL ROTXR Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 0 0 1 1 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa -- Mnemonic ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd C MSB ROTL.L ERd ROTL.L #2,ERd ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd L 2 L 2 -- 1 W 2 W 2 -- MSB LSB C B 2 -- B 2 -- L 2 L 2 W 2 LSB W 2 B 2 B 2 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- Operation IHNZVC ROTL 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 ROTR 657 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa -- 658 Addressing Mode/ Instruction Length (Bytes) Condition Code Operation (#xx:3 of Rd8)1 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 B 6 (Rn8 of Rd8)1 (Rn8 of @ERd)1 (Rn8 of @aa:8)1 (Rn8 of @aa:16)1 (Rn8 of @aa:32)1 (#xx:3 of Rd8)0 (#xx:3 of @ERd)0 (#xx:3 of @aa:8)0 (#xx:3 of @aa:16)0 (#xx:3 of @aa:32)0 (Rn8 of Rd8)0 (Rn8 of @ERd)0 (Rn8 of @aa:8)0 B (Rn8 of @aa:16)0 (#xx:3 of @aa:32)1 (#xx:3 of @aa:16)1 (#xx:3 of @aa:8)1 (#xx:3 of @ERd)1 IHNZVC ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ Mnemonic BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 B B B B B B B B B B B B B B B B B 2 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 (5) Bit-Manipulation Instructions No. of States*1 Advanced BSET BCLR Addressing Mode/ Instruction Length (Bytes) Condition Code Operation (Rn8 of @aa:32)0 IHNZVC ------------ No. of States*1 Advanced 6 1 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa Mnemonic BCLR Rn,@aa:32 BNOT #xx:3,Rd BNOT #xx:3,@ERd [ (#xx:3 of @ERd)] BNOT #xx:3,@aa:8 [ (#xx:3 of @aa:8)] BNOT #xx:3,@aa:16 B 6 (#xx:3 of @aa:16) [ (#xx:3 of @aa:16)] BNOT #xx:3,@aa:32 B 8 (#xx:3 of @aa:32) [ (#xx:3 of @aa:32)] BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 B 6 B 4 B 4 B 2 (Rn8 of Rd8)[ (Rn8 of Rd8)] B 4 (#xx:3 of @aa:8) B 4 (#xx:3 of @ERd) B 2 B 8 BCLR @(d,PC) @@aa -- BNOT (#xx:3 of Rd8)[ (#xx:3 of Rd8)] -- -- -- -- -- -- ------------ 4 ------------ 4 ------------ 5 ------------ 6 ------------ (Rn8 of @ERd)[ (Rn8 of @ERd)] -- -- -- -- -- -- (Rn8 of @aa:8)[ (Rn8 of @aa:8)] -- -- -- -- -- -- (Rn8 of @aa:16) [ (Rn8 of @aa:16)] ------------ 1 4 4 5 BNOT Rn,@aa:32 B 8 (Rn8 of @aa:32) [ (Rn8 of @aa:32)] ------------ 6 BTST BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 B B B BTST #xx:3,Rd B 2 4 4 6 (#xx:3 of Rd8)Z (#xx:3 of @ERd)Z (#xx:3 of @aa:8)Z (#xx:3 of @aa:16)Z ------ ------ ------ ------ ---- ---- ---- ---- 1 3 3 4 659 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa -- BTST Rn,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 B B B 2 4 4 B B 6 8 B 4 B 4 B 2 B 8 B 6 B 4 B 4 B 2 (#xx:3 of Rd8)C B 8 (Rn8 of @aa:32)Z ------ (#xx:3 of @aa:32)C C(#xx:3 of Rd8) C(#xx:3 of @ERd) C(#xx:3 of @aa:8) ---------- 660 Addressing Mode/ Instruction Length (Bytes) Condition Code Operation (#xx:3 of @aa:32)Z (Rn8 of Rd8)Z 4 4 6 (Rn8 of @aa:16)Z (Rn8 of @aa:8)Z (Rn8 of @ERd)Z ------ ------ ------ ------ ------ IHNZVC ---- ---- ---- ---- ---- ---- ---------- ---------- ---------- ---------- ---------- (#xx:3 of Rd8)C (#xx:3 of @ERd)C (#xx:3 of @aa:8)C (#xx:3 of @aa:16)C ---------- ---------- ---------- ---------- Mnemonic BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 B B B B 2 B 8 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 ------------ ------------ ------------ 1 4 4 (#xx:3 of @ERd)C (#xx:3 of @aa:8)C (#xx:3 of @aa:16)C (#xx:3 of @aa:32)C No. of States*1 Advanced BTST BLD BILD BST Addressing Mode/ Instruction Length (Bytes) Condition Code Operation C(#xx:3 of @aa:16) C(#xx:3 of @aa:32) C(#xx:3 of Rd8) IHNZVC ------------ ------------ ------------ ------------ ------------ ------------ ------------ ---------- ---------- ---------- ---------- C(#xx:3 of @aa:32)C C[ (#xx:3 of Rd8)]C ---------- ---------- C[ (#xx:3 of @ERd)]C ---------- No. of States*1 Advanced 5 6 1 4 4 5 6 1 3 3 4 5 1 3 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) B B B B B B B B B B B B B B B B B B B 2 4 4 4 6 8 2 8 6 4 4 2 8 6 4 C(#xx:3 of @aa:8) C(#xx:3 of @aa:16) C(#xx:3 of @aa:32) C(#xx:3 of Rd8)C C(#xx:3 of @ERd)C C(#xx:3 of @aa:8)C C(#xx:3 of @aa:16)C 4 C(#xx:3 of @ERd) 2 8 6 Mnemonic BST #xx:3,@aa:16 BST #xx:3,@aa:32 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BST BIST BAND BIAND @@aa -- C[ (#xx:3 of @aa:8)]C C[ (#xx:3 of @aa:16)]C C[ (#xx:3 of @aa:32)]C C(#xx:3 of Rd8)C C(#xx:3 of @ERd)C ---------- ---------- ---------- ---------- ---------- 3 4 5 1 3 BOR 661 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa -- BIXOR #xx:3,@aa:32 B 8 C[ (#xx:3 of @aa:32)]C ---------- C(#xx:3 of @aa:8)C C(#xx:3 of @aa:16)C C(#xx:3 of @aa:32)C C[ (#xx:3 of Rd8)]C 4 4 6 8 2 4 4 6 8 2 4 4 6 C[ (#xx:3 of @ERd)]C C[ (#xx:3 of @aa:8)]C C[ (#xx:3 of @aa:16)]C C[ (#xx:3 of @aa:32)]C C(#xx:3 of Rd8)C C(#xx:3 of @ERd)C C(#xx:3 of @aa:8)C C(#xx:3 of @aa:16)C C(#xx:3 of @aa:32)C C[ (#xx:3 of Rd8)]C C[ (#xx:3 of @ERd)]C C[ (#xx:3 of @aa:8)]C C[ (#xx:3 of @aa:16)]C ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- 662 Addressing Mode/ Instruction Length (Bytes) Condition Code Operation IHNZVC Mnemonic BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 B B B B B B B B B B B B B B 2 B 8 B 6 B 4 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 No. of States*1 Advanced BOR BIOR BXOR BIXOR (6) Branch Instructions Addressing Mode/ Instruction Length (Bytes) Operation Condition Code Branching Condition No. of States*1 Advanced 2 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa -- Mnemonic BRA d:8(BT d:8) BRA d:16(BT d:16) BRN d:8(BF d:8) BRN d:16(BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8(BHS d:8) BCC d:16(BHS d:16) BCS d:8(BLO d:8) BCS d:16(BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 -- -- -- -- -- -- -- 4 2 4 2 4 2 4 V=0 Z=1 Z=0 -- 2 -- 4 C=1 -- 2 -- 4 C=0 -- 2 -- 4 CZ=1 -- 2 -- 4 CZ=0 -- 2 else next; -- 4 PCPC+d Never -- 2 if condition is true then Always IHNZVC ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ Bcc 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 663 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) Mnemonic BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 -- -- -- 4 2 4 -- 2 -- 4 -- 2 -- 4 NV=1 -- 2 -- 4 NV=0 -- 2 -- 4 N=1 -- 2 -- 4 N=0 -- 2 V=1 @@aa -- 664 Addressing Mode/ Instruction Length (Bytes) Operation Branching Condition Condition Code IHNZVC ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ Z(NV)=0 -- -- -- -- -- -- ------------ Z(NV)=1 -- -- -- -- -- -- ------------ No. of States*1 Advanced 2 3 2 3 2 3 2 3 2 3 2 3 2 3 Bcc Addressing Mode/ Instruction Length (Bytes) Condition Code Operation PCERn IHNZVC ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ No. of States*1 Advanced 2 3 5 4 5 4 5 6 5 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) -- -- -- -- -- -- -- -- -- 2 4 2 PC@-SP,PCERn PC@-SP,PCaa:24 PC@-SP,PC@aa:8 2 PC@SP+ 4 PC@-SP,PCPC+d:16 2 PC@-SP,PCPC+d:8 2 PC@aa:8 4 PCaa:24 2 Mnemonic JMP @ERn JMP @aa:24 JMP @@aa:8 BSR d:8 BSR d:16 JSR @ERn JSR @aa:24 JSR @@aa:8 RTS JMP BSR JSR RTS @@aa -- 665 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa -- PC@SP+ -- B2 B4 B B W W W W W W W W W W W W 10 4 4 6 6 8 8 10 6 6 4 4 2 2 Rs8CCR Rs8EXR @ERsCCR @ERsEXR @(d:16,ERs)CCR @(d:16,ERs)EXR @(d:32,ERs)CCR @(d:32,ERs)EXR @ERsCCR,ERs32+2ERs32 @ERsEXR,ERs32+2ERs32 @aa:16CCR @aa:16EXR @aa:32CCR @aa:32EXR #xx:8EXR #xx:8CCR Transition to power-down state ------------ 2 SLEEP SLEEP LDC LDC #xx:8,CCR LDC #xx:8,EXR ------------ LDC Rs,CCR LDC Rs,EXR ------------ LDC @ERs,CCR LDC @ERs,EXR ------------ LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR ------------ LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR ------------ 666 Addressing Mode/ Instruction Length (Bytes) Condition Code Operation PC@-SP,CCR@-SP, EXR@-SP, (7) System Control Instructions No. of States*1 Mnemonic TRAPA TRAPA #xx:2 RTE RTE LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR Addressing Mode/ Instruction Length (Bytes) Condition Code Operation CCRRd8 EXRRd8 IHNZVC ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ No. of States*1 Advanced 1 1 3 3 4 4 6 6 4 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) Mnemonic STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@-ERd STC EXR,@-ERd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 ANDC #xx:8,CCR ANDC #xx:8,EXR ORC #xx:8,CCR ORC #xx:8,EXR XORC #xx:8,CCR XORC #xx:8,EXR NOP B4 B2 B4 -- B2 B4 B2 W 8 W 8 W 6 W 6 W 4 W 4 W 10 W 10 W 6 EXR@(d:16,ERd) CCR@(d:32,ERd) EXR@(d:32,ERd) W 6 CCR@(d:16,ERd) W 4 EXR@ERd W 4 CCR@ERd B 2 B 2 STC @@aa -- ERd32-2ERd32,CCR@ERd -- -- -- -- -- -- ERd32-2ERd32,EXR@ERd CCR@aa:16 EXR@aa:16 CCR@aa:32 EXR@aa:32 CCR#xx:8CCR EXR#xx:8EXR CCR#xx:8CCR EXR#xx:8EXR CCR#xx:8CCR EXR#xx:8EXR 2 PCPC+2 ------------ ------------ ------------ ------------ ------------ 4 4 4 5 5 1 ------------ ANDC 2 1 ------------ ORC 2 1 ------------ ------------ 2 1 XORC NOP 667 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ Mnemonic Operation EEPMOV.B -- 4 if R4L0 Repeat @ER5@ER6 ER5+1ER5 ER6+1ER6 R4L-1R4L Until R4L=0 else next; 4 if R40 Repeat @ER5@ER6 ER5+1ER5 ER6+1ER6 R4-1R4 Until R4=0 else next; @aa @(d,PC) @@aa -- 668 Addressing Mode/ Instruction Length (Bytes) Condition Code IHNZVC ------------ Advanced 4+2n *3 EEPMOV.W -- ------------ 4+2n *3 (8) Block Transfer Instructions No. of States*1 EEPMOV Notes: *1 *2 *3 [1] [2] [3] [4] [5] [6] [7] [8] [9] The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. n is the initial value of R4L or R4. Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. Cannot be used in the LSI. Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. Retains its previous value when the result is zero; otherwise cleared to 0. Set to 1 when the divisor is negative; otherwise cleared to 0. Set to 1 when the divisor is zero; otherwise cleared to 0. Set to 1 when the quotient is negative; otherwise cleared to 0. One additional state is required for execution when EXR is valid. A.2 Table A-2 Instruction Codes Instruction Format Size 1st byte 8 rd 8 rd rd rd 0 erd IMM IMM 9 9 A A B B B rd E rd IMM rs rd rd rd 0 erd 0 IMM 4 1 IMM rd 0 7 0 0 disp 0 0 disp 1 0 disp disp abs abs 6 0 IMM 0 7 6 0 IMM 0 7 6 0 IMM 0 7 6 0 IMM 0 0 6 0 IMM 0 erd abs 1 3 6 6 0 ers 0 erd IMM IMM 6 rs 6 F rd 6 9 6 A 1 6 1 6 C E A A 0 8 1 8 rs IMM 9 0 erd 8 0 erd 0 0 erd 1 ers 0 erd 1 rs 1 rs 0 7 0 7 0 0 0 0 9 0 E 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4 5 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B W W L L L L L B B B B W W L L B B B B B B B -- -- -- -- Instruction Mnemonic ADD ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS ADDS #1,ERd ADDS #2,ERd Instruction Codes ADDS #4,ERd ADDX ADDX #xx:8,Rd Table A.2 shows the instruction codes. ADDX Rs,Rd AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 Bcc BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) 669 670 Instruction Format Size 1st byte 4 2 8 2 disp 3 disp 4 disp 5 disp 6 disp 7 disp 8 disp 9 disp A disp B disp C disp D disp E disp F 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 3 8 4 8 5 8 6 8 7 8 8 8 9 8 A 8 B 8 C 8 D 8 E 8 F 8 0 disp 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 disp 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Instruction Mnemonic 10th byte Bcc BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 Instruction Size 1st byte 7 2 rd 0 7 2 0 0 7 2 0 7 2 0 IMM 0 abs 0 IMM 2 abs 0 IMM 7 8 8 rd 0 6 2 rn 0 0 6 2 rn 6 0 2 rn 0 abs rn abs 2 6 8 8 rd 0 7 6 0 0 7 6 abs 1 IMM 0 7 6 1 IMM 0 6 abs 1 IMM 7 0 0 rd 0 7 7 0 0 7 abs 7 1 IMM 0 7 7 1 IMM 0 7 abs 1 IMM 7 0 0 rd 0 7 7 0 0 4 4 1 IMM 1 IMM abs abs 0 0 7 4 1 IMM 0 7 4 1 IMM 0 1 IMM 1 IMM 0 IMM D F A 1 3 rn 0 erd abs 1 3 1 IMM 0 erd abs 1 3 1 IMM 0 erd abs 1 3 1 IMM 0 erd abs 1 3 A 2 D F A A 6 C E A A 7 C E A A 4 C E A A abs 0 erd 7 7 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 0 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B B B B B B B B B B B Mnemonic Instruction Format 10th byte BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 671 672 Instruction Format Size 1st byte 6 7 rd 0 6 7 0 0 6 7 0 6 7 1 IMM 0 abs 1 IMM 7 abs 1 IMM 6 8 8 rd 0 7 5 0 0 7 5 0 7 5 1 IMM 0 abs 1 IMM 5 abs 1 IMM 7 0 0 rd 0 7 7 0 0 7 7 abs 0 IMM 0 7 7 0 IMM 0 7 abs 0 IMM 7 0 0 rd 0 7 1 0 0 7 abs 1 0 IMM 0 7 1 0 IMM 0 1 abs 0 IMM 7 8 8 rd 0 6 1 1 abs abs 6 8 8 rn rn 0 0 6 1 rn 0 6 1 rn 0 0 IMM 0 IMM 1 IMM 1 IMM D F A 1 3 1 IMM 0 erd abs 1 3 0 IMM 0 erd abs 1 3 0 IMM 0 erd abs 1 3 rn 0 erd abs 1 3 A 5 C E A A 7 C E A A 1 D F A A 1 D F A A abs 0 erd 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 1 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B B B B B B B B B B B Instruction Mnemonic 10th byte BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 Instruction Size 1st byte 7 4 rd 0 7 4 0 0 7 4 0 7 4 0 IMM 0 abs 0 IMM 4 abs 0 IMM 7 0 0 rd 0 7 0 0 0 7 0 0 7 0 0 IMM 0 abs 0 IMM 0 abs 0 IMM 7 8 8 rd 0 6 0 rn 0 0 6 0 abs rn 0 6 0 rn 0 rn abs 0 6 8 8 disp 0 0 rd 0 6 7 7 abs abs 0 IMM 6 8 8 rd 0 7 7 0 0 rn 0 erd C rd 0 6 3 rn 0 3 3 0 IMM 0 IMM abs abs 3 0 0 7 3 0 IMM 0 7 3 0 IMM 0 0 IMM 0 0 6 7 0 IMM 0 6 7 0 IMM 0 0 IMM 0 erd abs 1 3 0 IMM 0 erd abs 1 disp 0 IMM 0 IMM C E A 1 3 0 IMM 0 erd abs 1 3 rn 0 erd abs 1 3 A 0 D F A A 0 D F A A 5 C 7 D F A A 3 C E A A 3 abs 0 erd 7 7 6 6 7 7 7 6 6 6 7 7 6 6 5 5 6 7 7 6 6 7 7 7 6 6 6 7 0 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B -- -- B B B B B B B B B B B B Mnemonic Instruction Format 10th byte BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR BSR d:8 BSR d:16 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd 673 674 Instruction Format Size 1st byte 7 E 6 0 6 abs 6 3 rn 0 3 rn 0 0 rd 0 7 7 0 7 abs 7 5 5 0 0 IMM 0 0 abs 0 IMM 5 0 IMM 0 5 0 0 IMM abs 3 rn 0 A 1 3 0 IMM 0 erd abs 1 3 A 5 C E A A abs 6 6 7 7 7 6 6 Cannot be used in the LSI A rd C rs rd rd rd 0 erd IMM IMM 2 rs 2 1 ers 0 erd 0 rd rd rd rd rd 0 erd 0 erd 0 0 rd 0 erd C 4 5 5 9 9 8 8 F F 5 5 1 3 rs rs rd 0 erd 0 0 5 D 7 F D D rs rs 5 D 9 D A F F F A B B B B 1 1 1 3 B B 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B -- B B W W L L B B B W W L L B W B W -- -- Instruction Mnemonic 10th byte BTST BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CLRMAC CMP CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAA Rd DAS DAS Rd DEC DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV EEPMOV.B EEPMOV.W Instruction Size 1st byte 1 7 D rd 0 erd rd 0 erd rd rd rd 0 erd 0 erd 0 abs abs 0 ern 0 abs abs IMM 4 1 0 7 rs rs 0 6 9 9 F F 8 7 6 1 4 4 0 1 6 6 6 8 D D B B 6 6 6 7 1 0 1 0 1 0 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 4 0 0 0 0 0 0 0 0 0 0 0 0 abs abs 1 6 6 B B disp disp 2 2 0 0 disp disp 0 1 4 4 4 4 4 4 4 IMM F 5 7 0 5 D 7 F 0 ern 7 7 7 A B B B B 9 A B D E F 7 1 3 3 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 5 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W L W L B W W L L -- -- -- -- -- -- B B B B W W W W W W W W W W Mnemonic Instruction Format 10th byte EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR 675 676 Instruction Format Size 1st byte 0 1 4 0 6 B 2 2 7 7 7 0 ern+3 0 ern+2 0 ern+1 0 abs B D D D 6 6 6 6 1 0 0 0 4 1 2 3 1 1 1 1 0 0 0 0 Cannot be used in the LSI 0 abs 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W L L L L L -- B rd C rs rd rd rd 0 6 A 2 rd rd disp disp 0 ers 0 ers 0 ers 0 ers abs 0 rd rd rs rs 0 6 A A rs disp rs disp abs 2 1 erd 1 erd 0 erd 1 erd abs 8 rs rs rd rd rd rd 0 ers 0 6 B disp 0 ers 2 rd disp IMM A 0 rs 0 ers abs abs abs 8 E 8 C rd A A 8 E 8 C rs A A 9 D 9 F 8 B B B B B B B B B B B B B B B W W W W W 7 6 6 0 7 6 6 3 6 7 6 6 6 6 2 6 7 6 6 0 F IMM Instruction Mnemonic 10th byte LDC LDC @aa:32,CCR LDC @aa:32,EXR LDM LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs,MACH LDMAC ERs,MACL MAC MAC @ERn+,@ERm+ MOV MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa :16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd Instruction Size 1st byte 6 D rd rd rd rs rs 0 6 B A rs rs rs rs 0 erd IMM abs abs disp disp abs abs B 0 2 1 erd 1 erd 0 erd 1 erd 8 A 0 1 ers 0 erd 0 0 6 9 F 8 0 6 B D B 0 2 1 erd 0 ers 1 erd 0 ers 0 erd 0 6 B disp A 0 ers disp 0 erd B 9 F 8 D B B 0 erd 0 ers 0 erd abs abs 0 ers 2 0 ers 0 erd disp 0 erd disp 6 7 6 6 6 6 6 7 6 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ers 0 erd B 9 F 8 D B B A F 1 1 1 1 1 1 1 1 1 1 1 1 6 6 6 6 7 6 6 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 Cannot be used in the LSI 0 ers 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W W W W W W W W L L L L L L L L L L Mnemonic Instruction Format 10th byte MOV MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,Rd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16 ,ERd MOV.L @aa:32 ,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd)*1 L L L L B B B 1 C C rs rs 1 0 2 W B W 5 5 0 0 0 0 rd 0 erd 5 5 0 2 rs rs MOV.L ERs,@-ERd 1 erd 0 ers 8 A 0 ers 0 ers abs abs MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVFPE @aa:16,Rd MOVTPE MOVTPE Rs,@aa:16 MULXS MULXS.B Rs,Rd rd 0 erd MULXS.W Rs,ERd MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd 677 678 Instruction Format Size 1st byte 1 7 8 rd rd 0 erd 0 rd rd 0 erd IMM rs rd rd rd 0 erd 0 IMM 4 1 rn 0 rn 0 rd rd rd rd 0 erd 0 erd 6 D F 0 ern 6 D 7 0 ern 7 0 F 0 8 C 9 D B F 0 4 IMM 6 4 0 ers 0 erd IMM IMM 4 rs 4 F 9 B 0 0 1 3 7 7 0 7 7 7 rd 4 9 4 A 1 4 1 D 1 D 1 2 2 2 2 2 2 1 1 0 1 1 1 C 1 7 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B W L -- B W L B B W W L L B B W L W L B B W W L L Instruction Mnemonic 10th byte NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOP NOT NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC ORC #xx:8,CCR ORC #xx:8,EXR POP POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.B #2, Rd ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd ROTL.L #2, ERd Instruction Size 1st byte 1 3 8 rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 0 rd rd rd rd 0 erd 0 erd C 9 D B F 0 4 1 5 3 7 0 4 1 5 3 7 7 7 8 C 9 D B F 3 3 3 3 3 2 2 2 2 2 2 3 3 3 3 3 3 6 4 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B W W L L B B W W L L B B W W L L -- -- B B W W L L Mnemonic Instruction Format 10th byte ROTR ROTR.B Rd ROTR.B #2, Rd ROTR.W Rd ROTR.W #2, Rd ROTR.L ERd ROTR.L #2, ERd ROTXL ROTXL.B Rd ROTXL.B #2, Rd ROTXL.W Rd ROTXL.W #2, Rd ROTXL.L ERd ROTXL.L #2, ERd ROTXR ROTXR.B Rd ROTXR.B #2, Rd ROTXR.W Rd ROTXR.W #2, Rd ROTXR.L ERd ROTXR.L #2, ERd RTE RTE RTS RTS SHAL SHAL.B Rd SHAL.B #2, Rd SHAL.W Rd SHAL.W #2, Rd SHAL.L ERd SHAL.L #2, ERd 679 680 Instruction Format Size 1st byte 1 1 8 rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 rd rd 0 1 0 1 0 1 0 4 1 6 7 7 6 4 6 6 6 9 F F 8 8 D D 6 9 1 erd 1 erd 1 erd 1 erd 0 erd 0 erd 1 erd 1 erd 0 0 0 0 0 0 0 0 6 6 B B disp disp A A 0 0 disp disp C 9 D B F 0 4 1 5 3 7 0 4 1 5 3 7 8 0 1 4 4 4 4 4 4 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B W W L L B B W W L L B B W W L L -- B B W W W W Instruction Mnemonic 10th byte SHAR SHAR.B Rd SHAR.B #2, Rd SHAR.W Rd SHAR.W #2, Rd SHAR.L ERd SHAR.L #2, ERd SHLL SHLL.B Rd SHLL.B #2, Rd SHLL.W Rd SHLL.W #2, Rd SHLL.L ERd SHLL.L #2, ERd SHLR SHLR.B Rd SHLR.B #2, Rd SHLR.W Rd SHLR.W #2, Rd SHLR.L ERd SHLR.L #2, ERd SLEEP SLEEP STC STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) W STC.W EXR,@(d:16,ERd) W STC.W CCR,@(d:32,ERd) W STC.W EXR,@(d:32,ERd) W STC.W CCR,@-ERd STC.W EXR,@-ERd Instruction Size 1st byte 0 1 4 0 6 B 8 0 0 0 0 0 ern 0 ern 0 ern abs abs abs 8 A A F F F B B B D D D 6 6 6 6 6 6 1 0 1 0 0 0 4 4 4 1 2 3 1 1 1 1 1 1 abs 0 0 0 0 0 0 Cannot be used in the LSI 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W W W L L L L L B 8 rs rd rd rd 0 erd IMM IMM 3 rs 3 1 ers 0 erd 0 8 9 IMM rs rd 0 7 B 0 0 erd C E 00 IMM IMM rs rd rd rd 0 erd 0 6 5 IMM 0 ers 0 erd F IMM 5 rs 5 0 erd 0 erd 0 erd 9 9 A A B B B rd E 1 7 rd 5 9 5 A 1 W W L L L L L B B B -- B B W W L L 0 7 6 7 1 D 5 0 1 B 1 1 1 1 7 1 7 1 Mnemonic Instruction Format 10th byte STC STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM STM.L(ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP STM.L (ERn-ERn+3), @-SP STMAC STMAC MACH,ERd STMAC MACL,ERd SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd SUBX SUBX #xx:8,Rd SUBX Rs,Rd TAS TAS @ERd *2 TRAPA TRAPA #x:2 XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd 681 682 Instruction Format Size 1st byte 0 0 1 4 1 0 5 IMM 5 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B Instruction Mnemonic 10th byte XORC XORC #xx:8,CCR XORC #xx:8,EXR Notes: *1 Bit 7 of the 4th byte of the MOV.L ERs, @(d:32,ERd) instruction can be either 1 or 0. *2 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Legend IMM: abs: disp: rs, rd, rn: ers, erd, ern, erm: Immediate data (2, 3, 8, 16, or 32 bits) Absolute address (8, 16, 24, or 32 bits) Displacement (8, 16, or 32 bits) Register field (4 bits specifying an 8-bit or 16-bit register. The symbols rs, rd, and rn correspond to operand symbols Rs, Rd,and Rn.) Register field (3 bits specifying an address register or 32-bit register. The symbols ers, erd, ern, and erm correspond to operand symbols ERs, ERd, ERn, and ERm.) The register fields specify general registers as follows. 16-Bit Register Register Field 0000 0001 * * * 0111 1000 1001 * * * 1111 R0 R1 * * * R7 E0 E1 * * * E7 0000 0001 * * * 0111 1000 1001 * * * 1111 General Register Register Field General Register R0H R1H * * * R7H R0L R1L * * * R7L 8-Bit Register Address Register 32-Bit Register Register Field General Register 000 001 * * * 111 ER0 ER1 * * * ER7 A.3 Table A-3 Operation Code Map (1) Instruction when most significant bit of BH is 0. 2nd byte BH BL Instruction when most significant bit of BH is 1. Instruction code 1st byte AH AL AL 2 ORC XORC XOR MOV.B AND Table A.3(2) SUB ANDC OR LDC ADD MOV CMP 3 4 5 6 8 7 9 A B C AH 0 1 D E ADDX SUBX F 0 NOP Operation Code Map 1 Table A.3(2) LDC Table STC * * A.3(2) STMAC LDMAC Table Table Table A.3(2) A.3(2) A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3 shows the operation code map. 2 3 BLS DIVXU MOV MOV Table A.3(2) BTST RTS BSR RTE TRAPA Table A.3(2) JMP BCC BCS BNE BEQ BVC BVS BPL BMI BGE BSR MOV EEPMOV Table A.3(3) BLT BGT JSR BLE 4 BRA BRN BHI 5 MULXU DIVXU MULXU 6 BSET BNOT BCLR 7 ADD ADDX CMP SUBX OR XOR AND MOV BST OR AND XOR BIST BXOR BAND BOR BLD BIXOR BIAND BIOR BILD Table A.3(2) Table A.3(2) 8 9 A B C D E F Note: * Cannot be used in the LSI. 683 684 2nd byte BH BL 2 3 STM STC LDC MAC* SLEEP CLRMAC * 4 5 9 A 6 7 8 B C Table A.3(3) ADD INC ADDS MOV SHLL SHLR ROTXL ROTXR NOT EXTU EXTU ROTXR ROTXL ROTL ROTR NEG NEG SUB DEC DEC SUBS CMP BHI BLS BCC Table * A.3(4) MOVFPE SUB SUB OR OR XOR XOR AND AND MOV CMP CMP BCS BNE BEQ BVC MOV BVS BPL MOV BMI BGE MOVTPE* BLT BGT BLE DEC DEC SHLR SHAR SHLL SHAL SHAL SHAR ROTL ROTR EXTS SHAL SHAR ROTL ROTR EXTS INC INC INC D Table A.3(3) E TAS F Table A.3(3) Table A-3 Operation Code Map (2) Instruction code 1st byte AH AL BH AH AL 0 1 01 MOV LDM 0A INC 0B ADDS 0F DAA 10 SHLL 11 SHLR 12 ROTXL 13 ROTXR 17 NOT 1A DEC 1B SUBS 1F DAS 58 BRA BRN 6A MOV Table A.3(4) 79 MOV ADD 7A MOV ADD Note: * Cannot be used in the LSI. Table A-3 Operation Code Map (3) 2nd byte BH BL CH CL DH DL 3rd byte 4th byte Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. Instruction code 1st byte AH AL CL 2 3 4 5 6 7 8 9 A MULXS DIVXS OR BTST BTST BCLR BCLR BTST BTST BCLR BCLR XOR AND AH AL BH BL CH 0 1 B C D E F 01C05 MULXS 01D05 DIVXS 01F06 7Cr06 *1 7Cr07 *1 7Dr06 *1 BSET BNOT BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST 7Dr07 *1 BSET BNOT 7Eaa6 *2 7Eaa7 *2 7Faa6 *2 BSET BNOT BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST 7Faa7 *2 BSET BNOT Notes: *1 r is the register specification field. *2 aa is the absolute address specification. 685 686 2nd byte BH BL CH CL DH DL EH EL FH FL Instruction when most significant bit of FH is 0. Instruction when most significant bit of FH is 1. 2 4 5 6 7 8 9 A B BTST BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 3 C D E F 3rd byte 4th byte 5th byte 6th byte BCLR 2nd byte BH BL CH CL DH DL EH 3rd byte 4th byte 5th byte EL 6th byte FH FL 7th byte GH GL 8th byte HH HL Instruction when most significant bit of HH is 0. Instruction when most significant bit of HH is 1. 2 4 5 BTST 3 6 7 8 9 A B C D E F BCLR BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST Table A-3 Operation Code Map (4) Instruction code 1st byte AH AL EL AHALBHBLCHCLDHDLEH 0 1 6A10aaaa6* 6A10aaaa7* 6A18aaaa6* BSET BNOT 6A18aaaa7* Instruction code 1st byte AH AL GL AHALBHBL ... FHFLGH 0 1 6A30aaaaaaaa6* 6A30aaaaaaaa7* 6A38aaaaaaaa6* BSET BNOT 6A38aaaaaaaa7* Note: * aa is the absolute address specification. A.4 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8S/2000 CPU. Table A.5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A.4 indicates the number of states required for each cycle, depending on its size. The number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I x SI + J x SJ + K x SK + L xS L + M x SM + N x SN Examples: Advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. BSET #0, @FFFFB3:8 From table A.5: I = L = 2, J = K = M = N = 0 From table A.4: S I = 4, SL = 2 Number of states required for execution = 2 x 4 + 2 x 2 = 12 2. JSR @@30 From table A.5: I = J = K = 2, L = M = N = 0 From table A.4: S I = SJ = SK = 4 Number of states required for execution = 2 x 4 + 2 x 4 + 2 x 4 = 24 687 Table A.4 Number of States per Cycle Access Conditions On-Chip Supporting Module External Device 8-Bit Bus 16-Bit Bus Cycle Instruction fetch SI On-Chip 8-Bit Memory Bus 1 4 16-Bit Bus 2 2-State 3-State 2-State 3-State Access Access Access Access 4 6 + 2m 2 3+m Branch address read SJ Stack operation Byte data access Word data access Internal operation SK SL SM SN 1 2 4 1 1 2 4 1 3+m 6 + 2m 1 1 1 m: Number of wait states inserted into external device access 688 Table A.5 Number of Cycles in Instruction Execution Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access M Internal Operation N Instruction ADD Mnemonic ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd I 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 2 1 2 2 3 4 2 2 2 2 2 2 2 2 2 2 2 J K L ADDS ADDX ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 1 1 1 1 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 689 Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction Bcc Mnemonic BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 I 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3 4 1 2 2 3 4 2 2 2 2 2 2 2 2 J K L Word Data Access M Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 690 Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction BIAND Mnemonic BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8 BIOR #xx:8,@aa:16 BIOR #xx:8,@aa:32 BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 1 1 1 1 1 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 J K L Word Data Access M Internal Operation N 691 Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction BNOT Mnemonic BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR BSR d:8 BSR d:16 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 2 2 1 2 2 3 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 J K L Word Data Access M Internal Operation N 1 692 Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction BTST Mnemonic BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CMP CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAS DEC DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 Cannot be used in the LSI 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 J K L Word Data Access M Internal Operation N 11 19 11 19 693 Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction EEPMOV Mnemonic EEPMOV.B EEPMOV.W EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR I 2 2 1 1 1 1 1 1 1 2 2 2 2 2 2 1 2 1 1 2 2 3 3 5 5 2 2 3 3 4 4 2 2 2 2 2 J K L 2n+2* 2 Word Data Access M Internal Operation N 2n+2*2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 694 Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction LDM Mnemonic LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs,MACH LDMAC ERs,MACL MAC MOV MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd Cannot be used in the LSI 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I 2 2 2 J K 4 6 8 L Word Data Access M Internal Operation N 1 1 1 Cannot be used in the LSI 1 1 1 1 1 1 1 1 1 1 695 Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction MOV Mnemonic MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVTPE MULXS MOVFPE @:aa:16,Rd MOVTPE Rs,@:aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOP NOT.B Rd NOT.W Rd NOT.L ERd 2 2 1 1 1 1 1 1 1 1 1 I 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 Can not be used in the LSI J K L Word Data Access M 1 1 1 1 1 Internal Operation N 1 2 2 2 2 2 2 2 2 2 2 2 2 1 1 11 19 11 19 696 Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction OR Mnemonic OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC ORC #xx:8,CCR ORC #xx:8,EXR POP POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd I 1 1 2 1 3 2 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 J K L Word Data Access M Internal Operation N 1 2 1 2 1 1 1 1 697 Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction ROTXR Mnemonic ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd RTE RTS SHAL RTE RTS SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP SLEEP I 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2/3*1 2 J K L Word Data Access M Internal Operation N 1 1 1 698 Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction STC Mnemonic STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd I 1 1 2 2 J K L Word Data Access M Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 4 6 8 1 1 1 1 1 STC.W CCR,@(d:16,ERd) 3 STC.W EXR,@(d:16,ERd) 3 STC.W CCR,@(d:32,ERd) 5 STC.W EXR,@(d:32,ERd) 5 STC.W CCR,@-ERd STC.W EXR,@-ERd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM STM.L (ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP STM.L (ERn-ERn+3), @-SP STMAC STMAC MACH,ERd STMAC MACL,ERd SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBX SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS TRAPA TAS @ERd *3 TRAPA #x:2 1 2 1 3 1 1 1 1 2 2 2 2/3* 1 2 2 3 3 4 4 2 2 2 Cannot be used in the LSI 2 2 699 Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction XOR Mnemonic XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC XORC #xx:8,CCR XORC #xx:8,EXR I 1 1 2 1 3 2 1 2 J K L Word Data Access M Internal Operation N Notes: *1 2 when EXR is invalid, 3 when EXR is valid. *2 When n bytes of data are transferred. *3 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 700 A.5 Bus States During Instruction Execution Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See table A.4 for the number of states per cycle. How to Read the Table: Order of execution Instruction JMP@aa:24 1 R:W 2nd 2 3 4 5 6 7 8 Internal operation R:W EA 1 state End of instruction Read effective address (word-size read) No read or write Read 2nd word of current instruction (word-size read) Legend R:B R:W W:B W:W :M 2nd 3rd 4th 5th NEXT EA VEC Byte-size read Word-size read Byte-size write Word-size write Transfer of the bus is not performed immediately after this cycle Address of 2nd word (3rd and 4th bytes) Address of 3rd word (5th and 6th bytes) Address of 4th word (7th and 8th bytes) Address of 5th word (9th and 10th bytes) Address of next instruction Effective address Vector address 701 Figure A.1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. o Address bus RD HWR, LWR High level R:W 2nd Fetching 3rd byte of instruction Fetching 4th byte of instruction Internal operation R:W EA Fetching 1nd byte of instruction at jump address Fetching 2nd byte of instruction at jump address Figure A.1 Address Bus, RD, HWR, and LWR Timing (8-Bit Bus, Three-State Access, No Wait States) 702 Table A.6 Instruction Execution Cycles 2 3 4 5 6 7 8 9 R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W NEXT Instruction ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 1 R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT 703 704 3 R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA 4 5 6 7 8 9 2 R:W EA Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state R:B:M EA R:B:M EA R:W 3rd R:W:M NEXT W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA Instruction BLE d:8 BRA d:16 (BT d:16) 1 R:W NEXT R:W 2nd BRN d:16 (BF d:16) R:W 2nd BHI d:16 R:W 2nd BLS d:16 R:W 2nd BCC d:16 (BHS d:16) R:W 2nd BCS d:16 (BLO d:16) R:W 2nd BNE d:16 R:W 2nd BEQ d:16 R:W 2nd BVC d:16 R:W 2nd BVS d:16 R:W 2nd BPL d:16 R:W 2nd BMI d:16 R:W 2nd BGE d:16 R:W 2nd BLT d:16 R:W 2nd BGT d:16 R:W 2nd BLE d:16 R:W 2nd BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 R:W NEXT R:W 2nd R:W 2nd R:W 2nd 2 R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA 3 R:W 4th 4 R:B:M EA 5 6 R:W:M NEXT W:B EA 7 8 9 R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT Instruction BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT 705 706 2 R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:W EA Internal operation, 1 state R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:W:M stack (H) R:W EA R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA W:W stack (L) W:W:M stack (H) W:W stack (L) R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA 3 R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th 4 5 6 W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA 7 8 9 W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA Instruction BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR d:8 BSR d:16 1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd 3 4 5 R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT Instruction BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC 1 2 R:W 2nd R:B EA R:W 2nd R:W 3rd R:W 2nd R:W 3rd R:W NEXT R:W 2nd R:B EA R:W 2nd R:B EA R:W 2nd R:W 3rd R:W 2nd R:W 3rd R:W NEXT R:W 2nd R:B EA R:W 2nd R:B EA R:W 2nd R:W 3rd R:W 2nd R:W 3rd Cannot be used in the LSI 6 7 8 9 R:W NEXT R:W 3rd R:W NEXT CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd R:W NEXT Internal operation, 11 states R:W NEXT Internal operation, 19 states Internal operation, 11 states Internal operation, 19 states R:B EAd*1 R:B EAs*2 W:B EAd*2 R:B EAs*1 R:B EAd*1 R:B EAs*2 W:B EAd*2 R:B EAs*1 Repeated n times*2 R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT 707 708 2 3 4 5 6 7 8 9 R:W EA Internal operation, R:W EA 1 state R:W:M aa:8 R:W aa:8 Internal operation, R:W EA 1 state R:W EA W:W:M stack (H) W:W stack (L) Internal operation, R:W EA W:W:M stack (H) W:W stack (L) 1 state R:W:M aa:8 R:W aa:8 W:W:M stack (H) W:W stack (L) R:W EA R:W NEXT R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W NEXT R:W EA R:W EA R:W 5th R:W 5th R:W EA R:W NEXT R:W NEXT R:W EA R:W EA R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W:M stack (H)*3 R:W stack (L)*3 R:W:M stack (H)*3 R:W stack (L)*3 R:W:M stack (H)*3 R:W stack (L)*3 R:W EA R:W EA Instruction INC.W #1/2,Rd INC.L #1/2,ERd JMP @ERn JMP @aa:24 1 R:W NEXT R:W NEXT R:W NEXT R:W 2nd JMP @@aa:8 R:W NEXT JSR @ERn JSR @aa:24 R:W NEXT R:W 2nd JSR @@aa:8 LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+,(ERn-ERn+2) LDM.L @SP+,(ERn-ERn+3) LDMAC ERs,MACH R:W EA R:W EA R:W NEXT R:W NEXT R:W 4th R:W 4th Internal operation, 1 state R:W 2nd R:W NEXT Internal operation, 1 state R:W 2nd R:W 3rd R:W NEXT R:W 2nd R:W 3rd R:W NEXT R:W 2nd R:W 3rd R:W 4th R:W 2nd R:W 3rd R:W 4th R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W NEXT Internal operation, 1 state R:W 2nd R:W NEXT Internal operation, 1 state Cannot be used in the LSI 1 2 Cannot be used in the LSI 3 4 5 6 7 8 9 Instruction LDMAC ERs,MACL MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd R:B EA R:W 4th R:B EA R:W NEXT R:B EA R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:B EA R:W NEXT R:B EA MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd W:B EA R:W 4th W:B EA R:W NEXT W:B EA R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:B EA R:W NEXT R:W 3rd Internal operation, 1 state R:B EA R:W NEXT R:W 3rd W:B EA R:W NEXT R:W 3rd Internal operation, 1 state W:B EA R:W NEXT R:W 3rd R:W NEXT W:B EA R:W NEXT W:B EA MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+, Rd R:W EA R:W 4th R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:B EA MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd W:W EA R:E 4th W:W EA W:W EA R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT W:W EA MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 R:W 2nd R:W 2nd R:W EA R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd W:W EA R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd W:W EA 709 710 2 R:W 3rd 3 R:W NEXT 4 5 6 7 8 9 R:W:M NEXT R:W:M 3rd R:W:M 3rd R:W:M NEXT R:W EA+2 R:W NEXT R:W EA+2 R:W:M EA R:W EA+2 R:W EA+2 R:W:M EA R:W EA+2 R:W EA+2 R:W:M EA R:W 5th R:W:M EA R:W:M EA R:W NEXT W:W EA+2 W:W:M EA R:W 5th W:W:M EA W:W EA+2 R:W NEXT W:W EA+2 W:W:M EA W:W EA+2 W:W:M EA W:W EA+2 W:W:M EA R:W NEXT W:W EA+2 R:W NEXT Internal operation, 11 states R:W NEXT Internal operation, 19 states Internal operation, 11 states Internal operation, 19 states R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W NEXT Instruction MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR R:W:M EA R:W NEXT R:W:M 4th Internal operation, 1 state R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W 4th R:W 2nd R:W:M NEXT W:W:M EA R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W:M 4th R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W 4th Cannot be used in the LSI R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd Instruction POP.W Rn R:W EA+2 1 R:W NEXT 5 6 7 8 9 POP.L ERn R:W 2nd PUSH.W Rn W:W EA+2 R:W NEXT PUSH.L ERn R:W 2nd 2 3 4 Internal operation, R:W EA 1 state R:W:M NEXT Internal operation, R:W:M EA 1 state Internal operation, W:W EA 1 state R:W:M NEXT Internal operation, W:W:M EA 1 state ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd RTE R:W stack (EXR) R:W stack (H) R:W:M stack (H) R:W stack (L) R:W stack (L) Internal operation, R:W*4 1 state Internal operation, R:W*4 1 state R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT RTS R:W NEXT SHAL.B Rd R:W NEXT 711 712 2 3 4 5 6 7 8 9 Internal operation:M 1 R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W NEXT W:W EA W:W EA R:W NEXT R:W NEXT R:W 4th R:W 4th Internal operation, 1 state W:W EA W:W EA R:W 5th R:W 5th W:W EA Instruction SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@-ERd R:W NEXT R:W NEXT W:W EA W:W EA Instruction STC EXR,@-ERd W:W EA W:W EA R:W NEXT W:W EA R:W NEXT W:W EA W:W:M stack (H)*3 W:W stack (L)*3 W:W:M stack (H)*3 W:W stack (L)*3 W:W:M stack (H)*3 W:W stack (L)*3 1 R:W 2nd 2 R:W NEXT 4 W:W EA 5 6 7 8 9 STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 STM.L(ERn-ERn+1),@-SP STM.L(ERn-ERn+2),@-SP STM.L(ERn-ERn+3),@-SP 3 Internal operation, 1 state R:W 2nd R:W 3rd R:W NEXT R:W 2nd R:W 3rd R:W NEXT R:W 2nd R:W 3rd R:W 4th R:W 2nd R:W 3rd R:W 4th R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W:M NEXT Internal operation, 1 state Cannot be used in the LSI R:W NEXT R:W 3rd R:W NEXT STMAC MACH,ERd STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd *5 TRAPA #x:2 R:W NEXT R:B:M EA Internal operation, W:W stack (L) 1 state W:B EA W:W stack (H) W:W stack (EXR) R:W:M VEC R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W VEC+2 Internal operation, R:W*8 1 state XOR.B #xx8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC #xx:8,CCR XORC #xx:8,EXR Reset exception handling R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 3rd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W:M VEC R:W VEC+2 Internal operation, R:W*6 1 state 713 714 1 Internal operation, W:W stack (L) 1 state W:W stack (H) W:W stack (EXR) R:W:M VEC R:W VEC+2 Internal operation, R:W*8 1 state 2 3 4 5 6 7 8 9 Instruction Interrupt exception handling R:W*7 Notes: *1 *2 *3 *4 *5 *6 *7 *8 EAs is the contents of ER5. EAd is the contents of ER6. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these bus cycles are not executed. Repeated two times to save or restore two registers, three times for three registers, or four times for four registers. Start address after return. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Start address of the program. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read operation is replaced by an internal operation. Start address of the interrupt-handling routine. A.6 Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below. m= 31 for longword operands 15 for word operands 7 for byte operands Si Di Ri Dn -- The i-th bit of the source operand The i-th bit of the destination operand The i-th bit of the result The specified bit in the destination operand Not affected Modified according to the result of the instruction (see definition) 0 1 * Z' C' Always cleared to 0 Always set to 1 Undetermined (no guaranteed value) Z flag before instruction execution C flag before instruction execution 715 Table A.7 Instruction ADD Condition Code Modification H N Z V C Definition H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm ADDS ADDX ---------- H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Z' * Rm * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm AND -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 ANDC Stores the corresponding bits of the result. No flags change when the operand is EXR. BAND Bcc BCLR BIAND BILD BIOR BIST BIXOR BLD BNOT BOR BSET BSR BST BTST BXOR CLRMAC -------- ---------- ---------- -------- -------- -------- ---------- -------- -------- ---------- -------- ---------- ---------- ---------- ---- ---- C = C' * Dn C = C' * Dn C = Dn C = C' + Dn C = C' * Dn + C' * Dn C = Dn C = C' + Dn Z = Dn C = C' * Dn + C' * Dn Cannot be used in the LSI -------- 716 Instruction CMP H N Z V C Definition H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm DAA * * N = Rm Z = Rm * Rm-1 * ...... * R0 C: decimal arithmetic carry DAS * * N = Rm Z = Rm * Rm-1 * ...... * R0 C: decimal arithmetic borrow DEC -- -- N = Rm Z = Rm * Rm-1 * ...... * R0 V = Dm * Rm DIVXS -- ---- N = Sm * Dm + Sm * Dm Z = Sm * Sm-1 * ...... * S0 N = Sm Z = Sm * Sm-1 * ...... * S0 DIVXU -- ---- EEPMOV EXTS ---------- -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 Z = Rm * Rm-1 * ...... * R0 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Dm * Rm EXTU INC --0 -- 0 -- -- JMP JSR LDC ---------- ---------- Stores the corresponding bits of the result. No flags change when the operand is EXR. LDM LDMAC MAC ---------- Cannnot be used in the LSI 717 Instruction MOV H -- N Z V 0 C -- Definition N = Rm Z = Rm * Rm-1 * ...... * R0 MOVFPE MOVTPE MULXS -- ---- Can not be used in the LSI N = R2m Z = R2m * R2m-1 * ...... * R0 MULXU NEG ---------- H = Dm-4 + Rm-4 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Dm * Rm C = Dm + Rm NOP NOT ---------- -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 OR -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 ORC Stores the corresponding bits of the result. No flags change when the operand is EXR. POP -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 PUSH -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 ROTL -- 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) ROTR -- 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) 718 Instruction ROTXL H -- N Z V 0 C Definition N = Rm Z = Rm * Rm-1 * ...... * R0 C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) ROTXR -- 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) RTE RTS SHAL ---------- -- Stores the corresponding bits of the result. N = Rm Z = Rm * Rm-1 * ...... * R0 V = Dm * Dm-1 + Dm * Dm-1 (1-bit shift) V = Dm * Dm-1 * Dm-2 * Dm * Dm-1 * Dm-2 (2-bit shift) C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) SHAR -- 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) SHLL -- 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) SHLR --0 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) SLEEP STC STM STMAC ---------- ---------- ---------- Cannot be used in the LSI 719 Instruction SUB H N Z V C Definition H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm SUBS SUBX ---------- H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Z' * Rm * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm TAS* -- 0 -- N = Dm Z = Dm * Dm-1 * ...... * D0 TRAPA XOR ---------- -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 XORC Stores the corresponding bits of the result. No flags change when the operand is EXR. Note: * Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 720 Appendix B Internal I/O Register B.1 Addresses Module Name DTC Data Bus Width 16/32* bits Register Address Name H'EBC0 MRA to SAR H'EFBF Bit 7 SM1 Bit 6 SM0 Bit 5 DM1 Bit 4 DM0 Bit 3 MD1 Bit 2 MD0 Bit 1 DTS Bit 0 Sz MRB DAR CHNE DISEL -- -- -- -- -- -- CRA CRB H'FDB4 SCRX H'FDD0 SMR3 H'FDD1 BRR3 H'FDD2 SCR3 H'FDD3 TDR3 H'FDD4 SSR3 H'FDD5 RDR3 H'FDD6 SCMR3 H'FDE4 SBYCR H'FDE5 SYSCR H'FDE6 SCKCR H'FDE7 MDCR -- C/A -- CHR -- PE -- O/E FLSHE STOP -- MP -- CKS1 -- CKS0 FLASH SCI3 8 bits 8 bits TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER PER TEND MPB MPBT -- SSBY -- PSTOP -- -- STS2 -- -- -- -- STS1 INTM1 -- -- -- STS0 INTM0 -- -- SDIR OPE NMIEG -- -- -- -- -- SCK2 MDS2 -- -- -- SCK1 MDS1 -- -- RAME SCK0 MSD0 Power-down state MCU Clock pulse generator MCU 8 bits 8 bits 8 bits 8 bits 8 bits H'FDE8 MSTPCRA MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Power-down state H'FDE9 MSTPCRB MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 H'FDEA MSTPCRC MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 H'FDEB PFCR H'FDEC LPWRCR H'FE00 BARA H'FE01 H'FE02 H'FE03 -- DTON -- BAA23 BAA15 BAA7 -- LSON -- BAA22 BAA14 BAA6 BUZZE NESEL -- BAA21 BAA13 BAA5 -- AE3 AE2 -- -- BAA18 BAA10 BAA2 AE1 STC1 -- BAA17 BAA9 BAA1 AE0 STC0 -- BAA16 BAA8 BAA0 Bus controller 8 bits Power-down state PBC 8 bits 16 bits SUBSTP RFCUT -- BAA20 BAA12 BAA4 -- BAA19 BAA11 BAA3 721 Register Address Name H'FE04 BARB H'FE05 H'FE06 H'FE07 H'FE08 BCRA H'FE09 BCRB H'FE12 ISCRH H'FE13 ISCRL H'FE14 IER H'FE15 ISR H'FE16 DTCER to H'FE1A, H'FE1E H'FE1F DTVECR H'FE30 P1DDR H'FE32 P3DDR H'FE36 P7DDR H'FE39 PADDR H'FE3A PBDDR H'FE3B PCDDR H'FE3C PDDDR H'FE3D PEDDR H'FE3E PFDDR H'FE3F PGDDR H'FE40 PAPCR H'FE41 PBPCR H'FE42 PCPCR H'FE43 PDPCR H'FE44 PEPCR H'FE46 P3ODR H'FE47 PAODR H'FEB0 TSTR H'FEB1 TSYR H'FEC0 IPRA H'FEC1 IPRB H'FEC2 IPRC H'FEC3 IPRD Bit 7 -- BAB23 BAB15 BAB7 CMFA CMFB Bit 6 -- BAB22 BAB14 BAB6 CDA CDB Bit 5 -- BAB21 BAB13 BAB5 Bit 4 -- BAB20 BAB12 BAB4 Bit 3 -- BAB19 BAB11 BAB3 Bit 2 -- BAB18 BAB10 BAB2 Bit 1 -- BAB17 BAB9 BAB1 Bit 0 -- BAB16 BAB8 BAB0 Module Name PBC Data Bus Width 16 bits BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 BIEA BAMRB2 BAMRB1 BAMRB0 CSELB1 CSELB0 BIEB 8 bits IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Interrupt IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA controller IRQ7E IRQ7F DTCE7 IRQ6E IRQ6F DTCE6 IRQ5E IRQ5F DTCE5 IRQ4E IRQ4F DTCE4 IRQ3E IRQ3F DTCE3 IRQ2E IRQ2F DTCE2 IRQ1E IRQ1F DTCE1 IRQ0E IRQ0F DTCE0 DTC 8 bits 8 bits SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 -- -- P16DDR -- P14DDR P13DDR P12DDR P11DDR P10DDR Port 8 bits P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR P75DDR P74DDR -- -- -- -- -- -- P77DDR -- -- -- PA3DDR PA2DDR PA1DDR PA0DDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR -- -- -- -- -- -- PG4DDR PG3DDR PG2DDR PG1DDR -- -- PA3PCR PA2PCR PA1PCR PA0PCR PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR -- -- -- -- -- -- -- -- -- -- -- -- IPR6 IPR6 IPR6 IPR6 P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR -- -- -- IPR5 IPR5 IPR5 IPR5 -- -- -- IPR4 IPR4 IPR4 IPR4 PA3ODR PA2ODR PA1ODR PA0ODR -- -- -- -- -- -- CST2 SYNC2 IPR2 IPR2 IPR2 -- CST1 SYNC1 IPR1 IPR1 IPR1 -- CST0 SYNC0 IPR0 IPR0 IPR0 -- Interrupt controller 8 bits TPU 8 bits 722 Register Address Name H'FEC4 IPRE H'FEC5 IPRF H'FEC6 IPRG H'FEC8 IPRI H'FEC9 IPRJ H'FECA IPRK H'FECE IPRO H'FED0 ABWCR H'FED1 ASTCR H'FED2 WCRH H'FED3 WCRL H'FED4 BCRH H'FED5 BCRL H'FEDB RAMER H'FF00 H'FF02 H'FF06 H'FF09 P1DR P3DR P7DR PADR Bit 7 -- -- -- -- -- -- -- ABW7 AST7 W71 W31 ICIS1 BRLE -- -- -- P77DR -- PB7DR PC7DR PD7DR PE7DR PF7DR -- CCLR2 -- IOB3 IOD3 TTGE -- Bit 6 IPR6 IPR6 IPR6 IPR6 -- IPR6 IPR6 ABW6 AST6 W70 W30 ICIS0 -- -- P16DR P36DR -- -- PB6DR PC6DR PD6DR PE6DR PF6DR -- CCLR1 -- IOB2 IOD2 -- -- Bit 5 IPR5 IPR5 IPR5 IPR5 -- IPR5 IPR5 ABW5 AST5 W61 W21 Bit 4 IPR4 IPR4 IPR4 IPR4 -- IPR4 IPR4 ABW4 AST4 W60 W20 Bit 3 -- -- -- -- -- -- -- ABW3 AST3 W51 W11 Bit 2 IPR2 IPR2 -- IPR2 IPR2 -- -- ABW2 AST2 W50 W10 Bit 1 IPR1 IPR1 -- IPR1 IPR1 -- -- ABW1 AST1 W41 W01 -- -- RAM1 P11DR P31DR -- PA1DR PB1DR PC1DR PD1DR PE1DR PF1DR PG1DR TPSC1 MD1 IOA1 IOC1 TGIEB TGFB Bit 0 IPR0 IPR0 -- IPR0 IPR0 -- -- ABW0 AST0 W40 W00 -- WAITE RAM0 P10DR P30DR -- PA0DR PB0DR PC0DR PD0DR PE0DR PF0DR -- TPSC0 MD0 IOA0 IOC0 TGIEA TGFA Module Name Interrupt controller Data Bus Width 8 bits Bus controller 8 bits BRSTRM BRSTS1 BRSTS0 -- -- -- -- P35DR P75DR -- PB5DR PC5DR PD5DR PE5DR PF5DR -- CCLR0 BFB IOB1 IOD1 -- -- -- -- P14DR P34DR P74DR -- PB4DR PC4DR PD4DR PE4DR PF4DR PG4DR CKEG1 BFA IOB0 IOD0 TCIEV TCFV -- RAMS P13DR P33DR -- PA3DR PB3DR PC3DR PD3DR PE3DR PF3DR PG3DR CKEG0 MD3 IOA3 IOC3 TGIED TGFD -- -- P12DR P32DR -- PA2DR PB2DR PC2DR PD2DR PE2DR PF2DR PG2DR TPSC2 MD2 IOA2 IOC2 TGIEC TGFC FLASH Port 8 bits 8 bits H'FF0A PBDR H'FF0B PCDR H'FF0C PDDR H'FF0D PEDR H'FF0E PFDR H'FF0F PGDR H'FF10 H'FF11 H'FF12 H'FF13 H'FF14 H'FF15 H'FF16 H'FF17 H'FF18 H'FF19 H'FF1A TGR0B H'FF1B H'FF1C TGR0C H'FF1D TGR0A TCR0 TMDR0 TIOR0H TIOR0L TIER0 TSR0 TCNT0 TPU0 8 bits 16 bits 723 Register Address Name H'FF1E TGR0D H'FF1F H'FF20 H'FF21 H'FF22 H'FF24 H'FF25 H'FF26 H'FF27 H'FF28 H'FF29 H'FF2A TGR1B H'FF2B H'FF30 H'FF31 H'FF32 H'FF34 H'FF35 H'FF36 H'FF37 H'FF38 H'FF39 H'FF3A TGR2B H'FF3B H'FF68 H'FF69 TCR0 TCR1 TGR2A TCR2 TMDR2 TIOR2 TIER2 TSR2 TCNT2 TGR1A TCR1 TMDR1 TIOR1 TIER1 TSR1 TCNT1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name TPU0 Data Bus Width 16 bits -- -- IOB3 TTGE TCFD CCLR1 -- IOB2 -- -- CCLR0 -- IOB1 TCIEU TCFU CKEG1 -- IOB0 TCIEV TCFV CKEG0 MD3 IOA3 -- -- TPSC2 MD2 IOA2 -- -- TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU1 8 bits 16 bits -- -- IOB3 TTGE TCFD CCLR1 -- IOB2 -- -- CCLR0 -- IOB1 TCIEU TCFU CKEG1 -- IOB0 TCIEV TCFV CKEG0 MD3 IOA3 -- -- TPSC2 MD2 IOA2 -- -- TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU2 8 bits 16 bits CMIEB CMIEB CMFB CMFB CMIEA CMIEA CMFA CMFA OVIE OVIE OVF OVF CCLR1 CCLR1 ADTE -- CCLR0 CCLR0 -- -- CKS2 CKS2 -- -- CKS1 CKS1 -- -- CKS0 CKS0 -- -- TMR0,TMR1 8 bits H'FF6A TCSR0 H'FF6B TCSR1 H'FF6C TCORA0 H'FF6D TCORA1 H'FF6E TCORB0 H'FF6F TCORB1 H'FF70 H'FF71 H'FF74 H'FF75 (read) H'FF77 (read) TCNT0 TCNT1 TCSR0 TCNT0 RSTCSR 8/16 bits OVF WT/IT TME -- -- CKS2 CKS1 CKS0 Watchdog timer 0 16 bits WOVF RSTE -- -- -- -- -- -- 724 Register Address Name H'FF78 H'FF79 SMR0 BRR0 Bit 7 C/A Bit 6 CHR Bit 5 PE Bit 4 O/E Bit 3 STOP Bit 2 MP Bit 1 CKS1 Bit 0 CKS0 Module Name SCI0 Data Bus Width 8 bits H'FF7A SCR0 H'FF7B TDR0 H'FF7C SSR0 H'FF7D RDR0 H'FF7E SCMR0 H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER PER TEND MPB MPBT -- C/A -- CHR -- PE -- O/E SDIR STOP -- MP -- CKS1 -- CKS0 SCI1 8 bits TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER PER TEND MPB MPBT -- AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGS1 OVF -- AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE TRGS0 WT/IT -- AD7 -- AD7 -- AD7 -- AD7 -- ADST -- TME -- AD6 -- AD6 -- AD6 -- AD6 -- SCAN -- PSS SDIR AD5 -- AD5 -- AD5 -- AD5 -- -- CKS1 -- AD4 -- AD4 -- AD4 -- AD4 -- CH2 CKS0 -- AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- CKS1 -- AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- CKS0 Watchdog timer 1 16 bits A/D converter 8 bits H'FFA2 TCSR1 H'FFA3 TCNT1 (read) H'FFA8 FLMCR1 H'FFA9 FLMCR2 H'FFAA EBR1 H'FFAB EBR2 H'FFAC FLPWCR H'FFB0 PORT1 H'FFB2 PORT3 H'FFB3 PORT4 H'FFB6 PORT7 H'FFB9 PORTA RST/NMI CKS2 FWE FLER EB7 -- SWE1 -- EB6 -- ESU1 -- EB5 -- -- -- P35 P45 -- -- PSU1 -- EB4 -- -- P14 P34 P44 -- -- EV1 -- EB3 -- -- P13 P33 P43 -- PA3 PV1 -- EB2 -- -- P12 P32 P42 -- PA2 E1 -- EB1 EB9 -- P11 P31 P41 -- PA1 P1 -- EB0 EB8 -- P10 P30 P40 -- PA0 FLASH 8 bits PDWND -- -- -- P47 -- -- P16 -- P46 P76 -- Port 8 bits 725 Register Address Name H'FFBA PORTB H'FFBB PORTC H'FFBC PORTD H'FFBD PORTE H'FFBE PORTF H'FFBF PORTG Bit 7 PB7 PC7 PD7 PE7 PF7 -- Bit 6 PB6 PC6 PD6 PE6 PF6 -- Bit 5 PB5 PC5 PD5 PE5 PF5 -- Bit 4 PB4 PC4 PD4 PE4 PF4 PG4 Bit 3 PB3 PC3 PD3 PE3 PF3 PG3 Bit 2 PB2 PC2 PD2 PE2 PF2 PG2 Bit 1 PB1 PC1 PD1 PE1 PF1 PG1 Bit 0 PB0 PC0 PD0 PE0 PF0 PG0 Module Name Port Data Bus Width 8 bits Note: * Located in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as register information, and 16 bits otherwise. 726 B.2 Functions H'EBC0 to H'EFBF 5 DM1 Undefined -- 4 DM0 Undefined -- 3 MD1 Undefined -- 2 MD0 Undefined -- 1 DTS Undefined -- 0 Sz Undefined -- MRA--DTC Mode Register A Bit : 7 SM1 Initial value : R/W : Undefined -- 6 SM0 Undefined -- DTC DTC Data Transfer Size 0 Byte-size transfer 1 Word-size transfer DTC Transfer Mode Select 0 Destination side is repeat area or block area 1 Source side is repeat area or block area DTC Mode 00 1 10 1 Normal mode Repeat mode Block transfer mode -- Destination Address Mode 0-- 10 1 DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) Source Address Mode 0-- 10 1 SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) 727 MRB--DTC Mode Register B Bit : 7 CHNE Initial value: R/W : Undefined -- 6 DISEL Undefined -- 5 -- Undefined -- 4 -- Undefined -- H'EBC0 to H'EFBF 3 -- Undefined -- 2 -- Undefined -- 1 -- Undefined -- 0 -- DTC Undefined -- Reserved Only 0 should be written to these bits DTC Interrupt Select 0 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 1 After a data transfer ends, the CPU interrupt is enabled DTC Chain Transfer Enable 0 End of DTC data transfer 1 DTC chain transfer SAR--DTC Source Address Register Bit : 23 22 21 20 19 H'EBC0 to H'EFBF 4 3 2 1 DTC 0 Initial value: R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- Specifies transfer data source address DAR--DTC Destination Address Register Bit : 23 22 21 20 19 H'EBC0 to H'EFBF 4 3 2 1 DTC 0 Initial value : R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- Specifies transfer data destination address 728 CRA--DTC Transfer Count Register A Bit : 15 14 13 12 11 10 9 8 H'EBC0 to H'EFBF 7 6 5 4 3 2 1 DTC 0 Initial value: R/W : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -------------------------------- CRAH CRAL Specifies the number of DTC data transfers CRB--DTC Transfer Count Register B Bit : 15 14 13 12 11 10 9 8 H'EBC0 to H'EFBF 7 6 5 4 3 2 1 DTC 0 Initial value: R/W : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -------------------------------- Specifies the number of DTC block data transfers SCRX--Serial Control Register X Bit : 7 -- Initial value : R/W : 0 R/W 6 -- 0 R/W 5 -- 0 R/W 4 -- 0 R/W H'FDB4 3 FLSHE 0 R/W 2 -- 0 R/W 1 -- 0 R/W FLASH 0 -- 0 R/W Flash memory control register enable 729 SMR3--Serial Mode Register 3 Bit : 7 C/A Initial value : R/W : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FDD0 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 SCI3 CKS0 0 R/W Clock Select 0 1 0 o clock 1 o/4 clock 0 o/16 clock 1 o/64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop Bit Length 0 1 stop bit Parity Mode 0 Even parity*1 1 Odd parity*2 Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. *2 When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd. Parity Enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled* Note: * When the PE bit is set to 1, an even or odd parity bit is added to transmit data according to the even or odd parity mode selection by the O/E bit, and the parity bit in receive data is checked to see if it matches the even or odd mode selected by the O/E bit. Character Length 0 8-bit data 1 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible to choose between LSB-first or MSB-first transfer. Selects Asynchronous Mode or Clocked Synchronous Mode 0 Asynchronous mode 1 Clocked synchronous mode 1 2 stop bits 730 BRR3--Bit Rate Register 3 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FDD1 3 1 R/W 2 1 R/W 1 1 R/W 0 1 SCI3 Initial value : R/W : R/W Sets the serial transfer bit rate Note: For details, see section 13.2.8, Bit Rate Register (BRR). 731 SCR3--Serial Control Register 3 Bit : 7 TIE Initial value : R/W : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W H'FDD2 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W SCI3 Clock Enable 0 0 Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode 1 * Setting prohibited*2 Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output Transmit End Interrupt Enable 0 Transmit end interrupt (TEI) request disabled*3 1 Transmit end interrupt (TEI) request enabled*3 Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When MPB= 1 data is received 1 Multiprocessor interrupts enabled*4 Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. Receive Enable 0 Reception disabled*5 1 Reception enabled*6 Transmit Enable 0 Transmission disabled*7 1 Transmission enabled*8 Receive Interrupt Enable 0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled*9 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 Transmit data empty interrupt (TXI) requests disabled 1 Transmit data empty interrupt (TXI) requests enabled Note: TXI cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or by clearing the TIE bit to 0. 732 Notes: *1 Outputs a clock of the same frequency as the bit rate. *2 The CKE1 bit of SCR3 should be cleared to 0. *3 TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0. *4 When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR, is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. *5 Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. *6 Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the receive format before setting the RE bit to 1. *7 The TDRE flag in SSR is fixed at 1. *8 In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transmit format before setting the TE bit to 1. *9 RXI and ERI cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0. TDR3--Transmit Data Register 3 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FDD3 3 1 R/W 2 1 R/W 1 1 R/W 0 1 SCI3 Initial value : R/W : R/W Stores data for serial transmission 733 SSR3--Serial Status Register 3 Bit : 7 TDRE Initial value : R/W : 1 R/(W)*1 6 RDRF 0 5 ORER 0 4 FER 0 3 PER 0 H'FDD4 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W SCI3 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit is received Transmit End 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] 1 * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character Parity Error 0 [Clearing condition] When 0 is written to PER after reading PER = 1 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR*2 Framing Error 0 [Clearing condition] * When 0 is written to FER after reading FER = 1 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0*3 Overrun Error 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1*4 Receive Data Register Full 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] 1 When serial reception ends normally and receive data is transferred from RSR to RDR Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Transmit Data Register Empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR 734 Notes: *1 Only 0 can be written, to clear the flag. *2 If a parity error occurs, the receive data is transferred to RDR but the RDRF flags is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. *3 In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. *4 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued either. RDR3--Receive Data Register 3 Bit : 7 0 R 6 0 R 5 0 R 4 0 R H'FDD5 3 0 R 2 0 R 1 0 R 0 0 R SCI3 Initial value : R/W : Stores received serial data SCMR3--Smart Card Mode Register 3 Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'FDD6 3 SDIR 0 R/W 2 -- 0 R/W 1 -- 1 -- 0 -- 0 SCI3 R/W Reserved Only 0 should be written to these bits Selects the Serial/Parallel Conversion Format 0 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first 735 SBYCR--Standby Control Register Bit : 7 SSBY Initial value : R/W : 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W H'FDE4 3 OPE 1 R/W 2 -- 0 -- Power-Down Modes 1 -- 0 -- 0 -- 0 -- Output Port Enable 0 In software standby mode and watch mode, and in a direct transition, address bus and bus control signals are high-impedance 1 In software standby mode and watch mode, and in a direct transition, address bus and bus control signals retain their output state Standby Timer Select 0 0 0 Standby time = 8192 states 1 Standby time = 16384 states 1 0 Standby time = 32768 states 1 Standby time = 65536 states 1 0 0 Standby time = 131072 states 1 Standby time = 262144 states 1 0 Reserved 1 Standby time = 16 states* Note: * Not used on the F-ZTAT version. Software Standby 0 Transition to sleep mode after execution of SLEEP instruction in high-speed mode or medium-speed mode Transition to subsleep mode after execution of SLEEP instruction in subactive mode 1 Transition to software standby mode, subactive mode, or watch mode after execution of SLEEP instruction in high-speed mode or medium-speed mode Transition to watch mode or high-speed mode after execution of SLEEP instruction in subactive mode 736 SYSCR--System Control Register Bit : 7 -- Initial value: R/W : 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W H'FDE5 3 NMIEG 0 R/W 2 -- 0 R/W 1 -- 0 -- 0 RAME 1 R/W MCU RAM Enable 0 On-chip RAM is disabled 1 On-chip RAM is enabled Note: When the DTC is used, the RAME bit must be set to 1. Reserved Only 0 should be written to this bit NMI Interrupt Input Edge Select 0 Falling edge 1 Rising edge Interrupt Control Mode Select 0 1 0 1 0 1 Interrupt control mode 0 Setting prohibited Interrupt control mode 2 Setting prohibited Reserved Only 0 should be written to this bit 737 SCKCR--System Clock Control Register Bit : 7 PSTOP Initial value: R/W : 0 R/W 6 -- 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 H'FDE6 2 SCK2 0 R/W Clock Pulse Generator 1 SCK1 0 R/W 0 SCK0 0 R/W -- 0 R/W Reserved Only 0 should be written to these bits Bus Master Clock Select 0 00 1 10 1 00 1 1-- Bus master is in high-speed mode Medium-speed clock is o/2 Medium-speed clock is o/4 Medium-speed clock is o/8 Medium-speed clock is o/16 Medium-speed clock is o/32 -- 1 o Clock Output Control PSTOP High-Speed Sleep Mode, Mode, Medium- Subsleep Mode Speed Mode, Subactive Mode o output Fixed high o output Fixed high Software Standby Mode, Watch Mode, Direct Transition Fixed high Fixed high Hardware Standby Mode 0 1 High impedance High impedance MDCR--Mode Control Register Bit : 7 -- Initial value: R/W : 1 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- H'FDE7 3 -- 0 -- 2 MDS2 --* R 1 MDS1 --* R 0 MCU MDS0 --* R Current mode pin operating mode Note: * Determined by pins MD2 to MD0. 738 MSTPCRA--Module Stop Control Register A MSTPCRB--Module Stop Control Register B MSTPCRC--Module Stop Control Register C MSTPCRA Bit : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W H'FDE8 H'FDE9 H'FDEA Power-Down State 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W MSTPCRB Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W : MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : R/W MSTPCRC Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W : MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : R/W : Specifies Module Stop Mode 0 Module stop mode is cleared 1 Module stop mode is set 739 PFCR--Pin Function Control Register Bit Modes 4 and 5 Initial value Modes 6 and 7 Initial value R/W : : 0 R/W 0 R/W 0 R/W 0 R/W : 0 0 0 0 : 7 -- 6 -- 5 BUZZE 4 -- H'FDEB 3 AE3 1 0 R/W 2 AE2 1 0 R/W Bus Controller 1 AE1 0 0 R/W 0 AE0 1 0 R/W Reserved Only 0 should be written to these bits Reserved Only 0 should be written to this bit Address Output Enable 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A8 to A23 output disabled (Initial value)*1 A8 output enabled; A9 to A23 output disabled A8, A9 output enabled; A10 to A23 output disabled A8 to A10 output enabled; A11 to A23 output disabled A8 to A11 output enabled; A12 to A23 output disabled A8 to A12 output enabled; A13 to A23 output disabled A8 to A13 output enabled; A14 to A23 output disabled A8 to A14 output enabled; A15 to A23 output disabled A8 to A15 output enabled; A16 to A23 output disabled A8 to A16 output enabled; A17 to A23 output disabled A8 to A17 output enabled; A18 to A23 output disabled A8 to A18 output enabled; A19 to A23 output disabled A8 to A19 output enabled; A20 to A23 output disabled A8 to A20 output enabled; A21 to A23 output disabled (Initial value)*2 A8 to A21 output enabled; A22, A23 output disabled A8 to A23 output enabled Notes: *1 In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000. In expanded mode with ROM, address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to 1. *2 In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101. In ROMless expanded mode, address pins A0 to A7 are always address outputs. BUZZ Output Enable 0 Functions as PF1 I/O pin 1 Functions as BUZZ output pin 740 LPWRCR--Low-Power Control Register Bit : 7 DTON Initial value : R/W : 0 R/W 6 LSON 0 R/W 5 0 R/W 4 0 R/W 3 0 H'FDEC 2 -- 0 R/W 1 STC1 0 R/W Power-Down Modes 0 STC0 0 R/W NESEL SUBSTP RFCUT R/W Frequency Multiplication Factor 00 1 10 1 Built-In Feedback Resistor Control 0 System clock oscillator's built-in feedback resistor and duty adjustment circuit are used 1 System clock oscillator's built-in feedback resistor and duty adjustment circuit are not used Subclock Oscillator Control 0 Subclock oscillator operates 1 Subclock oscillator is stopped Note: When the subclock is not used, this bit should be set to 1. Noise Elimination Sampling Frequency Select 0 Sampling at o divided by 8 1 Sampling at o divided by 4 Low-Speed On Flag 0 When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode* When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode, or directly to high-speed mode After watch mode is cleared, a transition is made to high-speed mode 1 When a SLEEP instruction is executed in high-speed mode a transition is made to watch mode or subactive mode* When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode After watch mode is cleared, a transition is made to subactive mode Direct-Transfer On Flag 0 When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode* When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode 1 When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made directly to subactive mode*, or a transition is made to sleep mode or software standby mode When a SLEEP instruction is executed in subactive mode, a transition is made directly to high-speed mode, or a transition is made to subsleep mode x1 (Initial value) x2 (Setting prohibited) x4 (Setting prohibited) PLL is bypassed Note: * When a transition is made to watch mode or subactive mode, high-speed mode must be set. 741 BARA--Break Address Register A BARB--Break Address Register B Bit : 31 -- Initial value : Undefined R/W :-- *** H'FE00 H'FE04 20 19 18 17 16 *** PBC 24 -- 23 22 21 7 6 5 4 3 2 1 0 *** BAA BAA BAA BAA BAA BAA BAA BAA 23 22 21 20 19 18 17 16 *** BAA BAA BAA BAA BAA BAA BAA BAA 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 *** *** Unde- 0 0 0 0 0 0 0 0 fined -- R/W R/W R/W R/W R/W R/W R/W R/W *** *** R/W R/W R/W R/W R/W R/W R/W R/W Bit : 31 -- *** 24 -- 23 22 21 20 19 18 17 16 *** 7 6 5 4 3 2 1 0 *** BAB BAB BAB BAB BAB BAB BAB BAB 23 22 21 20 19 18 17 16 *** BAB BAB BAB BAB BAB BAB BAB BAB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Initial value : Undefined R/W :-- *** *** Unde- 0 0 0 0 0 0 0 0 fined -- R/W R/W R/W R/W R/W R/W R/W R/W *** *** R/W R/W R/W R/W R/W R/W R/W R/W These bits hold the channel A or B PC break address 742 BCRA--Break Control Register A Bit : 7 CMFA Initial value : R/W : 0 R/(W)* 6 CDA 0 R/W 5 4 3 H'FE08 2 1 0 BIEA 0 R/W PBC BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Break Interrupt Enable 0 PC break interrupts are disabled 1 PC break interrupts are enabled Break Condition Select 00 1 10 1 Instruction fetch Data read cycle Data write cycle Data read/write cycle Break Address Mask Register 000 1 10 1 100 1 10 1 All BARA bits are unmasked and included in break conditions BAA0 (lowest bit) is masked, and not included in break conditions BAA1 to 0 (lower 2 bits) are masked, and not included in break conditions BAA2 to 0 (lower 3 bits) are masked, and not included in break conditions BAA3 to 0 (lower 4 bits) are masked, and not included in break conditions BAA7 to 0 (lower 8 bits) are masked, and not included in break conditions BAA11 to 0 (lower 12 bits) are masked, and not included in break conditions BAA15 to 0 (lower 16 bits) are masked, and not included in break conditions CPU Cycle/DTC Cycle Select 0 PC break is performed when CPU is bus master 1 PC break is performed when CPU or DTC is bus master Condition Match Flag A 0 [Clearing condition] When 0 is written to CMFA after reading CMFA = 1 1 [Setting condition] When a condition set for channel A is satisfied Note: * Only 0 can be written, to clear the flag. BCRB--Break Control Register B Bit : 7 CMFB Initial value : R/W : 0 R/W 6 CDB 0 R/W 5 4 H'FE09 3 2 1 0 BIEB 0 R/W PBC BAMRB2 BAMRB1 BAMRB0 CSELB1 CSELB0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W The bit configuration is the same as for BCRA 743 ISCRH--IRQ Sense Control Register H ISCRL--IRQ Sense Control Register L ISCRH H'FE12 H'FE13 Interrupt Controller Bit : 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value: R/W : IRQ7 to IRQ4 Sense Control ISCRL Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value: R/W : IRQ3 to IRQ0 Sense Control IRQnSCB 0 1 IRQnSCA 0 1 0 1 Interrupt Request Generation IRQn input low level Falling edge of IRQn input Rising edge of IRQn input Both falling and rising edges of IRQn input (n= 7 to 0) 744 IER--IRQ Enable Register Bit : 7 IRQ7E Initial value : R/W : 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W H'FE14 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W Interrupt Controller 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W IRQn Enable 0 IRQn interrupts disabled 1 IRQn interrupts enabled (n= 7 to 0) ISR--IRQ Status Register Bit : 7 IRQ7F Initial value: R/W : 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* H'FE15 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* Interrupt Controller 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* Indicates the status of IRQ7 to IRQ0 interrupt requests Note: * Only 0 can be written, to clear the flag. 745 DTCER--DTC Enable Registers H'FE16 to H'FE1A, H'FE1E 5 DTCE5 0 R/W 4 DTCE4 0 R/W 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTC Bit : 7 DTCE7 0 R/W 6 DTCE6 0 R/W DTCE0 0 R/W Initial value: R/W : DTC Activation Enable 0 DTC activation by this interrupt is disabled [Clearing conditions] * When the DISEL bit is 1 and the data transfer has ended * When the specified number of transfers have ended 1 DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended Correspondence between Interrupt Sources and DTCER Bit Register DTCERA DTCERB DTCERC DTCERD DTCERE DTCERI 7 IRQ0 -- TGI2A -- -- RXI3 6 IRQ1 ADI TGI2B -- -- TXI3 5 IRQ2 TGI0A -- -- -- -- 4 IRQ3 TGI0B -- -- -- -- 3 IRQ4 TGI0C -- CMIA0 RXI0 -- 2 IRQ5 TGI0D -- CMIB0 TXI0 -- 1 IRQ6 TGI1A -- CMIA1 RXI1 -- 0 IRQ7 TGI1B -- CMIB1 TXI1 -- 746 DTVECR--DTC Vector Register Bit : 7 0 R/(W) *1 H'FE1F 5 0 4 0 *2 DTC 2 0 1 0 *2 6 0 R/(W) *2 3 0 *2 0 0 *2 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value: R/W : R/(W) R/(W) R/(W) *2 R/(W) R/(W) R/(W)*2 Sets vector number for DTC software activation DTC Software Activation Enable 0 DTC software activation is disabled [Clearing conditions] * When the DISEL bit is 0 and the specified number of transfers have not ended * When 0 is written to the DISEL bit after a software-activated data transfer end interrupt (SWDTEND) request has been sent to the CPU 1 DTC software activation is enabled [Holding conditions] * When the DISEL bit is 1 and data transfer has ended * When the specified number of transfers have ended * During data transfer due to software activation Notes: *1 Only 1 can be written to the SWDTE bit. *2 Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0. P1DDR--Port 1 Data Direction Register Bit : 7 -- Initial value : Undefined R/W : W 6 P16DDR 0 W 5 -- Undefined H'FE30 4 0 W 3 0 W 2 0 W 1 0 W 0 0 Port 1 P14DDR P13DDR P12DDR P11DDR P10DDR W W Specify input or output for the pins of port 1 747 P3DDR--Port 3 Data Direction Register Bit : 7 -- Initial value : Undefined R/W : -- 6 0 W 5 0 W 4 0 W H'FE32 3 0 W 2 0 W 1 0 W 0 0 Port 3 P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR W Specify input or output for the pins of port 3 P7DDR--Port 7 Data Direction Register Bit : 7 P77DDR Initial value : R/W : 0 W 6 -- Undefined H'FE36 4 0 W 3 -- W 2 -- W 1 -- W 0 Port 7 5 0 W P75DDR P74DDR -- W Undefined Undefined Undefined Undefined W Specify input or output for the pins of port 7 PADDR--Port A Data Direction Register Bit : 7 -- R/W : -- 6 -- -- 5 -- -- 4 -- -- H'FE39 3 0 W 2 0 W 1 0 W 0 0 W Port A PA3DDR PA2DDR PA1DDR PA0DDR Initial value : Undefined Undefined Undefined Undefined Specify input or output for the pins of port A PBDDR--Port B Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FE3A 3 0 W 2 0 W 1 0 W 0 0 Port B PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value : R/W : W Specify input or output for the pins of port B 748 PCDDR--Port C Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FE3B 3 0 W 2 0 W 1 0 W Port C 0 0 W PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Initial value : R/W : Specify input or output for the pins of port C PDDDR--Port D Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FE3C 3 0 W 2 0 W 1 0 W Port D 0 0 W PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : R/W : Specify input or output for the pins of port D PEDDR--Port E Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FE3D 3 0 W 2 0 W 1 0 W 0 0 Port E PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : R/W : W Specify input or output for the pins of port E 749 PFDDR--Port F Data Direction Register Bit Modes 4 to 6 Initial value R/W Mode 7 Initial value R/W : : 0 W 0 W 0 W 0 W : : 1 W 0 W 0 W 0 W : 7 6 5 4 H'FE3E 3 2 1 Port F 0 PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Specify input or output for the pins of port F PGDDR--Port G Data Direction Register Bit Modes 4 and 5 Initial value R/W Modes 6 and 7 Initial value R/W : Undefined Undefined Undefined : -- -- -- 0 W : Undefined Undefined Undefined : -- -- -- 1 W : 7 -- 6 -- 5 -- 4 H'FE3F 3 2 1 Port G 0 -- Undefined W Undefined W PG4DDR PG3DDR PG2DDR PG1DDR 0 W 0 W 0 W 0 W 0 W 0 W Specify input or output for the pins of port G 750 PAPCR--Port A MOS Pull-Up Control Register Bit : 7 -- R/W : -- 6 -- -- 5 -- -- 4 -- -- H'FE40 3 0 R/W 2 0 R/W 1 0 R/W 0 0 Port A PA3PCR PA2PCR PA1PCR PA0PCR R/W Initial value : Undefined Undefined Undefined Undefined Controls the MOS input pull-up function incorporated into port A on a bit-by-bit basis PBPCR--Port B MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE41 3 0 R/W 2 0 R/W 1 0 R/W 0 0 Port B PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : R/W : R/W Controls the MOS input pull-up function incorporated into port B on a bit-by-bit basis PCPCR--Port C MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE42 3 0 R/W 2 0 R/W 1 0 R/W Port C 0 0 R/W PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : R/W : Controls the MOS input pull-up function incorporated into port C on a bit-by-bit basis PDPCR--Port D MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE43 3 0 R/W 2 0 R/W 1 0 R/W Port D 0 0 R/W PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : R/W : Controls the MOS input pull-up function incorporated into port D on a bit-by-bit basis 751 PEPCR--Port E MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE44 3 0 R/W 2 0 R/W 1 0 R/W 0 0 Port E PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : R/W : R/W Controls the MOS input pull-up function incorporated into port E on a bit-by-bit basis P3ODR--Port 3 Open-Drain Control Register Bit : 7 -- R/W : -- 6 -- R/W 5 0 R/W 4 0 R/W H'FE46 3 0 R/W 2 0 R/W 1 0 R/W 0 0 Port 3 P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR R/W Initial value : Undefined Undefined Controls the PMOS on/off status for each port 3 pin (P35 to P30) PAODR--Port A Open-Drain Control Register Bit : 7 -- R/W : -- 6 -- -- 5 -- -- 4 -- -- H'FE47 3 0 R/W 2 0 R/W 1 0 R/W 0 0 Port A PA3ODR PA2ODR PA1ODR PA0ODR R/W Initial value : Undefined Undefined Undefined Undefined Controls the PMOS on/off status for each port A pin (PA3 to PA0) 752 TSTR--Timer Start Register Bit : 7 -- Initial value : R/W : 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- H'FEB0 3 -- 0 -- 2 CST2 0 R/W 1 CST1 0 R/W 0 TPU CST0 0 R/W Counter Start 0 TCNTn count operation is stopped 1 TCNTn performs count operation (n= 2 to 0) Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. TSYR--Timer Synchro Register Bit : 7 -- Initial value : R/W : 0 -- 6 -- 0 -- 5 -- 0 -- Timer Synchro H'FEB1 4 -- 0 -- 3 -- 0 -- 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 TPU SYNC0 0 R/W 0 TCNTn operates independently (TCNT presetting/clearing is unrelated to other channels) 1 TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible (n= 2 to 0) Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. 2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 753 IPRA--Interrupt Priority Register A IPRB --Interrupt Priority Register B IPRC--Interrupt Priority Register C IPRD--Interrupt Priority Register D IPRE --Interrupt Priority Register E IPRF --Interrupt Priority Register F IPRG--Interrupt Priority Register G IPRI --Interrupt Priority Register I IPRJ --Interrupt Priority Register J IPRK--Interrupt Priority Register K IPRO--Interrupt Priority Register O Bit : 7 -- Initial value : R/W : 0 -- 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC4 H'FEC5 H'FEC6 H'FEC8 H'FEC9 H'FECA H'FECE 3 -- 0 -- 2 IPR2 1 R/W Interrupt Controller 1 IPR1 1 R/W 0 IPR0 1 R/W Set priority (levels 7 to 0) for interrupt sources Correspondence between Interrupt Sources and IPR Settings Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRI IPRJ IPRK IPRO Bits 6 to 4 IRQ0 IRQ2, IRQ3 IRQ6, IRQ7 Watchdog timer 0 PC break TPU channel 0 TPU channel 2 8-bit timer channel 0 --* SCI channel 1 SCI channel 3 2 to 0 IRQ1 IRQ4, IRQ5 DTC --* A/D converter, watchdog timer 1 TPU channel 1 --* 8-bit timer channel 1 SCI channel 0 --* --* Note: * Reserved bits. These bits cannot be modified and are always read as 1. 754 ABWCR--Bus Width Control Register Bit : 7 ABW7 Modes 5 to 7 Initial value : R/W Mode 4 Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W : 1 R/W 6 ABW6 1 R/W 5 ABW5 1 R/W 4 ABW4 1 R/W H'FED0 3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W Bus Controller 1 ABW1 1 R/W 0 R/W 0 ABW0 1 R/W 0 R/W Area 7 to 0 Bus Width Control 0 Area n is designated for 16-bit access 1 Area n is designated for 8-bit access (n= 7 to 0) ASTCR--Access State Control Register Bit : 7 AST7 Initial value : R/W : 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W H'FED1 3 AST3 1 R/W 2 AST2 1 R/W 1 Bus Controller 0 AST0 1 R/W AST1 1 R/W Area 7 to 0 Access State Control 0 Area n is designated for 2-state access Wait state insertion in area n external space is disabled 1 Area n is designated for 3-state access Wait state insertion in area n external space is enabled (n= 7 to 0) 755 WCRH--Wait Control Register H Bit : 7 W71 Initial value : R/W : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W H'FED2 3 W51 1 R/W 2 W50 1 R/W Bus Controller 1 W41 1 R/W 0 W40 1 R/W Area 4 Wait Control 0 0 Program wait not inserted 1 10 1 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Area 5 Wait Control 00 1 10 1 Area 6 Wait Control 00 1 10 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Area 7 Wait Control 00 1 10 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 756 WCRL--Wait Control Register L Bit : 7 W31 Initial value : R/W : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W H'FED3 3 W11 1 R/W 2 W10 1 R/W 1 Bus Controller 0 W00 1 R/W W01 1 R/W Area 0 Wait Control 00 1 10 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Area 1 Wait Control 00 1 10 1 Area 2 Wait Control 00 1 10 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Area 3 Wait Control 00 1 10 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 757 BCRH--Bus Control Register H Bit : 7 ICIS1 Initial value : R/W : 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W H'FED4 3 0 R/W 2 -- 0 R/W 1 Bus Controller 0 -- 0 R/W BRSTRM BRSTS1 BRSTS0 -- 0 R/W Reserved Only 0 should be written to these bits Burst Cycle Select 0 0 Max. 4 words in burst access 1 Max. 8 words in burst access Burst Cycle Select 1 0 Burst cycle comprises 1 state 1 Burst cycle comprises 2 states Area 0 Burst ROM Enable 0 Area 0 is basic bus interface 1 Area 0 is burst ROM interface Idle Cycle Insert 0 0 Idle cycle not inserted in case of successive external read and external write cycles 1 Idle cycle inserted in case of successive external read and external write cycles Idle Cycle Insert 1 0 Idle cycle not inserted in case of successive external read cycles in different areas 1 Idle cycle inserted in case of successive external read cycles in different areas 758 BCRL--Bus Control Register L Bit : 7 BRLE Initial value : R/W : 0 R/W 6 -- 0 R/W 5 -- 0 -- 4 -- 0 R/W H'FED5 3 -- 1 R/W 2 -- 0 R/W 1 Bus Controller 0 WAITE 0 R/W -- 0 R/W WAIT Pin Enable 0 Wait input by WAIT pin disabled 1 Wait input by WAIT pin enabled Reserved Only 0 should be written to these bits Reserved Only 1 should be written to this bit Reserved Only 0 should be written to this bit Reserved This bit cannot be modified Reserved Only 0 should be written to this bit Bus Release Enable 0 External bus release is disabled 1 External bus release is enabled 759 RAMER--RAM Emulation Register Bit : 7 -- Initial value : R/W : 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R/W H'FEDB 3 RAMS 0 R/W 2 -- 0 R/W 1 RAM1 0 R/W 0 ROM RAM0 0 R/W Flash Memory Area Selection Reserved Only 0 should be written to these bits RAM Select 0 Emulation not selected Program/erase-protection of all flash memory blocks is disabled 1 Emulation selected Program/erase-protection of all flash memory blocks is enabled P1DR--Port 1 Data Register Bit : 7 -- Initial value : Undefined R/W : R/W 6 P16DR 0 R/W 5 -- Undefined R/W 4 P14DR 0 R/W H'FF00 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 Port 1 P10DR 0 R/W Stores output data for the port 1 pins (P16, P14 to P10) P3DR--Port 3 Data Register Bit : 7 -- Initial value : Undefined R/W : -- 6 P36DR 0 R/W 5 P35DR 0 R/W 4 P34DR 0 R/W H'FF02 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 Port 3 P30DR 0 R/W Stores output data for the port 3 pins (P36 to P30) 760 P7DR--Port 7 Data Register Bit : 7 P77DR Initial value : R/W : 0 R/W 6 -- Undefined H'FF06 5 P75DR 0 R/W 4 P74DR 0 R/W 3 -- R/W 2 -- R/W 1 -- R/W 0 Port 7 -- R/W Undefined Undefined Undefined Undefined R/W Stores output data for the port 7 pins (P77, P75, P74) PADR--Port A Data Register Bit : 7 -- R/W : -- 6 -- -- 5 -- -- 4 -- -- H'FF09 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 Port A PA0DR 0 R/W Initial value : Undefined Undefined Undefined Undefined Stores output data for the port A pins (PA3 to PA0) PBDR--Port B Data Register Bit : 7 0 R/W 6 0 R/W 5 PB5DR 0 R/W 4 PB4DR 0 R/W H'FF0A 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W 0 Port B PB7DR PB6DR Initial value : R/W : PB0DR 0 R/W Stores output data for the port B pins (PB7 to PB0) PCDR--Port C Data Register Bit : 7 PC7DR Initial value : R/W : 0 R/W 6 PC6DR 0 R/W 5 PC5DR 0 R/W 4 PC4DR 0 R/W H'FF0B 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W Port C 0 PC0DR 0 R/W Stores output data for the port C pins (PC7 to PC0) 761 PDDR--Port D Data Register Bit : 7 PD7DR Initial value : R/W : 0 R/W 6 PD6DR 0 R/W 5 PD5DR 0 R/W 4 PD4DR 0 R/W H'FF0C 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W Port D 0 PD0DR 0 R/W Stores output data for the port D pins (PD7 to PD0) PEDR--Port E Data Register Bit : 7 PE7DR Initial value : R/W : 0 R/W 6 PE6DR 0 R/W 5 PE5DR 0 R/W 4 PE4DR 0 R/W H'FF0D 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W 0 Port E PE0DR 0 R/W Stores output data for the port E pins (PE7 to PE0) PFDR--Port F Data Register Bit : 7 PF7DR Initial value : R/W : 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4 PF4DR 0 R/W H'FF0E 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W Port F 0 PF0DR 0 R/W Stores output data for the port F pins (PF7 to PF0) PGDR--Port G Data Register Bit : 7 -- R/W : -- 6 -- -- 5 -- -- 4 0 R/W H'FF0F 3 0 R/W 2 0 R/W 1 PG1DR 0 R/W Port G 0 -- Undefined R/W PG4DR PG3DR PG2DR Initial value : Undefined Undefined Undefined Stores output data for the port G pins (PG4 to PG1) 762 TCR0--Timer Control Register 0 Bit : 7 CCLR2 Initial value : R/W : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W H'FF10 3 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPU0 CKEG1 CKEG0 TPSC0 0 R/W Time Prescaler 000 1 10 1 100 1 10 1 Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Setting prohibited Setting prohibited Select the Input Clock Edge 0 0 1 1-- Count at rising edge Count at falling edge Count at both edges Note: The internal clock edge selection is valid when the input clock is o/4 or slower. This setting is ignored if the input clock is o/1, or when overflow/underflow of another channel is selected. Counter Clear 000 1 10 1 100 1 10 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation *1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture *2 TCNT cleared by TGRD compare match/input capture *2 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation *1 Notes: *1 Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. *2 When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 763 TMDR0--Timer Mode Register 0 Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 BFB 0 R/W 4 BFA 0 R/W H'FF11 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 TPU0 MD0 0 R/W Modes 0000 1 10 1 100 1 10 1 1*** Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Setting prohibited *: Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channel 0. In this case, 0 should always be written to MD2. Buffer Operation A 0 1 TGRA operates normally TGRA and TGRC used together for buffer operation Buffer Operation B 0 1 TGRB operates normally TGRB and TGRD used together for buffer operation 764 TIOR0H--Timer I/O Control Register 0H Bit : 7 IOB3 Initial value : R/W : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FF12 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W TPU0 0 IOA0 0 R/W TGR0A I/O Control 0000 1 10 1 100 1 10 1 1000 1 1* 1** TGR0A is output compare register Output disabled Initial output is 0 output Output disabled Initial output is 1 output TGR0A is input capture register Capture input source isTIOCA0 pin Capture input source is channel 1/count clock 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT1 countup/count-down *: Don't care TGR0B I/O Control 0000 1 10 1 100 1 10 1 1000 1 1* 1** TGR0B is output compare register Output disabled Initial output is 0 output Output disabled Initial output is 1 output TGR0B is input capture register Capture input source isTIOCB0 pin Capture input source is channel 1/count clock 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT1 countup/count-down*1 *: Don't care Note: *1 When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and o/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. 765 TIOR0L--Timer I/O Control Register 0L Bit : 7 IOD3 Initial value : R/W : 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W H'FF13 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W TPU0 TGR0C I/O Control 0000 1 10 1 100 1 10 1 1000 1 1* 1** TGR0C is output compare register*1 Output disabled Initial output is 0 output Output disabled Initial output is 1 output TGR0C is input capture register*1 Capture input source isTIOCC0 pin Capture input source is channel 1/count clock 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT1 countup/count-down *: Don't care Note: *1 When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. TGR0D I/O Control 0000 1 10 1 100 1 10 1 1000 1 1* 1** TGR0D is output compare register*2 Output disabled Initial output is 0 output Output disabled Initial output is 1 output TGR0D is input capture register*2 Capture input source is TIOCD0 pin Capture input source is channel 1/count clock 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT1 countup/count-down*1 *: Don't care Notes: *1 When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and o/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. *2 When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. 766 TIER0--Timer Interrupt Enable Register 0 Bit : 7 TTGE Initial value : R/W : 0 R/W 6 -- 1 -- 5 -- 0 -- 4 TCIEV 0 R/W H'FF14 3 TGIED 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TPU0 TGIEA 0 R/W TGR Interrupt Enable A 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled TGR Interrupt Enable C 0 Interrupt requests (TGIC) by TGFC bit disabled 1 Interrupt requests (TGIC) by TGFC bit enabled TGR Interrupt Enable D 0 Interrupt requests (TGID) by TGFD bit disabled 1 Interrupt requests (TGID) by TGFD bit enabled Overflow Interrupt Enable 0 Interrupt requests (TCIV) by TCFV disabled 1 Interrupt requests (TCIV) by TCFV enabled A/D Conversion Start Request Enable 0 A/D conversion start request generation disabled 1 A/D conversion start request generation enabled 767 TSR0--Timer Status Register 0 Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 0 -- 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 H'FF15 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU0 TGFC 0 R/(W)* Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Input Capture/Output Compare Flag C 0 [Clearing conditions] * When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFC after reading TGFC = 1 1 [Setting conditions] * When TCNT = TGRC while TGRC is functioning as output compare register * When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register Input Capture/Output Compare Flag D 0 [Clearing conditions] * When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFD after reading TGFD = 1 1 [Setting conditions] * When TCNT = TGRD while TGRD is functioning as output compare register * When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register Overflow Flag 0 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. 768 TCNT0--Timer Counter 0 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FF16 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU0 0 0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TGR0A--Timer General Register 0A TGR0B--Timer General Register 0B TGR0C--Timer General Register 0C TGR0D--Timer General Register 0D Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FF18 H'FF1A H'FF1C H'FF1E 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU0 0 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 769 TCR1--Timer Control Register 1 Bit : 7 -- Initial value : R/W : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W H'FF20 3 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPU1 CKEG1 CKEG0 TPSC0 0 R/W Time Prescaler 000 1 10 1 100 1 10 1 Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on o/256 Setting prohibited Note: This setting is ignored when channel 1 is in phase counting mode. Select the Input Clock Edge 0 0 Count at rising edge 1 Count at falling edge 1 -- Count at both edges Notes: 1. This setting is ignored when channel 1 is in phase counting mode. 2. The internal clock edge selection is valid when the input clock is o/4 or slower. This setting is ignored if the input clock is o/1, or when overflow/underflow of another channel is selected. Counter Clear 00 1 10 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 770 TMDR1--Timer Mode Register 1 Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- H'FF21 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W TPU1 0 MD0 0 R/W Mode 0000 1 10 1 100 1 10 1 1*** Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Setting prohibited *: Don't care Note: MD3 is a reserved bit. In a write, it should always be written with 0. 771 TIOR1--Timer I/O Control Register 1 Bit : 7 IOB3 Initial value : R/W : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FF22 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 TPU1 IOA0 0 R/W TGR1A I/O Control 0000 1 10 1 100 1 10 1 1000 1 1* 1** TGR1A is output compare register Output disabled Initial output is 0 output Output disabled Initial output is 1 output TGR1A is input capture register Capture input source isTIOCA1 pin Capture input source is TGR0A compare match/ input capture 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at generation of channel 0/TGR0A compare match/ input capture *: Don't care TGR1B I/O Control 0000 1 10 1 100 1 10 1 1*** TGR1B is output compare register Output disabled Initial output is 0 output Output disabled Initial output is 1 output -- Setting prohibited *: Don't care 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match 772 TIER1--Timer Interrupt Enable Register 1 Bit : 7 TTGE Initial value : R/W : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W H'FF24 3 -- 0 -- 2 -- 0 -- 1 TGIEB 0 R/W 0 TPU1 TGIEA 0 R/W TGR Interrupt Enable A 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 Interrupt requests (TCIV) by TCFV disabled 1 Interrupt requests (TCIV) by TCFV enabled Underflow Interrupt Enable 0 Interrupt requests (TCIU) by TCFU disabled 1 Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 A/D conversion start request generation disabled 1 A/D conversion start request generation enabled 773 TSR1--Timer Status Register 1 Bit : 7 TCFD Initial value : R/W : 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* H'FF25 3 -- 0 -- 2 -- 0 -- 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU1 Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 1 [Setting condition] When TCNT = TGRB while TGRB is functioning as output compare register Overflow Flag 0 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Underflow Flag 0 [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) Count Direction Flag 0 TCNT counts down 1 TCNT counts up Note: * Can only be written with 0 for flag clearing. 774 TCNT1--Timer Counter 1 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FF26 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU1 0 0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note : * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. In other cases they function as up-counters. TGR1A--Timer General Register 1A TGR1B--Timer General Register 1B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FF28 H'FF2A 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU1 0 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 775 TCR2--Timer Control Register 2 Bit : 7 -- Initial value : R/W : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W H'FF30 3 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPU2 CKEG1 CKEG0 TPSC0 0 R/W Time Prescaler 000 1 10 1 100 1 10 1 Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Setting prohibited Internal clock: counts on o/1024 Note: This setting is ignored when channel 2 is in phase counting mode. Select the Input Clock Edge 0 1 0 Count at rising edge 1 Count at falling edge -- Count at both edges Note: The internal clock edge selection is valid when the input clock is o/4 or slower. This setting is ignored if the input clock is o/1, or when overflow/underflow of another channel is selected. Counter Clear 00 1 10 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 776 TMDR2--Timer Mode Register 2 Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- H'FF31 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W TPU2 0 MD0 0 R/W Mode 0000 1 10 1 100 1 10 1 1*** Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Setting prohibited *: Don't care Note: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channel 2. In this case, 0 should always be written to MD2. 777 TIOR2--Timer I/O Control Register 2 Bit : 7 IOB3 Initial value : R/W : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FF32 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W TPU2 0 IOA0 0 R/W TGR2A I/O Control 0000 1 10 1 100 1 10 1 1*00 1 1* TGR2A is output compare register Output disabled Initial output is 0 output Output disabled Initial output is 1 output TGR2A is input capture register Capture input source isTIOCA2 pin 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care TGR2B I/O Control 0000 1 10 1 100 1 10 1 1*** TGR2B is output compare register Output disabled Initial output is 0 output Output disabled Initial output is 1 output -- Setting prohibited *: Don't care 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match 778 TIER2--Timer Interrupt Enable Register 2 Bit : 7 TTGE Initial value : R/W : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W H'FF34 3 -- 0 -- 2 -- 0 -- 1 TGIEB 0 R/W 0 TPU2 TGIEA 0 R/W TGR Interrupt Enable A 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 Interrupt requests (TCIV) by TCFV disabled 1 Interrupt requests (TCIV) by TCFV enabled Underflow Interrupt Enable 0 Interrupt requests (TCIU) by TCFU disabled 1 Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 A/D conversion start request generation disabled 1 A/D conversion start request generation enabled 779 TSR2--Timer Status Register 2 Bit : 7 TCFD Initial value : R/W : 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 H'FF35 3 -- 0 -- 2 -- 0 -- 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU2 R/(W)* Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 1 [Setting condition] When TCNT = TGRB while TGRB is functioning as output compare register Overflow Flag 0 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Underflow Flag 0 [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) Count Direction Flag 0 TCNT counts down 1 TCNT counts up Note: * Can only be written with 0 for flag clearing. 780 TCNT2--Timer Counter 2 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FF36 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU2 0 0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note : * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. In other cases they function as up-counters. TGR2A--Timer General Register 2A TGR2B--Timer General Register 2B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FF38 H'FF3A 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU2 0 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 781 TCR0--Timer Control Register 0 TCR1--Timer Control Register 1 Bit : 7 CMIEB Initial value: R/W : 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W H'FF68 H'FF69 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 TMR0 TMR1 CKS0 0 R/W Clock Select 000 1 10 1 100 1 10 1 Clock input disabled Internal clock, counted at falling edge of o/8 Internal clock, counted at falling edge of o/64 Internal clock, counted at falling edge of o/8192 For channel 0: count at TCNT1 overflow signal* For channel 1: count at TCNT0 compare match A* Setting prohibited Setting prohibited Setting prohibited Note: If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting. Counter Clear 00 1 10 1 Clear is disabled Clear by compare match A Clear by compare match B Setting prohibited Timer Overflow Interrupt Enable 0 OVF interrupt requests (OVI) are disabled 1 OVF interrupt requests (OVI) are enabled Compare Match Interrupt Enable A 0 CMFA interrupt requests (CMIA) are disabled 1 CMFA interrupt requests (CMIA) are enabled Compare Match Interrupt Enable B 0 CMFB interrupt requests (CMIB) are disabled 1 CMFB interrupt requests (CMIB) are enabled 782 TCSR0--Timer Control/Status Register 0 TCSR1--Timer Control/Status Register 1 TCSR0 Bit : 7 CMFB Initial value : R/W TCSR1 Bit : 7 CMFB Initial value : R/W : 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 -- 1 -- : 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ADTE 0 R/W H'FF6A H'FF6B TMR0 TMR1 3 -- 0 R/W 2 -- 0 R/W 1 -- 0 R/W 0 -- 0 R/W 3 -- 0 R/W 2 -- 0 R/W 1 -- 0 R/W 0 -- 0 R/W Reserved Only 0 should be written to these bits A/D Trigger Enable (TCSR0 Only) 0 A/D converter start requests by compare match A are disabled 1 A/D converter start requests by compare match A are enabled Timer Overflow Flag 0 [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 to OVF 1 [Setting condition] Set when TCNT overflows from H'FF to H'00 Compare Match Flag A 0 [Clearing conditions] * Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA * When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0 1 [Setting condition] Set when TCNT matches TCORA Compare Match Flag B 0 [Clearing conditions] * Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB * When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 1 [Setting condition] Set when TCNT matches TCORB Note: * Only 0 can be written to bits 7 to 5, to clear these flags. 783 TCORA0--Time Constant Register A0 TCORA1--Time Constant Register A1 TCORA0 Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 H'FF6C H'FF6D TCORA1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 TMR0 TMR1 Initial value: R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB0--Time Constant Register B0 TCORB1--Time Constant Register B1 TCORB0 Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FF6E H'FF6F TCORB1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TMR0 TMR1 0 1 Initial value: R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT0--Timer Counter 0 TCNT1--Timer Counter 1 TCNT0 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 H'FF70 H'FF71 TCNT1 6 0 5 0 4 0 3 0 2 0 1 0 0 0 TMR0 TMR1 Initial value: R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 784 TCSR0--Timer Control/Status Register H'FF74(W) H'FF74(R) 4 -- 1 -- 3 -- 1 -- 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W WDT0 Bit : 7 OVF 0 6 WT/IT 0 R/W 5 TME 0 R/W Initial value : R/W : R/(W)*1 Clock Select CKS2 CKS1 CKS0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Clock o/2 (Initial value) o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 Overflow Period*2 (when o = 10 MHz) 51.2 s 1.6 ms 3.2 ms 13.2 ms 52.4 ms 209.8 ms 838.8 ms 3.36 s Note: *2 The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. Timer Enable 0 TCNT is initialized to H'00 and count operation is halted 1 TCNT counts Timer Mode Select 0 Interval timer mode: Interval timer interrupt (WOVI) request is sent to CPU when TCNT overflows 1 Watchdog timer mode: Internal reset can be selected when TCNT overflows* Note: * For details of case where TCNT overflows in watchdog timer mode. See section 12.2.3, Reset Control/Status Register (RSTCSR). Overflow Flag 0 [Clearing conditions] * Read TCSR when OVF = 1, then write 0 in OVF*2 1 [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. Notes: *1 Only 0 can be written, to clear the flag. *2 When the OVF flag is polled with the interval timer interrupt disabled, read the OVF bit while it is 1 at least twice. TCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on Register Access. 785 TCNT0--Timer Counter H'FF74(W) H'FF75(R) 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W WDT0 Bit : 7 0 R/W 0 0 R/W Initial value : R/W : RSTCSR--Reset Control/Status Register H'FF76(W) H'FF77(R) 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- WDT0 Bit : 7 WOVF 0 R/(W)* 6 RSTE 0 R/W 5 -- 0 R/W 0 -- 1 -- Initial value : R/W : Reserved Only 0 should be written to this bit Reset Enable 0 No internal reset when TCNT overflows* 1 Internal reset is generated when TCNT overflows Note: * The chip is not reset internally, but TCNT and TCSR in WDT0 are reset. Watchdog Overflow Flag 0 [Clearing condition] Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF 1 [Setting condition] When TCNT overflows (from H'FF to H'00) in watchdog timer mode Note: * Only 0 can be written, to clear the flag. RSTCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on Register Access. 786 SMR0--Serial Mode Register 0 Bit : 7 C/A Initial value : R/W : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF78 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 SCI0 CKS0 0 R/W Clock Select 0 1 0 o clock 1 o/4 clock 0 o/16 clock 1 o/64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop Bit Length 0 1 stop bit Parity Mode 0 Even parity*1 1 Odd parity*2 Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. *2 When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd. Parity Enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled* Note: * When the PE bit is set to 1, an even or odd parity bit is added to transmit data according to the even or odd parity mode selection by the O/E bit, and the parity bit in receive data is checked to see if it matches the even or odd mode selected by the O/E bit. Character Length 0 8-bit data 1 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible to choose between LSB-first or MSB-first transfer. Selects Asynchronous Mode or Clocked Synchronous Mode 0 Asynchronous mode 1 Clocked synchronous mode 1 2 stop bits 787 BRR0--Bit Rate Register 0 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF79 3 1 R/W 2 1 R/W 1 1 R/W 0 1 SCI0 Initial value : R/W : R/W Sets the serial transfer bit rate Note: For details, see section 13.2.8, Bit Rate Register (BRR) 788 SCR0--Serial Control Register 0 Bit : 7 TIE Initial value : R/W : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W H'FF7A 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W SCI0 Clock Enable 0 0 Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode 1 0 Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode Transmit End Interrupt Enable 0 Transmit end interrupt (TEI) request disabled*3 1 Transmit end interrupt (TEI) request enabled*3 Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When MPB= 1 data is received 1 Multiprocessor interrupts enabled*4 Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. Receive Enable 0 Reception disabled*5 1 Reception enabled*6 Transmit Enable 0 Transmission disabled*7 1 Transmission enabled*8 Receive Interrupt Enable 0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled*9 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 Transmit data empty interrupt (TXI) requests disabled 1 Transmit data empty interrupt (TXI) requests enabled Note: TXI cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or by clearing the TIE bit to 0. Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input 789 Notes: *1 Outputs a clock of the same frequency as the bit rate. *2 Inputs a clock with a frequency 16 times the bit rate. *3 TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0. *4 When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR, is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. *5 Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. *6 Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the receive format before setting the RE bit to 1. *7 The TDRE flag in SSR is fixed at 1. *8 In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transmit format before setting the TE bit to 1. *9 RXI and ERI cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0. 790 TDR0--Transmit Data Register 0 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF7B 3 1 R/W 2 1 R/W 1 1 R/W 0 1 SCI0 Initial value : R/W : R/W Stores data for serial transmission 791 SSR0--Serial Status Register 0 Bit : 7 TDRE Initial value : R/W : 1 R/(W)*1 6 RDRF 0 5 ORER 0 4 FER 0 3 PER 0 H'FF7C 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W SCI0 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit is received Transmit End 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] 1 * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character Parity Error 0 [Clearing condition] When 0 is written to PER after reading PER = 1 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR*2 Framing Error 0 [Clearing condition] * When 0 is written to FER after reading FER = 1 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0*3 Overrun Error 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1*4 Receive Data Register Full 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] 1 When serial reception ends normally and receive data is transferred from RSR to RDR Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Transmit Data Register Empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR 792 Notes: *1 Only 0 can be written, to clear the flag. *2 If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. *3 In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. *4 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued either. 793 RDR0--Receive Data Register 0 Bit : 7 0 R 6 0 R 5 0 R 4 0 R H'FF7D 3 0 R 2 0 R 1 0 R 0 0 R SCI0 Initial value : R/W : Stores received serial data SCMR0--Smart Card Mode Register 0 Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'FF7E 3 SDIR 0 R/W 2 -- 0 R/W 1 -- 1 -- 0 -- 0 SCI0 R/W Reserved Only 0 should be written to these bits Selects the Serial/Parallel Conversion Format 0 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first 794 SMR1--Serial Mode Register 1 Bit : 7 C/A Initial value : R/W : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF80 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 SCI1 CKS0 0 R/W Clock Select 0 1 0 o clock 1 o/4 clock 0 o/16 clock 1 o/64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop Bit Length 0 1 stop bit Parity Mode 0 Even parity*1 1 Odd parity*2 Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. *2 When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd. Parity Enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled* Note: * When the PE bit is set to 1, an even or odd parity bit is added to transmit data according to the even or odd parity mode selection by the O/E bit, and the parity bit in receive data is checked to see if it matches the even or odd mode selected by the O/E bit. Character Length 0 8-bit data 1 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible to choose between LSB-first or MSB-first transfer. Selects Asynchronous Mode or Clocked Synchronous Mode 0 Asynchronous mode 1 Clocked synchronous mode 1 2 stop bits 795 BRR1--Bit Rate Register 1 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF81 3 1 R/W 2 1 R/W 1 1 R/W 0 1 SCI1 Initial value : R/W : R/W Sets the serial transfer bit rate Note: For details, see section 13.2.8, Bit Rate Register (BRR) 796 SCR1--Serial Control Register 1 Bit : 7 TIE Initial value : R/W : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W H'FF82 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W SCI1 Clock Enable 0 0 Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode 1 0 Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input Transmit End Interrupt Enable 0 Transmit end interrupt (TEI) request disabled*3 1 Transmit end interrupt (TEI) request enabled*3 Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When MPB= 1 data is received 1 Multiprocessor interrupts enabled*4 Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. Receive Enable 0 Reception disabled*5 1 Reception enabled*6 Transmit Enable 0 Transmission disabled*7 1 Transmission enabled*8 Receive Interrupt Enable 0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled*9 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 Transmit data empty interrupt (TXI) requests disabled 1 Transmit data empty interrupt (TXI) requests enabled Note: TXI cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or by clearing the TIE bit to 0. 797 Notes: *1 Outputs a clock of the same frequency as the bit rate. *2 Inputs a clock with a frequency 16 times the bit rate. *3 TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0. *4 When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR, is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. *5 Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. *6 Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the receive format before setting the RE bit to 1. *7 The TDRE flag in SSR is fixed at 1. *8 In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transmit format before setting the TE bit to 1. *9 RXI and ERI cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0. 798 TDR1--Transmit Data Register 1 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF83 3 1 R/W 2 1 R/W 1 1 R/W 0 1 SCI1 Initial value : R/W : R/W Stores data for serial transmission 799 SSR1--Serial Status Register 1 Bit : 7 TDRE Initial value : R/W : 1 R/(W)*1 6 RDRF 0 5 ORER 0 4 FER 0 3 PER 0 H'FF84 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W SCI1 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit is received Transmit End 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character Parity Error 0 [Clearing condition] When 0 is written to PER after reading PER = 1 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR*2 Framing Error 0 [Clearing condition] * When 0 is written to FER after reading FER = 1 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0*3 Overrun Error 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1*4 Receive Data Register Full 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Transmit Data Register Empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR 800 Notes: *1 Only 0 can be written, to clear the flag. *2 If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. *3 In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. *4 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued either. 801 RDR1--Receive Data Register 1 Bit : 7 0 R 6 0 R 5 0 R 4 0 R H'FF85 3 0 R 2 0 R 1 0 R 0 0 R SCI1 Initial value : R/W : Stores received serial data SCMR1--Smart Card Mode Register 1 Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'FF86 3 SDIR 0 R/W 2 -- 0 R/W 1 -- 1 -- 0 -- 0 SCI1 R/W Reserved Only 0 should be written to these bits Selects the Serial/Parallel Conversion Format 0 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first 802 ADDRAH --A/D Data Register AH ADDRAL --A/D Data Register AL ADDRBH --A/D Data Register BH ADDRBL --A/D Data Register BL ADDRCH --A/D Data Register CH ADDRCL --A/D Data Register CL ADDRDH --A/D Data Register DH ADDRDL --A/D Data Register DL Bit : 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 7 0 R 6 0 R 5 0 R 4 -- 0 R 3 -- 0 R A/D Converter 2 -- 0 R 1 -- 0 R 0 -- 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- Initial value : R/W : Store the results of A/D conversion Analog Input Channel Group 1 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD Group 0 803 ADCSR--A/D Control/Status Register Bit : 7 ADF Initial value : R/W : 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W H'FF98 3 -- 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W A/D Converter 0 CH0 0 R/W Channel Select Channel Group Selection Selection CH2 0 Description Scan Mode AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 1 CH1 CH0 Single Mode AN0 (Initial value) 0 0 AN1 1 AN2 1 0 AN3 1 AN4 0 0 AN5 1 AN6 1 0 AN7 1 Reserved Only 0 should be written to this bit Scan Mode 0 Single mode 1 Scan mode A/D Start 0 * A/D conversion stopped 1 * Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends * Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. A/D Interrupt Enable 0 A/D conversion end interrupt (ADI) request disabled 1 A/D conversion end interrupt (ADI) request enabled A/D End Flag 0 [Clearing conditions] * When 0 is written to the ADF flag after reading ADF = 1 * When the DTC is activated by an ADI interrupt and ADDR is read 1 [Setting conditions] * Single mode: When A/D conversion ends * Scan mode: When A/D conversion ends on all specified channels Note: * Only 0 can be written, to clear this flag. 804 ADCR--A/D Control Register Bit : 7 TRGS1 Initial value : R/W : 0 R/W 6 TRGS0 0 R/W 5 -- 1 -- 4 -- 1 -- H'FF99 3 CKS1 0 R/W 2 CKS0 0 R/W 1 -- 1 -- A/D Converter 0 -- 1 -- Clock Select CKS1 CKS0 0 0 1 1 0 1 Description Conversion time = 530 states (max.) Conversion time = 260 states (max.) Conversion time = 134 states (max.) Conversion time = 68 states (max.) Timer Trigger Select A/D conversion start by software is enabled 00 A/D conversion start by TPU conversion start trigger is enabled 1 A/D conversion start by 8-bit timer conversion start trigger is enabled 10 A/D conversion start by external trigger pin (ADTRG) is enabled 1 805 TCSR1--Timer Control/Status Register 1 Bit : 7 OVF Initial value : R/W 0 : R/(W)*1 6 WT/IT 0 R/W 5 TME 0 R/W 4 PSS 0 R/W 3 RST/NMI 0 R/W 2 CKS2 0 R/W H'FFA2 1 CKS1 0 R/W 0 CKS0 0 R/W WDT1 Clock Select Clock Overflow Period 0 o/2 51.2 s*1 1 o/64 1.6 ms*1 1 0 o/128 3.2 ms*1 1 o/512 13.2 ms*1 1 0 0 o/2048 52.4 ms*1 1 o/8192 209.8 ms*1 1 0 o/32768 838.8 ms*1 1 o/131072 3.36 s*1 3.2 ms*3 1 0 0 0 oSUB/2 6.7 ms*2 6.4 ms*3 1 oSUB/4 13.3 ms*2 12.8 ms*3 1 0 oSUB/8 26.7 ms*2 25.6 ms*3 1 oSUB/16 53.3 ms*2 51.2 ms*3 1 0 0 oSUB/32 106.7 ms*2 102.4 ms*3 1 oSUB/64 213.3 ms*2 204.8 ms*3 1 0 oSUB/128 426.7 ms*2 409.6 ms*3 1 oSUB/256 853.3 ms*2 Notes: *1 The time from TCNT starting to count up from H'00 until it overflows, when o = 10 MHz. *2 The time from TCNT starting to count up from H'00 until it overflows, when oSUB = 76.8 kHz. *3 The time from TCNT starting to count up from H'00 until it overflows, when oSUB = 160 kHz. 0 0 0 Power-on Reset or NMI 0 An NMI interrupt is requested 1 A power-on reset is requested Prescaler Select 0 TCNT counts o-based prescaler (PSM) divided clock pulses 1 TCNT counts oSUB-based prescaler (PSS) divided clock pulses Timer Enable 0 TCNT is initialized to H'00 and count operation is halted 1 TCNT counts Timer Mode Select 0 Interval timer mode: Interval timer interrupt (WOVI) request is sent to CPU when TCNT overflows 1 Watchdog timer mode: Power-on reset or NMI interrupt request is sent to CPU when TCNT overflows Overflow Flag 0 [Clearing conditions] * Write 0 in the TME bit * Read TCSR when OVF = 1, then write 0 in OVF*2 1 [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the interval reset. Notes: *1 Only 0 can be written to clear the flag. *2 When the OVF flag is polled with the interval timer interrupt disabled, read the OVF bit while it is 1 at least twice. PSS CKS2 CKS1 CKS0 TCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on Register Access. 806 TCNT1--Timer Counter 1 H'FFA2 (Write) H'FFA3 (Read) 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W WDT1 Bit : 7 0 R/W 0 0 R/W Initial value : R/W : 807 FLMCR1--Flash Memory Control Register 1 Bit : 7 FWE Initial value : R/W : --* R 6 SWE1 0 R/W 5 ESU1 0 R/W 4 PSU1 0 R/W 3 EV1 0 R/W H'FFA8 2 PV1 0 R/W 1 E1 0 R/W 0 P1 0 R/W FLASH Program 0 1 Exits program mode. Enters program mode. [Setting] When FWE=1, SWE1=1, and PSU1=1. Erase 1 0 1 Exits erase mode. Enters erase mode. [Setting] When FWE=1, SWE1=1, and ESU1=1. Program verify 1 0 1 Exits program verify mode. Enters program verify mode. [Setting] When FWE=1 and SWE1=1. Erase verify 1 0 1 Exits erase verify mode. Enters erase verify mode. [Setting] When FWE=1 and SWE1=1 Program setup bit 1 0 1 Exits program setup. Program setup. [Setting] When FWE=1 and SWE1=1. Erase setup bit 1 0 1 Exits erase setup. Erase setup. [Setting] When FWE=1 and SWE1=1. Software write enable bit 1 0 1 Writing disabled. Writing enabled. [Setting] When FWE=1. Flash write enable bit 0 1 When LOW level signal input to FWE pin (hardware protect status). When HIGH level signal input to FWE pin. Note: * Determined by the state of pin FWE. 808 FLMCR2--Flash Memory Control Register 2 Bit : 7 FLER Initial value : R/W : 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R H'FFA9 3 -- 0 R 2 -- 0 R 1 -- 0 R FLASH 0 -- 0 R Flash memory error 0 Flash memory operating normally. Flash memory protection against writing and erasing (error protection) is ignored. [Clearing] At a power-on reset and in hardware standby mode. Shows that an error has occurred when writing to or erasing flash memory. Flash memory protection against writing and erasing (error protection) is enabled. [Setting] See "17.10.3 Error Protection." 1 EBR1--Erase Block Register 1 Bit : 7 EB7 Initial value : R/W : 0 R/W 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W H'FFAA 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W FLASH 0 EB0 0 R/W EBR2--Erase Block Register 2 Bit : 7 -- Initial value : R/W : 0 R/W 6 -- 0 R/W 5 -- 0 R/W 4 -- 0 R/W H'FFAB 3 -- 0 R/W 2 -- 0 R/W 1 EB9 0 R/W FLASH 0 EB8 0 R/W FLPWCR--Flash Memory Power Control Register Bit : 7 PDWND Initial value : R/W : 0 R/W 6 -- 0 R 5 -- 0 R 4 -- 0 R H'FFAC 3 -- 0 R 2 -- 0 R 1 -- 0 R FLASH 0 -- 0 R Power down disable 0 1 Transition to flash memory power-down mode enabled Transition to flash memory power-down mode disabled PDWND is enabled in subactive mode or subsleep mode. It is disabled in other mode. Note: 809 PORT1--Port 1 Register Bit : 7 -- Initial value : Undefined R/W : -- 6 P16 --* R 5 -- Undefined -- 4 P14 --* R H'FFB0 3 P13 --* R 2 P12 --* R 1 P11 --* R 0 Port 1 P10 --* R State of port 1 pins Note: * Determined by the state of pins P16, P14 to P10. PORT3--Port 3 Register Bit : 7 -- R/W : -- 6 -- R 5 P35 --* R 4 P34 --* R H'FFB2 3 P33 --* R 2 P32 --* R 1 P31 --* R 0 Port 3 P30 --* R Initial value : Undefined Undefined State of port 3 pins Note: * Determined by the state of pins P35 to P30. PORT4--Port 4 Register Bit : 7 P47 Initial value : R/W : --* R 6 P46 --* R 5 P45 --* R 4 P44 --* R H'FFB3 3 P43 --* R 2 P42 --* R 1 P41 --* R 0 Port 4 P40 --* R State of port 4 pins Note: * Determined by the state of pins P47 to P40. 810 PORT7--Port 7 Register Bit : 7 -- Initial value : Undefined R/W : R 6 P76 --* R 5 -- R 4 -- R H'FFB6 3 -- R 2 -- -- 1 -- -- 0 Port 7 -- -- Undefined Undefined Undefined Undefined Undefined Undefined State of MISO for FLEXTM decoder II Note: * Determined by the state of MISO for FLEXTM decoder II. PORTA--Port A Register Bit : 7 -- R/W : -- 6 -- -- 5 -- -- 4 -- -- H'FFB9 3 PA3 --* R 2 PA2 --* R 1 PA1 --* R Port A 0 PA0 --* R Initial value : Undefined Undefined Undefined Undefined State of port A pins Note: * Determined by the state of pins PA3 to PA0. PORTB--Port B Register Bit : 7 PB7 Initial value : R/W : --* R 6 PB6 --* R 5 PB5 --* R 4 PB4 --* R H'FFBA 3 PB3 --* R 2 PB2 --* R 1 PB1 --* R Port B 0 PB0 --* R State of port B pins Note: * Determined by the state of pins PB7 to PB0. PORTC--Port C Register Bit : 7 PC7 Initial value : R/W : --* R 6 PC6 --* R 5 PC5 --* R 4 PC4 --* R H'FFBB 3 PC3 --* R 2 PC2 --* R 1 PC1 --* R Port C 0 PC0 --* R State of port C pins Note: * Determined by the state of pins PC7 to PC0. 811 PORTD--Port D Register Bit : 7 PD7 Initial value : R/W : --* R 6 PD6 --* R 5 PD5 --* R 4 PD4 --* R H'FFBC 3 PD3 --* R 2 PD2 --* R 1 PD1 --* R Port D 0 PD0 --* R State of port D pins Note: * Determined by the state of pins PD7 to PD0. PORTE--Port E Register Bit : 7 PE7 Initial value : R/W : --* R 6 PE6 --* R 5 PE5 --* R 4 PE4 --* R H'FFBD 3 PE3 --* R 2 PE2 --* R 1 PE1 --* R Port E 0 PE0 --* R State of port E pins Note: * Determined by the state of pins PE7 to PE0. PORTF--Port F Register Bit : 7 PF7 Initial value : R/W : --* R 6 PF6 --* R 5 PF5 --* R 4 PF4 --* R H'FFBE 3 PF3 --* R 2 PF2 --* R 1 PF1 --* R 0 Port F PF0 --* R State of port F pins Note: * Determined by the state of pins PF7 to PF0. PORTG--Port G Register Bit : 7 -- R/W : -- 6 -- -- 5 -- -- 4 PG4 --* R H'FFBF 3 PG3 --* R 2 PG2 --* R 1 PG1 --* R 0 Port G PG0 --* R Initial value : Undefined Undefined Undefined State of port G pins and READY for FLEXTM decoder II Note: * Determined by the state of pins PG4 to PG1 and READY for FLEXTM decoder II. 812 Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagrams Reset Internal address bus R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1 P1n * TPU module Output compare output/ PWM output enable Output compare output/ PWM output Modes 4 to 6 Internal data bus Bus controller Address output enable RDR1 RPOR1 Input capture input Legend WDDR1 : Write to P1DDR WDR1 : Write to P1DR RDR1 : Read P1DR RPOR1 : Read port 1 n = 0 or 1 Note: * Priority order: Output compare/PWM output > DR output Figure C.1 (a) Port 1 Block Diagram (Pins P10 and P11) 813 Reset Internal address bus R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C Modes 4 to 6 P1n * WDR1 Internal data bus Bus controller Address output enable TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input External clock input Legend WDDR1 : Write to P1DDR WDR1 : Write to P1DR RDR1 : Read P1DR RPOR1 : Read port 1 n = 2 or 3 Note: * Priority order: Output compare/PWM output > DR output Figure C.1 (b) Port 1 Block Diagram (Pins P12 and P13) 814 Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1 P1n * TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Internal data bus Input capture input Interrupt controller IRQ interrupt input Legend WDDR1 : Write to P1DDR WDR1 : Write to P1DR RDR1 : Read P1DR RPOR1 : Read port 1 n = 4 or 6 Note: * Priority order: Output compare/PWM output > DR output Figure C.1 (c) Port 1 Block Diagram (Pins P14 and P16) 815 C.2 Port 3 Block Diagrams Reset R Q D P3nDDR C WDDR3 Reset R Q D P3nDR C WDR3 Reset Open-drain control signal R Q D P3nODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data RDR3 P3n * RPOR3 Legend WDDR3 : Write to P3DDR WDR3 : Write to P3DR WODR3 : Write to P3ODR RDR3 : Read P3DR RPOR3 : Read port 3 RODR3 : Read P3ODR n = 0 or 3 Note: * Priority order: Serial transmit data output > DR output Figure C.2 (a) Port 3 Block Diagram (Pins P30 and P33) 816 Internal data bus Output enable signal Reset R Q D P3nDDR C WDDR3 Reset * P3n R Q D P3nDR C WDR3 Reset Open-drain control signal R Q D P3nODR C WODR3 RODR3 Internal data bus SCI module Serial receive data enable Serial receive data Output enable signal RDR3 RPOR3 Legend WDDR3 : Write to P3DDR WDR3 : Write to P3DR WODR3 : Write to P3ODR RDR3 : Read P3DR RPOR3 : Read port 3 RODR3 : Read P3ODR n = 1 or 4 Note: * Priority order: Serial receive data input > DR output Figure C.2 (b) Port 3 Block Diagram (Pins P31 and P34) 817 Reset R Q D P3nDDR C WDDR3 Reset R Q D P3nDR C WDR3 Open-drain control signal Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial clock output enable Serial clock output RDR3 Serial clock input enable Internal data bus Serial clock input Interrupt controller IRQ interrupt input Output enable signal P3n * RPOR3 Legend WDDR3 : Write to P3DDR WDR3 : Write to P3DR WODR3 : Write to P3ODR RDR3 : Read P3DR RPOR3 : Read port 3 RODR3 : Read P3ODR n = 2 or 5 Note: * Priority order: Serial clock input > Serial clock output > DR output Figure C.2 (c) Port 3 Block Diagram (Pins P32 and P35) 818 Reset R Q D P36DDR C Internal data bus FLEXTM decoder II WDDR3 Reset SS R Q D P36DR C WDR3 RDR3 Legend WDDR3 : Write to P3DDR WDR3 : Write to P3DR RDR3 : Read P3DR Figure C.2 (d) Port 3 Block Diagram (Pin P36) 819 C.3 Port 4 Block Diagram RPOR4 P4n Internal data bus A/D converter module Analog input Legend RPOR4 : Read port n= 0 to 7 Figure C.3 Port 4 Block Diagram (Pins P40 to P47) 820 C.4 Port 7 Block Diagrams Reset R Q D P74DDR C Internal data bus FLEXTM decoder II WDDR7 Reset RESET R Q D P74DR C WDR7 RDR7 Legend WDDR7 : Write to P7DDR WDR7 : Write to P7DR RDR7 : Read P7DR Figure C.4 (a) Port 7 Block Diagram (Pin P74) 821 Reset R Q D P75DDR C Internal data bus SCI module Serial clock output enable Serial clock output Serial clock input enable FLEXTM decoder II WDDR7 Reset R Q D P75DR C WDR7 RDR7 SCK * Legend WDDR7 : Write to P7DDR WDR7 : Write to P7DR RDR7 : Read P7DR Note: * Priority order: Serial clock output > DR output Figure C.4 (b) Port 7 Block Diagram (Pin P75) 822 RPOR7 MISO Internal data bus FLEXTM decoder II SCI module Serial receive data enable Serial receive data Legend RPOR7 : Read port 7 Figure C.4 (c) Port 7 Block Diagram (Pin P76) 823 Reset R Q D P77DDR C Internal data bus SCI module Serial transmit enable Serial transmit data FLEXTM decoder II WDDR7 Reset R Q D P77DR C WDR7 RDR7 MOSI * Legend WDDR7 : Write to P7DDR WDR7 : Write to P7DR RDR7 : Read P7DR Note: * Priority order: Serial transmit data output > DR output Figure C.4 (d) Port 7 Block Diagram (Pin P77) 824 C.5 Port A Block Diagrams Reset R Q D PAnPCR C WPCRA RPCRA Reset Output enable signal R Q D PAnDDR C WDDRA Reset R Q D PAnDR C WDRA Reset Open-drain control signal R Q D PAnODR C WODRA RODRA PAn * Modes 4 to 6 Internal address bus Bus controller Address output enable RDRA RPORA Legend WDDRA : Write to PADDR WDRA : Write to PADR WODRA : Write to PAODR WPCRA : Write to PAPCR RDRA : Read PADR RPORA : Read port A RODRA : Read PAODR RPCRA : Read PAPCR n = 0 to 3 Note: * Priority order: Address output > DR output Figure C.5 Port A Block Diagram (Pins PA0 and PA3) 825 Internal data bus C.6 Port B Block Diagram Reset R Q D PBnPCR C WPCRB RPCRB Reset Output enable signal R Q D PBnDDR C WDDRB Reset R Q D PBnDR C WDRB Modes 4 to 6 PBn * Internal address bus Bus controller Address output enable RDRB RPORB Legend WDDRB : Write to PBDDR WDRB : Write to PBDR WPCRB : Write to PBPCR RDRB : Read PBDR RPORB : Read port B RPCRB : Read PBPCR n = 0 to 7 Note: * Priority order: Address output > DR output Figure C.6 Port B Block Diagram (Pins PB0 to PB7) 826 Internal data bus C.7 Port C Block Diagram Reset R Q D PCnPCR C WPCRC RPCRC Modes 4 and 5* Reset Output enable signal R S Q D PCnDDR C WDDRC Reset R Q D PCnDR C WDRC PCn Mode 7 Modes 4 to 6 RDRC RPORC Legend WDDRC : Write to PCDDR WDRC : Write to PCDR WPCRC : Write to PCPCR RDRC : Read PCDR RPORC : Read port C RPCRC : Read PCPCR n = 0 to 7 Note: * Set priority Figure C.7 Port C Block Diagram (Pins PC0 to PC7) Internal address bus Internal data bus 827 C.8 Port D Block Diagram Reset Internal upper data bus Internal lower data bus R Q D PDnPCR C WPCRD RPCRD Reset R Q D PDnDDR C WDDRD Reset R Q D PDnDR C WDRD External address write PDn Mode 7 Modes 4 to 6 External address upper write External address lower write RDRD RPORD External address upper read External address lower read Legend WDDRD : Write to PDDDR WDRD : Write to PDDR WPCRD : Write to PDPCR RDRD : Read PDDR RPORD : Read port D RPCRD : Read PDPCR n = 0 to 7 Figure C.8 Port D Block Diagram (Pins PD0 to PD7) 828 C.9 Port E Block Diagram Reset Internal upper data bus Internal lower data bus R Q D PEnPCR C WPCRE RPCRE Reset R Q D PEnDDR C WDDRE Reset R Q D PEnDR C WDRE 8-bit bus mode RDRE External address write PEn Mode 7 Modes 4 to 6 RPORE External address lower read Legend WDDRE : Write to PEDDR WDRE : Write to PEDR WPCRE : Write to PEPCR RDRE : Read PEDR RPORE : Read port E RPCRE : Read PEPCR n = 0 to 7 Figure C.9 Port E Block Diagram (Pins PE0 to PE7) 829 C.10 Port F Block Diagrams Reset Internal data bus Bus controller BRLE output Bus request input Interrupt controller IRQ interrupt input R Q D PF0DDR C WDDRF Reset PF0 R Q D PF0DR C Modes 4 to 6 WDRF RDRF RPORF Legend WDDRF WDRF RDRF RPORF : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Figure C.10 (a) Port F Block Diagram (Pin PF0) 830 Reset Internal data bus Bus controller BRLE output Bus request acknowledge output WDT1 module BUZZ output enable BUZZ output R Q D PF1DDR C WDDRF Reset PF1 * Modes 4 to 6 R Q D PF1DR C WDRF RDRF RPORF Legend WDDRF WDRF RDRF RPORF : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Note: * Priority order: Bus request acknowledge output > BUZZ output > DR output Figure C.10 (b) Port F Block Diagram (Pin PF1) 831 Reset R Q D PF2DDR C WDDRF Reset PF2 R Q D PF2DR C Modes 4 to 6 WDRF Bus controller Wait enable RDRF RPORF Internal data bus Wait input Legend WDDRF WDRF RDRF RPORF : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Figure C.10 (c) Port F Block Diagram (Pin PF2) 832 Reset R Q D PF3DDR C WDDRF Reset PF3 R Q D PF3DR C WDRF Bus controller LWR output 16 bit bus mode Modes 4 to 6 RDRF RPORF A/D converter ADTRG input Interrupt controller IRQ interrupt input Legend WDDRF WDRF RDRF RPORF : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Figure C.10 (d) Port F Block Diagram (Pin PF3) Internal data bus 833 Reset R Q D PFnDDR C WDDRF Reset Mode 7 PFn Modes 4 to 6 R Q D PFnDR C WDRF Internal data bus Bus controller PF4: HWR output PF5: RD output PF6: AS output Modes 4 to 6 RDRF RPORF Legend WDDRF : Write to PFDDR WDRF : Write to PFDR RDRF : Read PFDR RPORF : Read port F n = 4 to 6 Figure C.10 (e) Port F Block Diagram (Pins PF4 to PF6) 834 Modes 4 to 6* Reset S R Q D PF7DDR C WDDRF Reset PF7 R Q D PF7DR C WDRF o RDRF RPORF Legend WDDRF : Write to PFDDR WDRF : Write to PFDR RDRF : Read PFDR RPORF : Read port F Note: * Set priority Figure C.10 (f) Port F Block Diagram (Pin PF7) Internal data bus 835 C.11 Port G Block Diagrams RPORG READY Internal data bus Interrupt controller IRQ interrupt input FLEXTM decoder II Legend RPORG : Read port G Figure C.11 (a) Port G Block Diagram (Pin PG0) 836 Reset R Q D PG1DDR C WDDRG Reset Mode 7 PG1 Modes 4 to 6 R Q D PG1DR C WDRG Internal data bus Bus controller Chip select Interrupt controller IRQ interrupt input RDRG RPORG Legend WDDRG WDRG RDRG RPORG : Write to PGDDR : Write to PGDR : Read PGDR : Read port G Figure C.11 (b) Port G Block Diagram (Pin PG1) 837 Reset R Q D PGnDDR C WDDRG Reset Mode 7 PGn Modes 4 to 6 R Q D PGnDR C WDRG Internal data bus Bus controller Chip select RDRG RPORG Legend WDDRG : Write to PGDDR WDRG : Write to PGDR RDRG : Read PGDR RPORG : Read port G n = 2 or 3 Figure C.11 (c) Port G Block Diagram (Pins PG2 and PG3) 838 Modes Modes 4 and 5 6 and 7 Reset WDDRG Reset Mode 7 PG4 Modes 4 to 6 R Q D PG4DR C WDRG Internal data bus Bus controller Chip select SR Q D PG4DDR C RDRG RPORG Legend WDDRG WDRG RDRG RPORG : Write to PGDDR : Write to PGDR : Read PGDR : Read port G Figure C.11 (d) Port G Block Diagram (Pin PG4) 839 Appendix D Pin States D.1 Port States in Each Processing State I/O Port States in Each Processing State MCU Hardware Operating Power-On Standby Mode Reset Mode 4 to 7 7 T T T T Software Standby Mode, Bus-Released Watch Mode State keep keep keep keep Program Execution State, Sleep Mode, Subsleep Mode I/O port I/O port Table D.1 Port Name Pin Name P16, P14 P13/TIOCD0/TCLKB/A23 P12/TIOCC0/TCLKA/A22 P11/TIOCB0/A21 Address output selected by AEn bit Port selected P10/TIOCA0/A20 Address output selected by AEn bit Port selected P36 (dedicated internal I/O port for FLEXTM decoder II) P35 to P30 Port 4 P77, P75, P74 (dedicated internal I/O port for FLEXTM decoder II) P76 (dedicated internal input port for FLEXTM decoder II) Port A Address output selected by AEn bit Port selected Port B Address output selected by AEn bit Port selected 4 to 6 T T [OPE= 0] T [OPE= 1] keep keep keep [OPE= 0] T [OPE= 1] keep keep keep T Address output 4 to 6 7 4, 5 6 T T L T T T T keep keep T I/O port I/O port Address output 4 to 6 4 to 7 T* H T H keep keep I/O port I/O port 4 to 7 4 to 7 4 to 7 T T L T T L keep T keep keep T keep I/O port Input port I/O port 4 to 7 MISO MISO MISO MISO Input port 7 4, 5 6 T L T T T keep [OPE= 0] T [OPE= 1] keep keep keep [OPE= 0] T [OPE= 1] keep keep keep T I/O port Address output 4 to 6 7 4, 5 6 T* T L T T T T keep keep T I/O port I/O port Address output 4 to 6 T* T keep I/O port 840 Port Name Pin Name Port C MCU Hardware Operating Power-On Standby Mode Reset Mode 4, 5 L T Software Standby Mode, Bus-Released Watch Mode State [OPE= 0] T [OPE= 1] keep [DDR*OPE= 0] T [DDR*OPE= 1] keep keep T keep keep T keep [DDR= 0] Input port [DDR= 1] H [DDR= 0] Input port [DDR= 1] H [OPE= 0] T [OPE= 1] H keep keep keep [OPE= 0] T [OPE= 1] H [WAITE= 0] keep [WAITE= 1] T keep [BRLE= 0] keep [BRLE= 1] H keep T Program Execution State, Sleep Mode, Subsleep Mode Address output 6 T T T [DDR = 0] Input port [DDR = 1] Address output I/O port Data bus I/O port I/O port Data bus I/O port [DDR= 0] Input port [DDR= 1] Clock output [DDR= 0] Input port [DDR= 1] Clock output AS, RD, HWR 7 Port D 4 to 6 7 Port E 8-bit bus 16-bit bus 4 to 6 4 to 6 7 PF7/o 4 to 6 T T T T T T T T T T T T keep T keep keep T keep [DDR= 0] Input port [DDR= 1] Clock output [DDR= 0] Input port [DDR= 1] Clock output T Clock output T 7 T T PF6/AS, PF5/RD, PF4/HWR 4 to 6 H T 7 PF3/LWR/ADTRG/ IRQ3 8-bit bus 16-bit bus 7 4 to 6 4 to 6 T T (Mode 4) H (Modes 5 and 6) T T T T T keep keep keep T I/O port I/O port I/O port LWR PF2/WAIT 4 to 6 T T [WAITE= 0] keep [WAITE= 1] T keep L [WAITE= 0] I/O port [WAITE= 1] WAIT I/O port [BRLE= 0] I/O port [BRLE= 1] BACK I/O port 7 PF1/BACK/BUZZ 4 to 6 T T T T 7 T T keep 841 Port Name Pin Name PF0/BREQ/IRQ2 MCU Hardware Operating Power-On Standby Mode Reset Mode 4 to 6 T T Software Standby Mode, Bus-Released Watch Mode State [BRLE= 0] keep [BRLE= 1] T keep [DDR*OPE= 0] T [DDR*OPE= 1] H T Program Execution State, Sleep Mode, Subsleep Mode [BRLE= 0] I/O port [BRLE= 1] BREQ I/O port [DDR = 0] Input port [DDR = 1] CS0 (In sleep mode and subsleep mode: H) I/O port [DDR= 0] Input port [DDR= 1] CS1 to CS3 I/O port Input port 7 PG4/CS0 4, 5 6 T H T T T keep T 7 PG3/CS1 PG2/CS2 PG1/CS3/IRQ7 4 to 6 T T T T keep [DDR*OPE= 0] T [DDR*OPE= 1] H keep READY keep T 7 PG0/IRQ6 (dedicated 4 to 7 internal input port for FLEXTM decoder II) T READY T READY keep READY Legend: H: High level L: Low level T: High impedance keep: Input port becomes high-impedance, output port retains state DDR Data direction register OPE: Output port enable WAITE: Wait input enable BRLE: Bus release enable Note: * L in modes 4 and 5 (address output) 842 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at least 10 states before the STBY signal goes low, as shown below. RES must remain low until STBY signal goes low (delay from STBY low to RES high: 0 ns or more). STBY t110tcyc RES t20ns Figure E.1 Timing of Transition to Hardware Standby Mode (2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained, RES does not have to be driven low as in (1). Timing of Recovery from Hardware Standby Mode Drive the RES signal low approximately 100 ns or more before STBY goes high to execute a power-on reset. STBY t100ns RES tOSC Figure E.2 Timing of Recovery from Hardware Standby Mode 843 Appendix F Product Code Lineup Table F.1 H8S/2276 Series Product Code Lineup Product Code Non-roaming Roaming HD64F2277 HD64F2277R Package TFP-100B, TFP-100G Product Type H8S/2277 H8S/2277R 844 Appendix G Package Dimensions Figures G.1 and G.2 show the LSI package dimensions. Unit: mm 16.0 0.2 14 75 76 51 50 16.0 0.2 100 1 *0.22 0.05 0.20 0.04 25 0.08 M 26 0.5 *0.17 0.05 0.15 0.04 1.20 Max 1.00 1.0 1.0 0.5 0.1 0 - 8 0.10 0.10 0.10 *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC JEITA Mass (reference value) TFP-100B - Conforms 0.5 g Figure G.1 TFP-100B Package Dimensions 845 14.0 0.2 12 75 76 51 50 Unit: mm 14.0 0.2 100 1 *0.18 0.05 0.16 0.04 25 0.07 M 26 0.4 1.2 *0.17 0.05 0.15 0.04 1.20 Max 1.00 1.0 0- 8 0.5 0.1 0.10 0.10 0.10 *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC JEITA Mass (reference value) TFP-100G - Conforms 0.4 g Figure G.2 TFP-100G Package Dimensions 846 H8S/2276 Series, H8S/2277 F-ZTATTM Hardware Manual Publication Date: 1st Edition, December 2001 Published by: Business Planning Division Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright (c) Hitachi, Ltd., 2001. All rights reserved. Printed in Japan. |
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